CN200980092Y - A frequency shift keying demodulator based on the locked loops of a password lock - Google Patents
A frequency shift keying demodulator based on the locked loops of a password lock Download PDFInfo
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- CN200980092Y CN200980092Y CN 200620150020 CN200620150020U CN200980092Y CN 200980092 Y CN200980092 Y CN 200980092Y CN 200620150020 CN200620150020 CN 200620150020 CN 200620150020 U CN200620150020 U CN 200620150020U CN 200980092 Y CN200980092 Y CN 200980092Y
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Abstract
The utility model relates to a frequency-shift key-control demodulator based on digit phase-locked loop, characterized in that an extract filter (A) which can directly sample middle-frequency signal is connected with an input of a digit phase-locked loop, while an output of the digit phase-locked loop is connected with an input of the extract filter (B), an output of the extract filter (B) is respectively connected with an input of a zero-crossing detector and an input of a data clock recovery and frequency micro adjuster, an output of the zero-crossing detector is connected with another input of the data clock recovery and frequency micro adjuster, a micro adjust signal output of the data clock recovery and frequency micro adjuster is connected with a feedback input of the digit phase-locked loop. The utility model overcomes the defects of analogue receive demodulation method, with the advantages of high integration, small volume, low power consumption, and low cost or the like. And the utility model uses digit phase-locked loop demodulation method to obtain higher stability and lower error code rate than orthogonal frequency detection method.
Description
Technical field
The utility model belongs to wireless communication technology and digital integrated circuit field, especially a kind of FSK demodulator based on digital phase-locked loop.
Background technology
Traditional frequency shift keying (FSK) demodulator is to adopt arrowband analog fm receiver to carry out demodulation process to receiving the signal that comes mostly, recovers data then from the analog signal that demodulates.This analoglike FM receiver generally is to adopt the mode of quadrature frequency discrimination (quadrature discriminator), need an external phase shifter or ceramic discriminator, therefore there are power consumption height, the low cost problem of higher that reaches of big, the integrated degree of volume, and there is threshold effect in this receiver separating timing, there is poor stability, influenced the demodulation performance of receiver.
Summary of the invention
The purpose of the utility model patent is to overcome the deficiencies in the prior art, and a kind of FSK demodulator based on digital phase-locked loop is provided.
The utility model solves its technical problem and takes following technical scheme to realize:
Should be based on the FSK demodulator of digital phase-locked loop, it is characterized in that: the input that can directly connect digital phase-locked loop the decimation filter (A) of if signal sampling, the output of digital phase-locked loop connects the input of decimation filter (B), the output of this decimation filter (B) connects the input of zero-crossing detector respectively and data clock recovers and an input of frequency trim device, this zero-crossing detector output is connected to data clock and recovers and another input of frequency trim device, and the fine adjustment signal output of this data clock recovery and frequency trim device is connected to the feedback input end of digital phase-locked loop.
And described digital phase-locked loop is connected and composed successively by phase discriminator, loop filter, digital adder and digital vco.
Advantage of the present utility model and good effect are:
1. the utility model circuit is digital form, has integrated level height, volume is little, low in energy consumption, cost is low advantage.
2. the utility model circuit adopts the digital phase-locked loop demodulation mode to have the advantages that than quadrature frequency detection mode the demodulation working stability is reliable, the error rate is low.
Description of drawings
Fig. 1 is a circuit block diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing the utility model embodiment is further described:
As shown in Figure 1, FSK demodulator based on digital phase-locked loop, by decimation filter A, digital phase-locked loop, decimation filter (B), zero-crossing detector, data clock recovers and the frequency trim device constitutes, the input that can directly connect digital phase-locked loop to the decimation filter (A) of if signal sampling, the output of digital phase-locked loop connects the input of decimation filter (B), the output of this decimation filter (B) connects the input of zero-crossing detector respectively and data clock recovers and an input of frequency trim device, this zero-crossing detector output is connected to data clock and recovers and another input of frequency trim device, and the fine adjustment signal output of this data clock recovery and frequency trim device is connected to the feedback input end of digital phase-locked loop.Wherein, digital phase-locked loop 1 is connected and composed successively by phase discriminator, loop filter, digital adder and digital vco.
Basic functional principle of the present utility model is: decimation filter (A) is directly to the intermediate-freuqncy signal high-speed sampling, by obtaining low speed 6bit digital signal behind high-speed sampling and the filtering extraction; Phase discriminator, loop filter, digital adder and digital vco constitute digital phase-locked loop, adopt the method for this digital phase-locked loop to carry out frequency shift keying (FSK) demodulation; Decimation filter (B) is used for the signal of digital phase-locked loop output is done further processing, is equivalent to the effect of matched filtering, has improved demodulation performance; Zero-crossing detector is used to extract zero crossing phase information and output signal; Data clock recovers and the frequency trim device, signal and zero crossing counter output signal according to decimation filter (B) output, extract the bit synchronization clock and be used to recover data and clock, and after extracting frequency error signal and carrying out Filtering Processing, the signal feedback that obtains is used for frequency trim to digital phase-locked loop.
The utility model course of work is as follows:
The analog if signal S that decimation filter (A) provides prime
1(t) carry out high-speed sampling after, obtain low speed 6bit digital signal S
2(n), this decimation filter (A) filtering even-order harmonic component and high fdrequency component, the spectral aliasing problem when avoiding sampling; Phase discriminator, loop filter, digital vco and digital adder constitute digital phase-locked loop together, frequency shift keying (FSK) signal are carried out demodulation, as the output signal S of digital vco
9(n) and input signal S
2When phase place (n) was inconsistent, the phase demodulation effect by the phase discriminator realized by digital multiplier obtained error signal S
3(n), loop filter carries out filtering to this error signal and obtains S
4(n), feed back to digital vco, to change its output signal S
9(n) phase place makes S
9(n) can follow the tracks of S
2(n) phase change, the S of digital phase-locked loop output
4(n) be the signal that preliminary demodulation obtains; Decimation filter (B) adopts moving average filter (Moving Average filter) to realize, to S
4(n) noise in further suppresses, to S
4(n) carry out low-pass filtering and down-sampled, obtain S
5(n); Zero-crossing detector is used to extract S
5(n) the zero crossing phase information in, output signal S
6(n); Data clock recovery and frequency trim device are according to S
5(n) and S
6(n), recover data DATA, clock CLK, and extract frequency error signal, after Filtering Processing, obtain signal S
7(n), feed back to digital phase-locked loop, be used for frequency trim.
The utility model excellent performance carries out demodulation to the frequency shift keying (FSK) of frequency modulation index (FM index) h=0.7, and when Eb/N0=10dB, the error rate (BER) is 10
-3
Decimation filter described in the utility model (A), phase discriminator, loop filter, digital vco, digital adder, decimation filter (B), data clock recover with the frequency trim device and are connected to be prior art, do not provide concrete circuit structure in an embodiment.
Present embodiment is illustrative; rather than it is determinate; therefore can not limit protection range of the present utility model according to this, every by those skilled in the art according to other execution modes that the technical solution of the utility model draws, belong to the scope of the utility model protection equally.
Claims (2)
1. FSK demodulator based on digital phase-locked loop, it is characterized in that: the input that can directly connect digital phase-locked loop the decimation filter (A) of if signal sampling, the output of digital phase-locked loop connects the input of decimation filter (B), the output of this decimation filter (B) connects the input of zero-crossing detector respectively and data clock recovers and an input of frequency trim device, this zero-crossing detector output is connected to data clock and recovers and another input of frequency trim device, and the fine adjustment signal output of this data clock recovery and frequency trim device is connected to the feedback input end of digital phase-locked loop.
2. the FSK demodulator based on digital phase-locked loop according to claim 1 is characterized in that: described digital phase-locked loop is connected and composed successively by phase discriminator, loop filter, digital adder and digital vco.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620150020 CN200980092Y (en) | 2006-11-27 | 2006-11-27 | A frequency shift keying demodulator based on the locked loops of a password lock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620150020 CN200980092Y (en) | 2006-11-27 | 2006-11-27 | A frequency shift keying demodulator based on the locked loops of a password lock |
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| Publication Number | Publication Date |
|---|---|
| CN200980092Y true CN200980092Y (en) | 2007-11-21 |
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| CN 200620150020 Expired - Fee Related CN200980092Y (en) | 2006-11-27 | 2006-11-27 | A frequency shift keying demodulator based on the locked loops of a password lock |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101917188A (en) * | 2010-07-29 | 2010-12-15 | 西安空间无线电技术研究所 | A method for self-recovery locking of demodulator |
| CN102055699A (en) * | 2010-10-25 | 2011-05-11 | 清华大学 | Demodulation method for frequency shift keying and device for realizing same |
| CN103124247A (en) * | 2011-11-21 | 2013-05-29 | 国民技术股份有限公司 | Signal demodulating system, receiver and demodulation filtering method |
| CN106487395A (en) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | Multi-mode demodulation system based on FPGA |
| CN106907999A (en) * | 2017-05-04 | 2017-06-30 | 合肥工业大学 | A kind of grating sensor displacement measurement system based on phase-modulation |
-
2006
- 2006-11-27 CN CN 200620150020 patent/CN200980092Y/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101917188A (en) * | 2010-07-29 | 2010-12-15 | 西安空间无线电技术研究所 | A method for self-recovery locking of demodulator |
| CN102055699A (en) * | 2010-10-25 | 2011-05-11 | 清华大学 | Demodulation method for frequency shift keying and device for realizing same |
| CN102055699B (en) * | 2010-10-25 | 2013-01-30 | 清华大学 | Frequency Shift Keying Demodulation Method and Implementation Device |
| CN103124247A (en) * | 2011-11-21 | 2013-05-29 | 国民技术股份有限公司 | Signal demodulating system, receiver and demodulation filtering method |
| CN103124247B (en) * | 2011-11-21 | 2016-06-22 | 国民技术股份有限公司 | A kind of signal demodulating system, receptor and demodulation filtering method |
| CN106487395A (en) * | 2016-10-18 | 2017-03-08 | 哈尔滨工业大学 | Multi-mode demodulation system based on FPGA |
| CN106907999A (en) * | 2017-05-04 | 2017-06-30 | 合肥工业大学 | A kind of grating sensor displacement measurement system based on phase-modulation |
| CN106907999B (en) * | 2017-05-04 | 2019-11-15 | 合肥工业大学 | A Grating Sensor Displacement Measurement System Based on Phase Modulation |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071121 Termination date: 20101127 |