CN1992087B - Parts testing device and method and interface apparatus thereof - Google Patents
Parts testing device and method and interface apparatus thereof Download PDFInfo
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- CN1992087B CN1992087B CN2006100809416A CN200610080941A CN1992087B CN 1992087 B CN1992087 B CN 1992087B CN 2006100809416 A CN2006100809416 A CN 2006100809416A CN 200610080941 A CN200610080941 A CN 200610080941A CN 1992087 B CN1992087 B CN 1992087B
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- 238000012360 testing method Methods 0.000 title claims abstract description 211
- 238000000034 method Methods 0.000 title abstract description 9
- 238000012546 transfer Methods 0.000 claims abstract description 13
- 230000001360 synchronised effect Effects 0.000 claims description 15
- 238000001514 detection method Methods 0.000 claims description 8
- 230000003139 buffering effect Effects 0.000 claims description 7
- 230000001105 regulatory effect Effects 0.000 claims description 7
- 230000001276 controlling effect Effects 0.000 claims description 5
- 101150097994 hagh gene Proteins 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000003860 storage Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000013101 initial test Methods 0.000 description 1
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- 230000014759 maintenance of location Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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Abstract
The present invention relates to a device testing appratus and method, and an interface eqipment. The device testing appratus includes: a performance board for installing the tested devices and inputting/outputting signals aiming at the tested devices; a host for generatering the testing wave of the tested devices; a header for transmitting the test signal based on the testing wave to the performance board, and receiving a test result signal from the performance board corresponding to the test signal; an interface part set between the header and the performance board, for changing the transfer speed of the test signal and the test result signal according to the operating speed of the tested device. Thereby the hagh speed testing can be carried on with low cost.
Description
Technical field
The present invention relates to device testing apparatus and method and interface arrangement thereof, relate in particular to device testing apparatus and the method and the interface arrangement thereof that can carry out high speed test by lower cost.
Background technology
Fig. 1 is the block diagram of existing device testing apparatus 10 structures of expression.Device testing apparatus 10 may be for being used to test the memorizer test device of Double Data Rate synchronous DRAM storeies such as (DDR SDRAM:double-data-rate synchronous dynamic random access memory).As shown in Figure 1, device testing apparatus 10 comprises: main frame (main frame) 11, to be used for by the action generation test logic of working out and to produce desired test waveform; Head (head) 12, the device (hereinafter to be referred as " DUT (Device Under Test) ") that is fed to the needs test with the test waveform that is used for being produced is gone up and is received from the data of DUT (14) output; Be used to install the performance board (performance board) 13 of DUT (14).Main frame 11 comprises test control part 111, pulse efferent 112, test pattern efferent 113 and waveform generating unit 114.Head (head) 12 comprises drive division 121, comparing section 122 and DC determination part 123.
When device 14 is storer, usually whether three kinds of tests can be roughly carried out in true(-)running for testing memory, and these three kinds of tests specifically comprise the DC characteristic, test storage unit of testing memory, and whether defectiveness, testing memory drive (hereinafter referred to as " At-Speed Test ") according to the operating rate identical with reality.
When the DC characteristic of test DUT (14), the DC characteristic of the DC determination part 123 test DUT (14) of head 12, and test result is sent on the main frame 11, main frame 11 is judged the quality of DUT (14) according to this result.
Test storage unit whether defectiveness and At-Speed Test is tested in the following manner.That is, device testing apparatus 10 is fed to desired test waveform (following also claim " test data ") after the particular address as the storer of DUT (14), read again be stored in this particular address data to confirm whether this reading of data correct.If there is defective in DUT in (14), then be fed to the test data of DUT (14) and the data that read from DUT (14) different, device testing apparatus 10 is judged to be defective device with corresponding D UT (14).
Device testing apparatus 10 is in the following order to DUT (14) supply test waveform.The test waveform target program that the test control part 111 of main frame 11 will be worked out in advance sends to test pattern efferent 113.The order that test pattern efferent 113 is worked out according to target program produces logical data.Test control part 111 is in order to work out out the operation Waveform Control waveform generating unit 114 of DUT (14), makes its logical data that test pattern efferent 113 is produced be formatted as desired test waveform and exports.In addition, test control part 111 gating pulse efferents 112 are so that it produces the pulse corresponding to the test waveform of being exported.
The drive division 121 of head 12 receives formative test waveform, and by driving make test waveform have can the actual DUT of driving (14) enough big electric current, be sent to DUT (14) by performance board 13 then.
Device testing apparatus 10 reads data based on test result (following also claim " test result signal " or " test result data ") from DUT (14) in the following order.The comparing section 122 of head 12 receives test result data from DUT (14) output by performance board 13, and measures the size of test result data and be sent on the main frame 11.Main frame 11 is judged the quality of DUT (14) by relatively more initial test waveform that produces and received test result data.
Yet, when carrying out the At-Speed Test in aforesaid DUT (14) test, have only when the drive division 121 of the test pattern efferent 113 of main frame 11 and waveform generating unit 114, head 12 and comparing section 122 and performance board 13 according to " At-Speed " promptly according to the real work speed operation of DUT (14), just can correctly test.
Therefore, along with storer is accelerated gradually through DDR (200MHz), DDR2 (400MHz), DDR3 developing stage speed such as (800MHz), the travelling speed of device testing apparatus 10 also needs corresponding increase.But device testing apparatus 10 is usually designed to the structure of the DUT (14) of a plurality of kinds that test characteristic has nothing in common with each other, thereby is difficult to replace main frame 11 and head 12.Device testing apparatus at a high speed 10 needs the cost of exploitation for a long time and great number to realize.In addition, the situation that also may exist main frame 11 and head 12 can't replace on the structural design.
Summary of the invention
The present invention proposes in order to solve aforesaid problem, and its purpose is to provide a kind of device testing apparatus and the method and interface arrangement thereof that can carry out high speed test with low cost.
To achieve these goals, comprise according to device testing apparatus provided by the present invention: performance board, being used to install measured device, and I/O is at the signal of described measured device; Main frame is to be used to produce the test waveform of described measured device; Head being used for that the test signal based on described test waveform is sent to described performance board, and receives the test result signal that transmits from described performance board corresponding to described test signal; Be installed in the interface portion between described head and the described performance board, described interface portion comprises: frequency multiplication portion, to be used to the described frequency test signal that doubles; Described test result signal is carried out the frequency division department of frequency division; Control part is to be used for controlling described frequency multiplication portion and described frequency division department based on the operating rate of described measured device.
And described interface portion can increase the transfer rate of described test signal, and can reduce the transfer rate of described test result signal.
And described interface portion can comprise: the first I/O portion, transmit with the signal that is used between interface connection and the described head; The second I/O portion transmits with the signal that is used between interface connection and the described performance board.
And described interface portion can comprise the data buffering portion that is used to store described test result signal data.Described interface portion also comprises the strobe pulse generating unit that is used to produce strobe signal, and described control part can be controlled described strobe pulse generating unit, so that it produces the described strobe signal corresponding to described measured device operating rate.
And described interface portion can comprise distortion (skew) adjusting portion, to be used for regulating the distortion status of described test signal and at least a signal of described test result signal.Described measured device can comprise Double Data Rate synchronous DRAM (DDR SDRAM:double-data-rate synchronous dynamic random access memory).
To achieve these goals, interface arrangement according to device testing apparatus provided by the present invention, this device testing apparatus have be used to install measured device and I/O at the performance board of the signal of described measured device, be used for the test signal based on predetermined test waveform is sent to described performance board and receives the head of the test result signal that transmits from described performance board corresponding to described test signal, it is characterized in that comprising: be used for interface connect with described head between the first I/O portion of signal transmission; Be used for the second I/O portion that the signal between interface connection and the described performance board transmits; Velocity variations portion, described velocity variations portion comprises: frequency multiplication portion, to be used to the described frequency test signal that doubles; Described test result signal is carried out the frequency division department of frequency division; Control part is to be used for controlling described frequency multiplication portion and described frequency division department based on the operating rate of described measured device.
And described velocity variations portion can increase the transfer rate of described test signal, and can reduce the transfer rate of described test result signal.
And described velocity variations portion can comprise the data buffering portion that is used to store described test result signal data.Described velocity variations portion also comprises the strobe pulse generating unit that is used to produce strobe signal, and described control part can be controlled described strobe pulse generating unit, so that it produces the described strobe signal corresponding to described measured device operating rate.
And described velocity variations portion can comprise distortion (skew) adjusting portion, to be used for regulating the distortion status of described test signal and at least a signal of described test result signal.Described measured device can comprise Double Data Rate synchronous DRAM (DDR SDRAM:double-data-rate synchronous dynamic random access memory).
To achieve these goals, adopt device detection method according to device testing apparatus provided by the present invention, this device testing apparatus have be used to install measured device and I/O at the performance board of the signal of described measured device, be used for the test signal based on predetermined test waveform is sent to described performance board and receives the head of the test result signal that transmits from described performance board corresponding to described test signal, it is characterized in that comprising step: receive the described test signal that transmits by first speed from described head; The second speed that received test signal is doubled described frequency test signal by the operating rate based on described measured device and obtain is sent to described performance board; Receive described test result signal by described second speed from described performance board; Described first speed that received test result signal is obtained by based on the operating rate of described measured device described test result signal being carried out frequency division is sent to described head.
And described second speed can be faster than first speed.
And the step that described test result signal is sent to described head can comprise the step of storing described test result signal data.The step that described test result signal is sent to described head can comprise the step that operating rate according to described measured device produces the step of strobe signal and receives described test result signal according to described strobe signal from described performance board.
And described device detection method can also comprise the step of regulating the distortion status of at least a signal in described test signal and the described test result signal.Described measured device can comprise Double Data Rate synchronous DRAM (DDR SDRAM:double-data-rate synchronous dynamic random access memory).
Description of drawings
Fig. 1 is the block diagram of the existing device testing apparatus structure of expression;
Fig. 2 is the block diagram of expression according to the device testing apparatus structure that one embodiment of the invention provided;
Fig. 3 is the process flow diagram of expression according to the device testing apparatus action that one embodiment of the invention provided.
Embodiment
Below, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.Fig. 2 is the block diagram of expression according to device testing apparatus 20 structures that one embodiment of the invention provided.Device testing apparatus 20 comprises main frame 21, head 22, performance board 23 and interface portion 25.Device testing apparatus 20 may be for being used to test the memorizer test device of Double Data Rate synchronous DRAM storeies such as (DDR SDRAM:double-data-rate synchronous dynamic random access memory).
The test signal that head 22 will form based on the test waveform that is transmitted by main frame 21 is sent to performance board 23, and receives the test result signal that is transmitted by performance board 23 corresponding to test signal, is sent on the main frame 21 again.The test signal that present embodiment provided by driving make test waveform have can the actual DUT of driving (24) enough big size of current.The head 22 that present embodiment provided has the structure similar with head shown in Figure 1 12.That is, head 22 can comprise drive division 121, comparing section 122 and DC determination part 123.When DUT (24) is Double Data Rate synchronous DRAM (DDR SDRAM), the test signal of present embodiment comprise clock (CLK), address (ADDR), data (DQs), control signal (/RAS ,/CAS, DQS) etc.
DUT (24) is installed on the performance board 23, is used to carry out I/O at the signal of DUT (24).
The signal that the first I/O portion 251 is used between interface connection and the head 22 transmits.The identical action in order to carry out transmitting signals with performance board 23 time of the first I/O portion 251 with head 22, according to head 22 and performance board 23 between the identical agreement of communication protocol carry out signal with head 22 and transmit.When DUT (24) was the Double Data Rate synchronous DRAM, the first input and output portion 251 can be realized by ddr interface.
The signal that the second I/O portion 252 is used between interface connection and the performance board 23 transmits.The second I/O portion 252 comprises the 252a of frequency multiplication portion of the frequency test signal that is used to double.The 252a of frequency multiplication portion can doubly increase the phase-locked loop of signal speed (PLL:phase locked loop) realization by frequency test signal is increased to N.
The second I/O portion 252 is increased to N test signal doubly according to the control of control part 257 with frequency and is fed to the presumptive address of DUT (24), and reads the test result data that is stored in described address.At this moment, control part 257 is based on the operating rate control frequency multiplication 252a of portion of DUT (24).
Strobe pulse generating unit 255 produces strobe signal.When transmitting test result data, for the strobe signal generation time of correct acceptance test result data control part 257 according to the operating rate control strobe pulse generating unit 255 of DUT (24) by DUT (24).The test result data that the 253 interim storages of data buffering portion transmit from DUT (24).
In addition, the 252a of frequency multiplication portion that present embodiment provided, frequency division department 254, data buffering portion 253, strobe pulse generating unit 255 and control part 257 are an example of velocity variations of the present invention portion.
Fig. 3 is the process flow diagram of expression according to device testing apparatus 20 interface connecting methods that present embodiment provided.22 by the first speed acceptance test signal (S11) at first, from the head.Then, according to second speed received test signal is sent to performance board 23 (S12) greater than first speed.At this moment, doubly increase transfer rate by frequency being increased to N.
Secondly, from performance board 23 according to second speed acceptance test consequential signal (S13).Then, according to first speed received test result signal is sent to head 22 (S14).At this moment, be divided into 1/N by frequency and doubly reduce transfer rate the test result signal.
As mentioned above, according to the transfer rate of the present invention, thereby, also can carry out test at a high speed even adopt than the relatively low head 22 of DUT (24) speed at a high speed by change test signal and test result signal between head 22 and performance board 23.
Though, need more expense could increase the speed of device testing apparatus usually, by the less relatively speed variable interface device of setup fee on the low speed devices proving installation, can carry out high speed test with low cost.
In sum, though describe the present invention in detail by preferred embodiment, the present invention is defined in this content, can be implemented in every way in the claim scope.
Claims (19)
1. device testing apparatus is characterized in that comprising:
Performance board, being used to install measured device, and I/O is at the signal of described measured device;
Main frame is to be used to produce the test waveform of described measured device;
Head being used for that the test signal based on described test waveform is sent to described performance board, and receives the test result signal that transmits from described performance board corresponding to described test signal;
Be installed in the interface portion between described head and the described performance board, described interface portion comprises: frequency multiplication portion, to be used to the described frequency test signal that doubles; Described test result signal is carried out the frequency division department of frequency division; Control part is to be used for controlling described frequency multiplication portion and described frequency division department based on the operating rate of described measured device.
2. device testing apparatus according to claim 1 is characterized in that described interface portion increases the transfer rate of described test signal, reduces the transfer rate of described test result signal.
3. device testing apparatus according to claim 1 and 2 is characterized in that described interface portion comprises:
The first I/O portion transmits with the signal that is used between interface connection and the described head;
The second I/O portion transmits with the signal that is used between interface connection and the described performance board.
4. device testing apparatus according to claim 1 and 2 is characterized in that described interface portion comprises the data buffering portion that is used to store described test result signal data.
5. device testing apparatus according to claim 1 and 2, it is characterized in that described interface portion also comprises the strobe pulse generating unit that is used to produce strobe signal, described control part is controlled described strobe pulse generating unit, so that the strobe pulse generating unit produces the described strobe signal corresponding to described measured device operating rate.
6. device testing apparatus according to claim 1 and 2 is characterized in that described interface portion comprises the distortion adjusting portion, to be used for regulating the distortion status of described test signal and at least a signal of described test result signal.
7. device testing apparatus according to claim 1 and 2 is characterized in that described measured device comprises the Double Data Rate synchronous DRAM.
8. a kind of interface arrangement of device testing apparatus, this device testing apparatus have be used to install measured device and I/O at the performance board of the signal of described measured device, be used for the test signal based on predetermined test waveform is sent to described performance board and receives the head of the test result signal that transmits from described performance board corresponding to described test signal, it is characterized in that comprising:
The first I/O portion transmits with the signal that is used between interface connection and the described head;
The second I/O portion transmits with the signal that is used between interface connection and the described performance board;
Velocity variations portion, described velocity variations portion comprises: frequency multiplication portion, to be used to the described frequency test signal that doubles; Described test result signal is carried out the frequency division department of frequency division; Control part is to be used for controlling described frequency multiplication portion and described frequency division department based on the operating rate of described measured device.
9. interface arrangement according to claim 8 is characterized in that described velocity variations portion increases the transfer rate of described test signal, reduces the transfer rate of described test result signal.
10. according to Claim 8 or 9 described interface arrangements, it is characterized in that described velocity variations portion comprises the data buffering portion that is used to store described test result signal data.
11. according to Claim 8 or 9 described interface arrangements, it is characterized in that described velocity variations portion also comprises the strobe pulse generating unit that is used to produce strobe signal, described control part is controlled described strobe pulse generating unit, so that the strobe pulse generating unit produces the described strobe signal corresponding to described measured device operating rate.
12. according to Claim 8 or 9 described interface arrangements, it is characterized in that described velocity variations portion comprises the distortion adjusting portion, to be used for regulating the distortion status of described test signal and at least a signal of described test result signal.
13. according to Claim 8 or 9 described interface arrangements, it is characterized in that described measured device comprises the Double Data Rate synchronous DRAM.
14. utilize a kind of device detection method of device testing apparatus, this device testing apparatus have be used to install measured device and I/O at the performance board of the signal of described measured device, be used for the test signal based on predetermined test waveform is sent to described performance board and receives the head of the test result signal that transmits from described performance board corresponding to described test signal, it is characterized in that comprising step:
Receive the described test signal that transmits by first speed from described head;
The second speed that received test signal is doubled described frequency test signal by the operating rate based on described measured device and obtain is sent to described performance board;
Receive described test result signal by described second speed from described performance board;
Described first speed that received test result signal is obtained by based on the operating rate of described measured device described test result signal being carried out frequency division is sent to described head.
15. device detection method according to claim 14 is characterized in that described second speed is faster than first speed.
16., it is characterized in that the step that described test result signal is sent to described head is comprised the step of storing described test result signal data according to claim 14 or 15 described device detection methods.
17., it is characterized in that the step that described test result signal is sent to described head is comprised according to claim 14 or 15 described device detection methods:
Produce the step of strobe signal according to the operating rate of described measured device;
Receive the step of described test result signal from described performance board according to described strobe signal.
18., it is characterized in that also comprising the step of regulating the distortion status of at least a signal in described test signal and the described test result signal according to claim 14 or 15 described device detection methods.
19., it is characterized in that described measured device comprises the Double Data Rate synchronous DRAM according to claim 14 or 15 described device detection methods.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020050131939A KR100735920B1 (en) | 2005-12-28 | 2005-12-28 | Device test apparatus and method, and its interface apparatus |
| KR1020050131939 | 2005-12-28 | ||
| KR10-2005-0131939 | 2005-12-28 |
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| CN1992087A CN1992087A (en) | 2007-07-04 |
| CN1992087B true CN1992087B (en) | 2010-10-06 |
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| KR101137537B1 (en) | 2008-05-30 | 2012-04-23 | 가부시키가이샤 어드밴티스트 | Tester and information processing system |
| KR101535228B1 (en) | 2009-05-13 | 2015-07-08 | 삼성전자주식회사 | Built-off test equipment |
| KR101281823B1 (en) | 2012-11-30 | 2013-07-04 | 주식회사 아이티엔티 | Automatic test equipment having fixed type power board and exchange type core board |
| US9618577B2 (en) * | 2014-01-03 | 2017-04-11 | Litepoint Corporation | System and method for testing data packet transceivers having varied performance characteristics and requirements using standard test equipment |
| CN106855608B (en) * | 2015-12-09 | 2023-11-14 | 深圳市盛德金科技有限公司 | Dual clock test circuit |
| KR102512985B1 (en) * | 2018-06-12 | 2023-03-22 | 삼성전자주식회사 | Test Apparatus For Semiconductor Device and Method Of Manufacturing Semiconductor Device |
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| CN1204125A (en) * | 1997-06-30 | 1999-01-06 | 三星电子株式会社 | Method for Testing High-Speed Memory Devices Using Clock Modulation Technology |
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| CN1624807A (en) * | 2003-11-19 | 2005-06-08 | 国际商业机器公司 | Automatic bit fail mapping for embedded memories with clock multipliers |
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| KR100272503B1 (en) * | 1998-01-26 | 2000-11-15 | 김영환 | Rambus asic having high speed testing function and testing method thereof |
| KR20030049481A (en) * | 2001-12-15 | 2003-06-25 | 삼성전자주식회사 | Semiconductor device capable of interfacing low-speed test equipment and Test system using the same |
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- 2005-12-28 KR KR1020050131939A patent/KR100735920B1/en active IP Right Grant
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| EP0097781A1 (en) * | 1982-06-18 | 1984-01-11 | International Business Machines Corporation | Testing method for high speed logic designs using low speed tester |
| CN1204125A (en) * | 1997-06-30 | 1999-01-06 | 三星电子株式会社 | Method for Testing High-Speed Memory Devices Using Clock Modulation Technology |
| CN1527948A (en) * | 2001-03-20 | 2004-09-08 | 尼佩泰斯特公司 | Low-jitter clock for test system |
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| KR100735920B1 (en) | 2007-07-06 |
| KR20070069616A (en) | 2007-07-03 |
| CN1992087A (en) | 2007-07-04 |
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