CN1983566A - A stacked thin film transistor non-volatile memory device and its manufacturing method - Google Patents

Abstract

The present invention discloses a stacked non-volatile memory device, which includes a plurality of bit line layers and word line layers stacked on each other. The bit line layer includes a plurality of bit lines, which can be efficiently and economically manufactured using advanced manufacturing technology. The device can be structured to be suitable for NAND operation.

Description

A stacked thin film transistor non-volatile memory device and its manufacturing method

related application

This application claims the priority of the U.S. provisional application filed on December 9, 2005, the application number is No. 60/748,911, the title of the invention is "The Process of TFTNAND and Nitride Read Only Memory", the application is based on Application reference. This application also relates to U.S. Patent Application No.11/425,959 filed on June 22, 2006, whose title of invention is "A Stacked Non-Volatile Memory Device and Methods for Fabricating the Same", which is also listed as the subject of this application refer to.

technical field

Embodiments described herein relate to methods for fabricating thin film transistor nonvolatile memory devices, and more particularly to methods for fabricating thin film transistor nonvolatile memory devices including multilayer memory cells.

Background technique

Non-volatile memory devices are used more and more frequently in products. For example, flash memory devices are used in MP3 players, digital cameras, and as storage devices for computers. As these uses increase, there is a greater need to accommodate large-capacity storage devices in small sizes, which in turn requires the manufacture of high-density storage devices. Accordingly, research and development is directed toward increasing the density of conventional nonvolatile memory devices.

One approach to increasing the density of non-volatile memory devices is to create stacked memory devices, ie, devices with multiple layers of memory cells stacked on top of each other. Unfortunately, so far not a lot of research and development effort has been devoted to producing various stacked memory devices. For example, stacked nitride ROM has only a few designs. This phenomenon can be attributed in part to the fact that stacked memory devices are not fully compatible with recent processes, making their manufacture inefficient and costly.

There are still other ways to increase the density of known non-volatile memory devices, but these ways are not necessarily suitable for all applications. Therefore, there remains a need for a method of increasing the density of known non-volatile memory devices.

One particular type of non-volatile memory device is a nitride read-only memory device. FIG. 1 is a schematic diagram of a known nitride ROM structure 150 . As shown, the NROM 150 is fabricated on a silicon substrate 152 . The substrate can be a P-type silicon substrate or an N-type silicon substrate, however, a P-type silicon substrate is generally preferred for various design reasons. Source/drain regions 154 , 156 may then be implanted in substrate 152 . A trapping structure 158 is then formed over the substrate 152 between the source/drain regions 154 , 156 . A control gate 160 is then formed over trapping structure 158 .

The source/drain regions 154 , 156 are silicon regions doped with the opposite type of dopant to the substrate 152 . For example, when a P-type silicon substrate is used, N-type source/drain regions 154, 156 are implanted.

The charge trapping structure 158 includes a nitride trapping layer, and an insulating oxide layer between the trapping layer and the channel 166 of the substrate 152 . In other embodiments, the trapping structure 158 may include a nitride trapping layer sandwiched between two insulating (dielectric) layers, such as an oxide layer or a silicon dioxide layer. Such structures are commonly referred to as oxide-nitride-oxide (ONO) trapping structures.

Charge can accumulate and be localized within the trapping structure 158 immediately adjacent to the source/drain regions 154, 156, thereby effectively storing two separate and independent charges 162, 164. Each charge 162, 164 can be maintained in one of two states, a programmed state or an erased state, each of which is represented by the presence or absence of a locally trapped electron. This structure allows the storage of two bits of information without the use of complex multi-level cell technology.

Each storage area in the nitride read-only memory cell 150 can be independently programmed without affecting other storage areas. Nitride ROM cells are programmed by applying a voltage such that negatively charged electrons are injected into the nitride layer of trapping structure 158 near one end of the cell. Erasing is accomplished by applying a voltage so that holes are injected into the nitride layer, so that the holes cancel the electrons stored in the nitride layer during previous programming.

Nitride read-only memory devices are constructed by fabricating an array of memory cells as shown in FIG. 1 . The array connects cells together with word lines and bit lines.

Nitride ROM devices, such as the device shown in FIG. 1 , can be configured to store multiple bits in a single cell, so the density of NROM devices can be increased using a stacked structure. Unfortunately, nitride ROM device stacking is rarely implemented, and when it is, the process is inefficient and thus increases manufacturing costs.

Contents of the invention

The present invention discloses a method for fabricating a stacked non-volatile memory device. The disclosed method uses efficient process technology to fabricate the stacked device. therefore. Embodiments of the present invention can be scaled down to allow stacking of different levels of layers.

In one of the objects of the present invention, a stacked nitride ROM can be fabricated using the method of the present invention.

In another object of the present invention, the stacked nitride read-only memory device can be manufactured using silicon-on-insulator (SOI) process technology, such as thin film transistor (TFT) process technology and the like.

In another object of the present invention, the trapping layer included in this stacked nonvolatile memory device may include various structures such as silicon-oxide-nitride-oxide-silicon (SONOS), bandgap Processed SONOS (BE-SONOS), silicon-oxide-nitride-silicon (SONS), high dielectric value materials, etc.

In another object of the present invention, the stacked memory device fabricated by the method of the present invention can be configured to operate with a NAND gate (NAND).

The structure and method of the present invention will be described in detail below. The purpose of this summary of the invention is not to limit the invention. The invention is defined by the appended claims. All embodiments, features, objects and advantages of the present invention will be fully understood through the following description, claims and accompanying drawings.

Description of drawings

FIG. 1 is a known nitride read-only memory structure.

FIG. 2 shows a stacked nitride ROM structure in an embodiment of the present invention.

3-17 illustrate an exemplary process for fabricating the stacked nitride ROM as shown in FIG. 2, according to an embodiment of the present invention.

18A-18H illustrate different trapping structure embodiments that may be included in the device in FIG. 2 .

19A and 19B are band diagrams of the trapping structure of FIG. 18C.

FIG. 20 illustrates another example stacked non-volatile memory structure according to an embodiment of the present invention.

21-31 illustrate example process steps including steps to fabricate the devices of 18A through 18H, according to an embodiment of the invention.

Description of main component symbols

100 Nitride ROM

102 insulation layer

103, 107 trapping layer

104 bit lines

105 word line conductor

106 Insulation area

110 The first bit line layer

120 first word line layer

130 Second bit line layer

140 Second word line layer

150 Nitride ROM structure

152 silicon substrate

154, 156 source/drain regions

158 trapping structure

160 Control grid

162,164 charges

166 channel

202 insulation layer

204 semiconductor layer

206 Overlay

209 medium layer

210, 212 medium area

216 trapping structure

218 word line conductor layer

219 word line

220 source and drain regions

221 P-type area

222 Trapped

224 polysilicon layer

226 medium area

338 trapping structure

230 bit line layer

231 word line conductor layer

232 trapping structure

240-256 non-volatile memory cells

260-270 Additional Units

272, 276, 278, 282, 284, 288 oxide layer

274, 280, 286, 290 Nitride layer

292 medium layer

294 ONO structure

302 Thin oxide layer

304, 308, 318 nitride layer

306, 310, 314, 316 oxide layer

321 OSO structure

322,328 Thin polysilicon layer

324, 326, 330, 334, 336, 340 thin oxide layer

325 Thin OSO structure

328, 332, 338, 342 Thin nitride layer

341 ON structure

2402 medium layer

2404 inter-unit dielectric layer

2406 word line layer

2408 trapping structure

2410 bit line layer

2502 insulation layer

2504 polysilicon layer

2506 bitline regions

2508 Overlay

2510 Coverage area

2508 Trapped structure layer

2510 word line

2512 area

2514 source and drain regions

2516 channel area

2518 Medium layer between units

2520-2526 storage unit

Detailed ways

It should be understood that any dimensions, measurements, ranges, test results, data, etc. stated below are approximate and unless stated otherwise, are not intended to imply exact data. The degree of near reality involved will vary with the nature of the data, the context, and the particular embodiment or application.

FIG. 2 illustrates an example thin film transistor (TFT) stack nitride read only memory 100 according to an implementation example. In the embodiment of FIG. 2 , the stacked nitride ROM 100 is fabricated on the insulating layer 102 . Accordingly, device 100 is fabricated using silicon-on-insulator (SOI) process technology. For example, device 100 may be fabricated using thin film transistor (TFT) process technology. TFT is a special field effect transistor, which is manufactured by depositing thin films on insulating layers as metal contacts, semiconductor active layers, and dielectric layers. The channel region of a TFT is a thin film deposited on a substrate, which is often glass.

Successive bit line layers and word line layers may then be formed over the insulating layer 102 . For example, in FIG. 2 , the first bit line layer 110 is formed on the insulating layer 102 . The first word line layer 120 is then fabricated on the first bit line layer 110 . The second bit line layer 130 is then fabricated on the first word line layer 120 . Finally, the second word line layer 140 is fabricated on the second bit line layer 130 .

Additional bitline and wordline layers can be sequentially fabricated on top of the layers shown in FIG. 2 . Therefore, for the sake of brevity, two bit line layers and two word line layers are shown in the figure, but the method described in the present invention should not be considered as limiting the present invention to a specific number of bit line layers and/or word line layers. Each bitline layer 110 , 130 includes a plurality of bitlines 104 separated by insulating regions 106 . Each wordline layer 120 , 140 includes a wordline conductor 105 sandwiched between trapping layers 103 and 107 .

By using the stacked structure shown in Figure 2, greater storage density can be achieved. Furthermore, as explained below, efficient process means can be used to fabricate the structure 100 .

3-17 illustrate an example sequence of process steps to fabricate structure 100 in accordance with an embodiment of the present invention. As shown in FIG. 3 , a semiconductor layer 204 may be formed on the insulating layer 202 . For example, in some embodiments, insulating layer 202 may include an oxide material. The semiconductor layer 204 may include a P-type semiconductor material, such as silicon, germanium, or silicon germanium. Preferably, the semiconductor layer 204 includes a thin film polysilicon layer deposited on the insulating layer 202 . It can be understood that, in other embodiments, the semiconductor layer 204 may include N-type semiconductor material. A capping layer 206 may then be formed over the semiconductor layer 204 . For example, in certain embodiments, capping layer 206 may include a silicon nitride material.

As shown in FIG. 4 , known lithography techniques can be used to pattern and etch layers 204 and 206 . The figure shows a top view of the various layers in the devices fabricated so far. Fig. 4 is a sectional view taken along line AA' of Fig. 5 . Thus, as shown in FIG. 5 , layers 206 and 204 are patterned and etched into region 205 , which traverses insulating layer 202 from top to bottom. Region 205 will form the bitlines of first bitline layer 110 of FIG. 2 as explained below.

Referring to FIG. 6 , a dielectric layer 209 may then be formed on the insulating layer 202 as shown. For example, the dielectric layer 209 can be an oxide layer such as silicon dioxide, and can be formed by high density plasma chemical vapor deposition (HDP-CVD). Referring to FIG. 7 , a portion of the dielectric layer 209 is removed to expose the remaining portion of the capping layer 206 and the remaining portion of the semiconductor layer 204 . For example, a known wet etching process (ie, isotropic etching) can be used to remove a portion of the dielectric layer 209 . In order to remove the correct amount of dielectric layer 209 , an etching method with a high etch selectivity ratio for dielectric layer 209 and capping layer 206 may be used. The etching process creates dielectric region 210 above capping layer 206 and forms dielectric region 212 between remaining portions of semiconductor layer 204 .

Figure 8 shows a top view of the layers fabricated so far. Fig. 7 is a sectional view taken along line AA'. Thus, as shown in FIG. 8 , dielectric regions 212 are located between regions 205 . As shown, the dielectric region 210 covers a portion of the cover layer 206 .

Referring to FIG. 9 , the remaining portion of capping layer 206 may be removed, while region 210 of dielectric layer 209 is removed in this step. For example, hot phosphoric acid may be used to remove the remaining portion of cap layer 206 . When removing the remaining portion of cover layer 206 , dielectric region 210 of dielectric layer 209 is automatically removed because dielectric region 210 is not connected to dielectric region 212 .

The process shown in Figures 6-9 is described in U.S. Patent No. 6,380,068 "Method for Planarizing a Flash Memory Device," assigned to the applicant of this patent on April 30, 2002, and incorporated herein referenced in this case. The process shown in FIGS. 6-9 can efficiently planarize the remaining surface shown in FIG. 9 . Accordingly, the processes described herein are compatible with newer, more efficient process technologies. This feature will make the fabrication of stacked non-volatile memory devices more efficient and cost-effective.

Figure 10 is a top view of the layers formed so far. Fig. 9 is a sectional view taken along line AA' of Fig. 10 . Consequently, insulating layer 202 is now covered by alternating oxide regions 212 and bitlines 205 formed by the remainder of semiconductor material 204 .

As shown in FIG. 11 , a trapping structure 216 may then be formed over the remaining portion of the semiconductor layer 204 and the insulating region 212 . A word line conductor layer 218 may then be formed over the trapping structure 216 . A silicon nitride layer (not shown) may then be formed over the word line conductor layer 218 . The silicon nitride layer (not shown) and the layers 218, 216 can then be patterned and etched using well-known lithographic techniques. The etch step is performed such that the HDPO region 212 acts as a stop layer for the etch process. Another high density plasma oxide layer may then be formed over these etched layers, including a silicon nitride layer (not shown). The HDP layer may then be partially etched, after which part of the HDP oxide layer and the remaining silicon nitride layer (not shown) are removed to form the word lines 219 shown in FIG. The method is similar to the method shown in Figure 6-9.

In the embodiment of FIG. 11 , trapping structure 216 may comprise a multilayer structure. Embodiments of multilayer structures will be further described when explaining Figures 18A-18H. Therefore, the trapping structure 216 can be formed by successively forming each layer included in the trapping structure 216 .

The word line conductor layer 218 can be formed from N+ or P+ conductor material, such as polysilicon material, polysilicon/silicide/polysilicon material, or metal such as aluminum, copper, or tungsten.

Figure 12 shows a top view of the layers formed so far. Thus, word line 219 overlaps bit line 205 in the figure. Fig. 13 shows a cross-sectional view of the layers in Fig. 12 along line AA'. Fig. 14 shows a sectional view of each layer in Fig. 12 taken along line BB'.

As shown in FIG. 15 , once the wordline 219 is formed over the bitline 205 , source and drain regions 220 may be formed in the semiconductor layer 204 in regions including the bitline 205 not covered by the wordline conductor 218 . Accordingly, the source and drain regions 220 may be implanted and thermally injected into the region 220 of the semiconductor layer 204 . It can be understood that the process of implanting the source and drain regions 220 is a self-aligned process. In the embodiment of FIG. 15 , the source and drain regions should be N+ regions formed by arsenic (As) or phosphorus (P), because the semiconductor layer 204 includes a P-type semiconductor material. It can be understood that, in the embodiment using N-type semiconductor material, a P+-type region must be formed.

After forming the source and drain regions 220 , the semiconductor layer 204 will include an N+ type source/drain region 220 and a P type region under the word line conductor 218 . These P-type regions will become the channel region of a particular memory cell as described below.

Fig. 16 is a sectional view taken along line BB' for each layer formed so far. As shown, the N+ type source/drain regions 220 are formed between the word lines 219 and separated by the dielectric region 212 . Figure 13 shows a cross-sectional view of the layers formed so far along the line AA'. As shown, layer 204 still includes P-type region 221 below wordline conductor 218 .

The layers formed so far will form the non-volatile memory cells 240-256. The source and drain regions of the nonvolatile memory cells 240 - 256 are formed from the N+ source/drain regions 220 on both sides of the associated word line 219 . Referring to FIG. 13, a region 221 in the polysilicon layer 204 of the bit line 205 is formed under the word line 219 to form channel regions of the non-volatile memory cells 240-256. Trapping structures 216 over these channel regions are used to store charge in each cell 240-256. The charge trapping structure is described in more detail with reference to Figures 18A-18H.

Thus, by applying the correct voltages to the word line conductors 218 and the source/drain regions 220, charge can be stored in the trapping structures 216 of the appropriate cells 240-256. Similarly removal of cells 240-256 may be accomplished by applying appropriate voltages to word line conductor 218 and associated source/drain regions 220. Referring now to FIG. The programmed state of cells 240-256 can be obtained by applying appropriate voltages to the appropriate word line conductors 218 and source/drain regions 220.

As shown in FIG. 17, additional memory cells 260-270 may be formed by forming additional bit line layers and word line layers above bit line layer 210 and word line layer 220, respectively. Accordingly, an additional trapping structure 222 may be formed over the wordline conductor 218 , and then an additional bitline layer 230 may be formed over the trapping structure 222 . The bit line layer 230 can be formed using the same steps as the bit line layer 210 described above. Thus, bit line layer 230 will include remaining portions of etched polysilicon layer 224 separated by dielectric regions 226 . The remaining portions of polysilicon layer 224 , shown in FIG. 17 , which form the channel regions of additional cells 260 - 270 , are located below the wordlines of wordline layer 240 .

Source and drain regions may be implanted in the remainder of the polysilicon layer 224 on either side of each wordline in the wordline layer 240 .

By forming trapping structure 228 over the remainder of polysilicon layer 224 and dielectric region 226, forming wordline conductor layer 231 and trapping structure 228, and then forming trapping structure 232 over wordline conductor 231, and A word line layer 240 may be formed. Again, word line layer 240 may be formed using the process techniques described above for word line layer 220 . The memory cells 240-244 of FIG. 15 are shown in FIG. 17 . Thus, the outer memory cells 260-270 are formed in layers above the memory cells 240-244. However, it will be appreciated that devices fabricated according to the systems and methods of the present invention may include any number of layer structures and any number of memory cells.

Due to the use of efficient techniques to form the wordline and bitline layers, the process can be scaled to produce any number of layered structures. Therefore, it can be understood that the second bit line layer and the second word line layer shown in FIG. 17 are only for the sake of simplicity of the drawing.

18A-18H illustrate various embodiments of trapping structures that may be used in device 100. FIG. For example, referring to FIG. 11 , various structures shown in FIGS. 18A-18H may be used as trapping structures 216 . A first example embodiment, shown in FIG. 18A, includes a silicon-oxide-nitride-oxide-silicon (SONOS) structure. The structure includes an oxide layer 272 , a nitride layer 274 , and an oxide layer 276 , which are sequentially formed on the polysilicon layer 204 . The oxide region 272 acts as a channel dielectric layer, and the nitride layer 274 acts as a trapping layer to trap charges. When using the SONOS structure of FIG. 18A , charges are stored in the trapping layer 274 of a particular cell by injecting electrons into the trapping layer 274 . Erasing of the cell is accomplished by tunneling holes directly into the trapping layer 274 to cancel any electrons previously stored in the trapping layer 274 . Hole tunneling in the trapping layer 274 is realized by using the Fuller-Nordham tunneling effect. Oxide layer 272 may be a thin oxide layer, for example, may be less than 3 nanometers thick. For example, cells formed using the SONOS trap structure of FIG. 18A can be used in NAND memory applications.

The NAND device constructed using the SONOS trapping structure shown in FIG. 18A may exhibit poor charge retention because holes directly tunnel into the trapping layer 274 during the charge retention process to generate leakage current.

Figure 18B shows a nitride ROM trap structure. Likewise, the nitride ROM trap structure includes an ONO structure formed by sequentially forming an oxide layer 278 , a nitride layer 280 , and a second oxide layer 282 over the polysilicon region 214 . However, the thickness of the oxide layer 278 here is about 5-7 nm. Programming of cells formed using the nitride ROM structure of FIG. 18B is accomplished by injecting electrons into layer 280 . Cells formed using the nitride ROM structure of FIG. 18B can then be erased using hot hole erase techniques. The nitride read-only memory structure shown in Figure 18B can be used in NOR (or not) applications; however, devices constructed using the nitride read-only memory structure of Figure 18B show the some damage.

Figure 18C shows a bandgap engineered (BE) SONOS structure. The BE-SONOS structure shown in FIG. 18C is formed by successively forming an ONO structure 294 followed by a nitride layer 290 and a dielectric layer 292 . ONO structure 294 is obtained by sequentially forming oxide layer 284 , nitride layer 286 , and oxide layer 288 on polysilicon layer 204 . Like the SONOS structure of FIG. 18A, the BE-SONOS structure of FIG. 18C uses the Fuller-Nordham hole tunneling effect to erase memory cells; however, the BE-SONOS structure of FIG. resulting in poor charge retention, or damage caused by hot hole erase. In addition, the BE-SONOS structure of FIG. 18C can be used in NOR and NAND applications.

19A and 19B show band diagrams of the ONO structure 294 in the BE-SONOS structure in FIG. 18C. FIG. 19A shows the band diagram at the time of data saving, and FIG. 19B is the band diagram at the time of erasing. As shown in FIG. 19A , during data storage, the energy of the holes is not enough to overcome the potential barriers of the layers including the ONO structure 294 . Since the hole tunneling effect is blocked by the structure 294, the tunneling leakage current hardly occurs when a low field is applied. However, when trapping structure 294 has a high field across it, as shown in FIG. 19B , the shift in energy bands allows holes to tunnel through structure 294 . This phenomenon is due to the fact that the potential barrier represented by layers 286 and 288 is almost eliminated by the holes due to the band shift in the presence of high fields.

18D-18H illustrate other example structures that may be used in the trapping layer of device 100 . For example, FIG. 18D shows a SONS structure, which may be included in a trapping structure of device 100 . The structure shown in FIG. 18D includes a thin oxide layer 302 formed over a polysilicon layer 204 . A nitride layer 304 is then formed over the thin oxide layer 302 . A gate conductive layer 218 may then be formed over the nitride layer 304 . The thin oxide layer 302 acts as a tunneling dielectric layer, and charge can be stored in the nitride layer 304 .

FIG. 18E shows an upper BE-SONOS structure that can be used as a trapping structure in device 100 . Thus, the structure shown in FIG. 18E includes an oxide layer 306 formed over the polysilicon layer 214 . A nitride layer 308 is then formed over the oxide layer 306 , and an ONO structure 315 including the oxide layer 310 , the nitride layer 312 , and the oxide layer 314 is then formed over the nitride layer 308 . In the embodiment shown in FIG. 18E , the oxide layer 306 acts as a tunneling dielectric layer, and charges can be trapped in the nitride layer 308 .

FIG. 18F shows a bottom SONOSOS structure, which can be applied in the trapping layer of device 100 . The structure shown in FIG. 18F includes an oxide layer 316 formed over the polysilicon layer 204 , and a nitride layer 318 formed over the oxide layer 316 . A thin oxide layer 320 is then formed on the nitride layer 318 , followed by a thin polysilicon layer 322 . Another thin oxide layer 324 is then formed over the polysilicon layer 322 . Thus, the layers 320 , 322 , 324 form an OSO structure 321 adjacent to the gate conductor 218 . In the embodiment shown in FIG. 18F , the oxide layer 316 can function as a tunneling dielectric layer, and charges can be stored in the nitride layer 318 .

Figure 18G shows the bottom SOSONOS structure. As can be seen in the figure, a thin OSO structure 325 is formed on the polysilicon layer 204 . OSO structure 325 includes thin oxide layer 326 , thin polysilicon layer 328 , and thin oxide layer 330 . A nitride layer 332 is then formed over the OSO structure 325 , and an oxide layer 334 may then be formed over the nitride layer 332 . In the embodiment of FIG. 18G , the OSO structure 325 can be used as a tunnel dielectric layer, and charges can be stored in the nitride layer 332 .

FIG. 18H shows an example SONONS structure that can be used in the trapping structure of device 100 . As can be seen in the figure, an oxide layer 336 is formed on the polysilicon layer 204 , and a nitride layer 338 is formed on the oxide layer 336 . ON structure 341 is then formed over nitride layer 338 . ON structure 341 includes thin oxide layer 340 formed over nitride layer 338 , and nitride layer 342 formed over thin oxide layer 340 . In the embodiment shown in FIG. 18H , the oxide layer 336 acts as a tunneling dielectric layer, and charges are trapped in the nitride layer 338 .

In other embodiments, the trapping structure may include silicon nitride or silicon oxynitride, or high-k materials such as hafnium oxide, aluminum oxide, aluminum nitride, and the like. In general, any dielectric construction or dielectric material can be used so long as it can meet the requirements of a particular application.

Figure 20 illustrates an example stacked non-volatile memory device constructed in accordance with another embodiment of the present invention. 21-31 illustrate the progression of process steps used to fabricate the memory device of FIG. 20 in accordance with an embodiment of the present invention. The embodiment described in Figures 20-31 provides a simpler design in which the word line is not shared by multiple memory cells. As shown in FIG. 20, the processes shown in FIGS. 21-31 result in a stacked memory structure that includes an insulating or dielectric layer 2402 with stacked wordline and bitline layers above the insulating layer 2402, surrounded by intervening layers. (or inter-unit dielectric layer) 2404 separated. The word line and bit line layer includes a bit line 2410 and a word line layer 2406 separated by a trap structure 2408 . As described below, a bitline layer may be deposited first, followed by patterning and etching to form bitlines 2410 . A trapping structure layer may then be deposited, and then a word line layer may be deposited over the trapping structure layer. The wordline and trapping structure layers may then be patterned and etched to form wordlines over the bitlines 2410 . Trapping structure 2408, located above bit line 2410 and below word line 2406, may then function as a trapping layer to store charge in the memory cell.

21-31 illustrate example processes to fabricate the device of FIG. 20 . As shown in FIG. 21 , polysilicon layer 2504 may be deposited over insulating layer 2502 . The insulating layer 2502 may include an oxide material, such as a silicon dioxide material. The polysilicon layer 2504 may have a thickness between about 200-1000 Angstroms. For example, the thickness of polysilicon layer 2504 may preferably be approximately 400 Angstroms in certain embodiments.

Referring to FIG. 22 , the polysilicon layer 2504 can then be patterned and etched using known lithography techniques to generate bit line regions 2506 . For example, insulating layer 2502 may serve as an etch stop for an etching step to create region 2506 . The overall thickness of the structure shown in FIG. 22 may be between about 200 and 1000 angstroms, and is preferably about 400 angstroms.

23A-23C illustrate an alternative process to etch the polysilicon layer 2504 to create bit line regions 2506 . Referring to FIG. 23A , a capping layer 2508 may be formed on the polysilicon layer 2504 . Capping layer 2508 may include, for example, a silicon nitride layer. The polysilicon layer 2504 and capping layer 2508 can then be patterned and etched using known lithographic techniques, as shown in FIG. 23B. Likewise, the insulating layer 2502 may serve as an etch stop layer for the etch process.

Referring to FIG. 23C, after the layers 2504, 2508 are etched to form the regions 2506, 2510 and the capping layer 2508, the region 2510 can be removed using known techniques.

Referring to FIG. 24 , a trapping structure layer 2508 may be formed on the insulating layer 2502 and the bit line region 2506 . As noted above, the trapping structure layer 2508 may include any of a number of trapping structures, such as SONOS, BE-SONOS, BE-SONOS on, SONONS, SONOSLS, SLSLNLS, and the like. In other embodiments, the trapping structure layer 2508 may include silicon nitride material, silicon oxynitride material, or high dielectric material, such as hafnium oxide, aluminum oxide, aluminum nitride, and the like.

Referring to FIG. 25 , a word line layer 2510 may then be formed on the trapping structure layer 2508 . For example, word line layer 2510 may include polysilicon material deposited over trapping structure layer 2508 . Layers 2510 and 2508 may then be patterned and etched using known lithographic techniques. This will form word line 2510 over bit line 2506 as shown in FIG. 27 .

As shown in FIG. 26 , the etch process can be structured such that the etch occurs in the region between the word lines 2510 and penetrates the trapping structure layer 2508 . This process results in a region 2506 flanked by regions 2512 with trapping structure layer 2508 .

Figure 27 shows a top view of the layers generated so far. Fig. 25 shows a cross-sectional view of the layers in Fig. 27 taken along line AA'. Fig. 26 shows a sectional view of each layer in Fig. 27 taken along line BB'.

Referring to FIG. 30 , source and drain regions 2514 may be deposited in the bitline 2506 , not in the region underlying the wordline 2510 . For example, if the word line 2506 is formed of P-type polysilicon material, the N-type source/drain region 2514 can be implanted and heat injected into the portion of the bit line 2506 not covered by the word line 2510 . Alternatively, if the word line 2506 is formed of N-type polysilicon material, P-type source/drain regions can be implanted and heat injected into the bit line 2506 .

Fig. 28 shows a cross-sectional view of the layers in Fig. 30 taken along line AA'. Fig. 29 shows a sectional view of each layer in Fig. 30 taken along line BB'. Thus, bit line 2506 can be seen to include channel region 2516 beneath word line 2510 . Source and drain regions 2514 are formed on both sides of the word line 2510 . It can be understood that the formation process of the source/drain region 2514 is a self-alignment process.

Referring to FIG. 31 , an intermediate layer (or inter-unit dielectric layer) 2518 is then formed on the word line layer 2510 . Another bitline and wordline layer can then be formed on the intermediate layer (or inter-unit dielectric layer) 2518 using the same process as described above. In this way, any number of word line layers and bit line layers can be formed on the insulating layer 2502 and separated by the intermediate layer (or inter-unit dielectric layer) 2518 .

Referring to FIG. 30, memory cells 2520-2526 may then be formed in the structure shown. Storage units 2520, 2522 are shown in FIG. 31 . The source and drain regions of the memory cells are formed by the source/drain regions 2514 on either side of the associated word line 2510 . A channel region is formed from a region 2516 of the bitline 2506 underlying the wordline 2510 .

It will be appreciated that the cells shown in Figures 30 and 31 are tri-gate devices. Tri-gate devices may exhibit excessive edge effects, but can also increase cell current due to larger device widths.

While this invention has been described with reference to preferred embodiments, it should be understood that the scope of the invention is not limited to the detailed description thereof. Alternatives and modifications have been suggested in the preceding description, and other alternatives and modifications will occur to those skilled in the art. In particular, according to the structure and method of the present invention, all combinations of components that are substantially the same as those of the present invention to achieve substantially the same results as the present invention do not depart from the scope of the present invention. Accordingly, all such alternatives and modifications are intended to come within the scope of the present invention as defined by the appended claims and their equivalents. Any patent applications and publications mentioned above are incorporated by reference in this case.

Claims (48)

1. one kind in order to making the method for nonvolatile semiconductor memory member, and this memory device comprises and be formed at multilayer bit line layer over each other and multilayer word line layer alternately that this method comprises:

Form these multilayer bit line layer, wherein the formation of each this bit line layer comprises:

Form semi-conductor layer on insulating barrier; And

This semiconductor layer of patterning and etching is to form multiple bit lines;

Form these multilayer word line layers on these previous multilayer bit line layer, wherein the formation of each this word line layer comprises:

Form trapping structure and conductive layer in regular turn; And

This trapping structure of patterning and etching and this conductive layer are to form many word lines.

2. the method for claim 1, wherein the patterning of this semiconductor layer and etching comprise:

Form cover layer on this semiconductor layer;

This cover layer of etching and this semiconductor layer are to form the bit line zone, and this bit line zone comprises the remainder of this cover layer and this semiconductor layer;

Form dielectric layer on overetched this cover layer and this semiconductor layer;

The some of this dielectric layer of etching is to form areas of dielectric between each bit line and on this tectal remainder; And

Remove this tectal remainder, and then remove this dielectric layer part that is positioned on this cover layer.

3. method as claimed in claim 2, wherein this cover layer comprises the mononitride layer.

4. method as claimed in claim 2, wherein this dielectric layer comprises silicon dioxide.

5. method as claimed in claim 4, wherein this silicon dioxide utilizes the high density plasma chemical vapor deposition method and deposits.

6. the method for claim 1, wherein the formation of this trapping structure comprises formation silicon-oxide-nitride--oxide-silicon structure.

7. the method for claim 1, wherein the formation of this trapping structure comprises the read-only storage organization of nitride that forms oxide-nitride thing-oxide.

8. the method for claim 1, wherein the formation of this trapping structure comprises the silicon-oxide-nitride--oxide-silicon structure that forms band gap processing.

9. the method for claim 1, wherein the formation of this trapping structure comprises formation silicon-oxide-nitride--silicon structure.

10. the method for claim 1, wherein the formation of this trapping structure comprises and forms upper strata band gap machine silicon-oxide-nitride thing-oxide-silicon structure.

11. the method for claim 1, wherein the formation of this trapping structure comprises formation upper strata silicon-oxide-nitride--oxide-silicon-oxide-silicon structure.

12. the method for claim 1, wherein the formation of this trapping structure comprises formation bottom silicon-oxide-silicon-oxide-nitride--oxide-silicon structure.

13. the method for claim 1, wherein the formation of this trapping structure comprises formation silicon-oxide-nitride--oxide-nitride thing-silicon structure.

14. the method for claim 1, wherein the formation of this trapping structure comprises the formation silicon nitride layer.

15. the method for claim 1, wherein the formation of this trapping structure comprises the formation silicon oxynitride layer.

16. the method for claim 1, wherein the formation of this trapping layer comprises the high dielectric radio material of deposition.

17. method as claimed in claim 16, wherein this high dielectric radio material is a hafnium oxide), aluminium nitride or aluminium oxide.

18. the method for claim 1, also comprise form regions and source in these multiple bit lines not by the zone that this many word lines covered in.

19. method as claimed in claim 18, wherein this semiconductor layer comprises the P type semiconductor material, and wherein the formation of this regions and source is included in formation N+ zone in the P type semiconductor material.

20. method as claimed in claim 19, wherein this N+ zone utilizes arsenic or phosphorus and forms.

21. the method for claim 1, wherein this conductive layer comprises polycrystalline silicon material.

22. the method for claim 1, wherein this conductive layer comprises polysilicon/silicide/polycrystalline silicon material.

23. the method for claim 1, wherein this conductive layer comprises metal.

24. method as claimed in claim 23, wherein this metal is aluminium, copper or tungsten.

25. the method for claim 1, wherein the patterning of this trapping structure and this conductive layer and etching comprise:

Form cover layer on this trapping structure and this conductive layer;

This cover layer of etching and this trapping structure and this conductive layer, to form word line regions, this word line regions comprises the remainder of this cover layer, this trapping structure and conductive layer;

Form dielectric layer in this on etched this cover layer, this trapping structure and this conductive layer:

The some of this dielectric layer of etching is to form areas of dielectric between each word line and on this tectal remainder; And

Remove this tectal remainder, to remove this dielectric layer part that is positioned on this cover layer.

26. method as claimed in claim 25, wherein this cover layer comprises nitride layer.

27. method as claimed in claim 25, wherein this cover layer comprises silicon dioxide.

28. method as claimed in claim 27, wherein this silicon dioxide utilizes high density plasma chemical vapor deposition and deposits.

Be formed at multilayer bit line layer over each other and multilayer word line layer in regular turn 29. the method in order to the manufacturing nonvolatile semiconductor memory member, this device comprise, this method comprises:

Form the multilayer bit line layer, wherein the formation of each bit line layer comprises:

Form first semiconductor layer on insulator;

Form cover layer on this semiconductor layer;

This cover layer of etching and this semiconductor layer are to form the bit line zone, and this bit line zone comprises the remainder of this cover layer and this semiconductor layer;

Form dielectric layer in this through overetched cover layer on semiconductor layer;

The some of this dielectric layer of etching to be forming areas of dielectric between the bit line zone, and forms areas of dielectric on this tectal remainder; And

Remove this tectal remainder, and then remove this dielectric layer part that is positioned on this cover layer; And

Form this multilayer word line layer on this previous multilayer bit line layer, wherein the formation of each word line layer comprises:

Form trapping structure and conductive layer in regular turn, this trapping structure comprises sandwich construction, and

This trapping structure of patterning and etching and this conductive layer are to form many word lines.

30. method as claimed in claim 29, wherein this cover layer comprises nitride layer.

31. method as claimed in claim 29, wherein this dielectric layer comprises silicon dioxide.

32. method as claimed in claim 31, wherein this silicon dioxide utilizes the high density plasma chemical vapor deposition method and deposits.

33. method as claimed in claim 29, wherein the formation of this trapping structure comprises formation silicon-oxide-nitride--oxide-silicon structure.

34. method as claimed in claim 29, wherein the formation of this trapping structure comprises the read-only storage organization of nitride that forms oxide-nitride thing-oxide.

35. method as claimed in claim 29, wherein the formation of this trapping structure comprises the silicon-oxide-nitride--oxide-silicon structure that forms band gap processing.

36. method as claimed in claim 29, wherein the formation of this trapping structure comprises formation silicon-oxide-nitride--silicon structure.

37. method as claimed in claim 29, wherein the formation of this trapping structure comprises formation upper strata band gap machine silicon-oxide-nitride thing-oxide-silicon structure.

38. method as claimed in claim 29, wherein the formation of this trapping structure comprises formation upper strata silicon-oxide-nitride--oxide-silicon-oxide-silicon structure.

39. method as claimed in claim 29, wherein the formation of this trapping structure comprises formation bottom silicon-oxide-silicon-oxide-nitride--oxide-silicon structure.

40. method as claimed in claim 29, wherein the formation of this trapping structure comprises formation silicon-oxide-nitride--oxide-nitride thing-silicon structure.

41. method as claimed in claim 29, wherein the formation of this trapping structure comprises the formation silicon nitride layer.

42. method as claimed in claim 29, wherein the formation of this trapping structure comprises the formation silicon oxynitride layer.

43. method as claimed in claim 29 also comprises forming regions and source in these multiple bit lines and in not by the zone that this many word lines covered.

44. method as claimed in claim 43, wherein this semiconductor layer comprises the P type semiconductor material, and wherein the formation of this regions and source is included in formation N+ zone in the P type semiconductor material.

45. method as claimed in claim 44, wherein this N+ zone utilizes arsenic or phosphorus and forms.

46. method as claimed in claim 29, wherein this conductive layer comprises polycrystalline silicon material.

47. method as claimed in claim 29, wherein this conductive layer comprises polysilicon/silicide/polycrystalline silicon material.

48. method as claimed in claim 29, wherein this conductive layer comprises metal.

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