CN1971904A - The stacked structure of semiconductor components embedded in the carrier board - Google Patents

Abstract

The invention discloses a splicing structure of a semiconductor element embedded bearing plate, which comprises: two bearing plates, each bearing plate is provided with at least one opening; at least two semiconductor elements fixed in the opening of the bearing plate; at least one dielectric layer formed on the active surface of the semiconductor element and the surface of the bearing plate and at least one conductive structure formed in the opening of the dielectric layer, at least one circuit layer formed on the surface of the dielectric layer, the circuit layer electrically connected to the electrode pad of the semiconductor element by the conductive structure; the splicing structure of the semiconductor element embedded bearing plate can be a three-dimensional combined modular structure so as to greatly improve the storage capacity, integrate the semiconductor element in the bearing plate so as to effectively reduce the size of a module, and flexibly change and combine the semiconductor element and the bearing plate according to the use requirement so as to form the required storage capacity.

Description

The stacked structure of semiconductor components embedded in the carrier board

technical field

The invention relates to a lamination structure in which semiconductor elements are embedded in a carrying plate, in particular to a structure in which semiconductor elements are first embedded in a carrying plate, and then the carrying plate is laminated.

Background technique

With the vigorous development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development to meet the packaging needs of high integration and miniaturization of semiconductor packages, and in order to improve the single semiconductor package The performance and capacity of the components, in order to meet the trend of miniaturization, large capacity and high speed of electronic products, the existing technology is to present the semiconductor package in the form of multi-chip modular (Multi Chip Module; MCM), this package is also It can reduce the volume of the overall package and improve the electrical function, which has become the mainstream of a package at present. It is to connect at least two semiconductor chips (semiconductor chips) on the chip carrier of a single package, and each semiconductor chip and the carrier are connected in a stack (stack) manner. This stacked chip package Structures have been found in US Patent No. 6,798,049.

As shown in Fig. 1, it is a cross-sectional view of the CDBGA package disclosed in U.S. Patent No. 6,798,049. It forms an opening 101 on a circuit board 10 with a circuit layer 11, and forms a circuit board 10 with an electrical The circuit layer 11 of the connection pad 11a and the bonding wire pad 11b (bounding pad), the two stacked semiconductor chips 121, 122 are combined in the opening 101, and the semiconductor chips 121, 122 are connected by a soldering layer 13 (bounding pad). layer) is electrically connected, and the semiconductor chip 122 is electrically connected to the wire pad 11b of the circuit layer 11 with a conductive device 14 such as a gold wire, and then the opening 101 of the circuit board 10 is filled with the encapsulant 15, and the semiconductor chip is covered. Chips 121, 122 and conductive device 14, and an insulating protective layer 16 is formed on the circuit layer 11 of the circuit board, and a plurality of openings 16a are formed on the insulating protective layer 16 to expose the electrical connection pad 11a, and A conductive element 17 such as a solder ball is formed in the opening 16a of the insulating protection layer 16 to complete the packaging process.

However, for this type of package, the stacked semiconductor chips 121 and 122 are electrically connected to the circuit layer 11 by wire bonding. The structure of wire bonding increases the height of the package due to the height of the wire loop, so that Can't realize the light and small purpose. Moreover, the semiconductor chips 121 and 122 must be electrically connected with the solder layer 13 connected at the chip level, that is, the semiconductor chips 121 and 122 must first be electrically connected in the chip factory for a stacking process, and then sent to the packaging factory for further processing. Packaging makes the process more complicated and increases the manufacturing cost.

And by means of stacking to increase electrical functions and modular performance, if the performance is to be further improved, stacking must be performed again. In this way, in addition to increasing the thickness of the package, it also increases the complexity of the circuit layer 11, and It is also necessary to increase the number of wire bonding pads 11b of the circuit layer 11. To increase the circuit density and the number of wire bonding pads 11b within a limited or fixed area of use, the circuit board used to carry the semiconductor chips 121 and 122 must reach a thin line. , in order to meet the requirements of thin and small packages. However, the effect of reducing the area of the circuit board by using thin lines is limited, and by directly stacking the semiconductor chips 121 and 122 to increase electrical functions and modular performance, the number of stacked chips is limited and cannot be continuously expanded. Moreover, the purpose of thin and small package cannot be achieved.

In order to increase the density of multi-chip modularization on multi-layer circuit boards, reduce the area of semiconductor chips on multi-layer circuit boards, reduce the packaging volume, and increase storage capacity, it has become an important issue in the circuit board industry. topic.

Contents of the invention

In order to overcome the shortcomings of the prior art, the main purpose of the present invention is to provide a stacked structure in which semiconductor components are embedded in a carrier board, which can form a modular structure by embedding semiconductor devices in a carrier board.

Another object of the present invention is to provide a lamination structure in which semiconductor elements are embedded in a carrier board, which can flexibly change the number of semiconductor elements according to needs, and has better combination and transformation flexibility.

Another object of the present invention is to provide a stacked structure in which semiconductor elements are embedded in a carrier board, which can reduce the modular volume.

In order to achieve the above and other purposes, the stacking structure of the semiconductor element embedded in the carrier board of the present invention includes: two carrier boards, each of which is formed with at least one opening, and the carrier boards are laminated by a connecting layer. Integral; at least two semiconductor elements are fixed in the opening of the carrier plate, wherein the semiconductor element includes an active surface with a plurality of electrode pads and a non-active surface opposite to the active surface; at least one dielectric layer forms On the active surface of the semiconductor element and the surface of the carrier plate, at least one opening is formed on the dielectric layer corresponding to the electrode pad; and at least one conductive structure is formed in the opening of the dielectric layer, At least one circuit layer is formed on the surface of the dielectric layer, and the circuit layer is electrically connected to the electrode pad of the semiconductor element through the conductive structure. These carrier boards are stacked with a connecting layer to form a modular structure, and different semiconductor elements and quantities can be changed and combined according to needs, so as to realize different changing use requirements, and have better changing and combining flexibility.

Since the semiconductor element is placed in the opening of the carrier board, and then the carrier board is laminated, a dielectric layer, a circuit layer and a conductive structure are formed on the active surface of the semiconductor element and the surface of the carrier board, and the conductive structure is electrically conductive. The electrode pads connected to the semiconductor element form a stacked modular structure, which can avoid the increase in thickness caused by direct stacking in the prior art, and can avoid the lack of wire bonding (wire bounding), thereby reducing the volume to achieve thin small purpose of use.

At least one plated through hole (PTH) is penetrated through the dielectric layer, the circuit layer, the connection layer and at least two carrier plates, and the semiconductor elements in the at least two carrier plates are electrically connected through the circuit layer and the plated through hole. connect.

The present invention can further form a line build-up structure on the surface of the dielectric layer and the circuit layer, and a plurality of conductive structures are formed in the line build-up structure to be electrically connected to the line layer, and the line build-up structure A connection pad is formed on the surface; there is a solder resist layer on the surface of the circuit build-up structure, and the surface of the solder resist layer has a plurality of openings to expose the connection pads of the circuit build-up structure, and a solder mask is formed in the opening of the solder resist layer The conductive element is electrically connected to the connection pad. To form a circuit board structure in which the semiconductor element is packaged in the carrier board.

Wherein the circuit build-up structure includes a dielectric layer, a circuit layer stacked on the dielectric layer and conductive blind holes formed in the dielectric layer.

Since the semiconductor element is embedded in the carrier board, and a dielectric layer, a circuit layer and an electrode pad electrically connected to the semiconductor element are formed on the active surface of the semiconductor element and the surface of the carrier board, it becomes a modular structure, and then the A layered structure is formed on the circuit, which can be flexibly combined according to the use demand to form the required storage capacity.

Description of drawings

Figure 1 is a cross-sectional view of US Patent No. 6,798,049;

2A to 2D are cross-sectional views of Embodiment 1 of the stacked structure of the semiconductor element embedded in the carrier plate of the present invention;

3A and 3B are cross-sectional views of Embodiment 2 of the stacked structure of semiconductor elements embedded in the carrier board of the present invention;

4A and 4B are cross-sectional views of Embodiment 3 of the stacked structure of the semiconductor element embedded in the carrier plate of the present invention;

5A to 5D are cross-sectional views of Embodiment 4 of the stacked structure of the semiconductor element embedded in the carrier plate of the present invention; and

FIG. 6 is a cross-sectional view of Embodiment 5 of the stacked structure of the semiconductor element embedded in the carrier board of the present invention.

Detailed ways

Example 1

Please refer to FIG. 2A to FIG. 2C , which are schematic cross-sectional views of the stacked structure of the semiconductor device embedded in the carrier board of the present invention.

Please refer to FIG. 2A, at least two bearing plates 21 have a first surface 21a and a second surface 21b, and at least one opening 21c that runs through the first and second surfaces 21a, 21b is formed on the bearing plate 21. It is an insulating board or a circuit board with lines, and at least one semiconductor element 22 is connected in these openings 21c, and it can fix the semiconductor element 22 in the opening 21c of the carrier plate 21 by means of an adhesive material (not shown). , the semiconductor element 22 is, for example, one of active elements or passive elements, wherein the active element is, for example, a memory, and the passive element is, for example, electronic elements such as resistors, capacitors or inductors, and the semiconductor element 22 has a The active surface 22a and the non-active surface 22b corresponding to the active surface have a plurality of electrode pads 22c on the active surface 22a, and the active surfaces 22a of these semiconductor elements 22 are fixed on the opening 21c of the same carrier plate 21 in the same direction middle.

2B, a dielectric layer 23 is formed on the active surface 22a of the semiconductor element 22 and the first surface 21a of the carrier plate 21, and a circuit layer 24 is formed on the surface of the dielectric layer 23, and the circuit layer 24 There is a conductive structure 24 a formed in the dielectric layer 23 , and the conductive structure 24 a is electrically connected to the electrode pad 22 c of the semiconductor device 22 .

Please refer to FIG. 2C and FIG. 2D, at least two carrier plates 21 embedded with semiconductor elements 22 are stacked with a connection layer 25, the connection layer 25 may be an organic adhesive layer, and the carrier plate 21 is based on The second surface 21b is overlapped with the second surface 21b of the other carrier plate 21 to form an integrated body, as shown in FIG. 2C; or the carrier plate 21 is overlapped with the first surface 21a of the other carrier plate 21. The first surface 21a is similarly stacked up and down (not shown); or these carrier boards 21 are laminated on another carrier board with the dielectric layer 23 and the circuit layer 24 on the first surface 21a The second surface 21b is stacked up and down in the same direction, as shown in FIG. 2D; and the dielectric layer 23, the circuit layer 24, the connecting layer 25 and the two carrier plates 21 are penetrated by at least one plated via hole 26, And the plated via hole 26 is electrically connected to the circuit layer 24, so that the semiconductor elements 22 embedded in the carrier board 21 can be electrically connected, and a modular structure can be formed.

The semiconductor element 22 is embedded in the opening 21c of the carrier plate 21. Multiple semiconductor elements 22 can be embedded in the carrier plate 21, thereby increasing the number of semiconductor elements 22 connected to the carrier plate 21 and increasing its storage capacity. Form a dielectric layer 23 and a circuit layer 24 with a conductive structure 24a on the active surface 22a of the semiconductor element 22 and the first surface 21a of the carrier plate 21, and the conductive structure 24a is electrically connected to the electrode of the semiconductor element 22 Pad 22c, and then at least two carrier boards 21 are stacked together with a connection layer 25, and the circuit layer 24 is connected with a plated via hole 26, so that a larger number of semiconductor elements 22 can be electrically connected, and the overall size can be reduced. volume, and can avoid the lack of existing direct chip stacking and wire bonding.

And the semiconductor element 22 is embedded in the carrier board 21, and then the carrier board 21 is laminated, and different combinations and changes can be made according to the needs, so as to meet different use needs, so it has better conversion flexibility.

Example 2

Please refer to Fig. 3A and Fig. 3B, which is a schematic cross-sectional view of Embodiment 2 of the stacked structure of the semiconductor element embedded in the carrier plate of the present invention. The difference from Embodiment 1 is that the active surface of the semiconductor element is in the same carrier plate It is embedded in the opening of the bearing plate in different directions.

Referring to FIG. 3A , semiconductor elements 32 are respectively placed in a plurality of openings 31c of the carrier plate 31, which can fix the semiconductor elements 32 in the openings 31c of the carrier plate 31 by means of an adhesive material (not shown). And the active surface 32a of the semiconductor element 32 is selectively formed on the first surface 31a and the second surface 31b of the carrier plate 31, so that the first and second surfaces 31a, 31b of the carrier plate 31 have the semiconductor element 32 respectively. Active surface 32a.

Referring to FIG. 3B, a dielectric layer 33 and a circuit layer 34 having a conductive structure 34a are formed on the first and second surfaces 31a, 31b of the carrier board 31, respectively, and the conductive structure 34a is electrically connected to the semiconductor element. 32 electrode pads 32b, so that the upper and lower sides of the carrier board 31 have circuit layers 34 respectively, and the circuits can be dispersed on both sides of the carrier board 31.

The carrier board 31 with circuits on both sides can be stacked as required, and then the circuit layer 34 of each layer is connected with the plated via hole 36, so as to increase the number of electrical connections of the semiconductor element 32, improve the electrical function or increase the modularization performance. , and can reduce the overall volume to achieve the purpose of thinness, and can have greater flexibility in transformation and combination to meet different use needs.

Example 3

Please refer to FIG. 4A and FIG. 4B , which are schematic cross-sectional views of Embodiment 3 of the stacked structure of the semiconductor element embedded in the carrier plate of the present invention. The difference from the above embodiment is that the opening 41c of the carrier plate 41 is non-through, and The direction of the opening 41c is selectively formed on the first surface 41a or the second surface 41b of the carrier plate 41, and the semiconductor element 42 can be placed in the opening 41c, so that the active surfaces 42a of the semiconductor element 42 can all face the same direction. Or in different directions, a dielectric layer 43 and a circuit layer 44 with a conductive structure 44a can be formed on the active surface 42a of the semiconductor element 42 and the surface of the carrier plate 41, and the conductive structure 44a is electrically connected to the semiconductor element 42. The electrode pad 42b also achieves the above-mentioned purpose of reducing the overall volume, and has greater flexibility in changing combinations to meet different usage needs.

Example 4

Please refer to Figures 5A to 5C, which are cross-sectional schematic views of Embodiment 4 of the stacked structure of the semiconductor element embedded in the carrier plate of the present invention. The properties are formed on the first surface and the second surface of the bearing plate.

Please refer to FIG. 5A, at least one non-penetrating opening 51c is formed on each of at least two carrying plates 51, and the opening direction of the opening 51c is selectively formed on the first surface 51a and the second surface 51b of the carrying plate 51, A semiconductor element 52 is connected in the opening 51c, and the active surface 52a of the semiconductor element 52 with the electrode pad 52b is exposed outside the opening 51c of the carrier plate 51 and fixed in it, so that the upper and lower sides of the carrier plate 51 Both surfaces have the active surface 52a of the semiconductor element 52 .

Please refer to FIG. 5B, a dielectric layer 53 is formed on the first and second surfaces 51a, 51b of the carrier board 51 and the active surface 52a of the semiconductor element 52, and a circuit layer 54 is formed on the surface of the dielectric layer 53. , and the circuit layer 54 has a conductive structure 54a formed in the dielectric layer 53, the conductive structure 54a is electrically connected to the electrode pad 52b of the semiconductor element 52, so that the first and second surfaces 51a, 51a, and 51b has a wiring layer 54 .

Please refer to FIG. 5C and FIG. 5D, at least two carrier plates 51 embedded with semiconductor elements 52 are stacked with a connection layer 55, so that the carrier plate 51 is stacked on the other side with the first surface 51a. One side of the second surface 51b of the carrying plate 51 becomes overlapping up and down in the same direction (as shown in FIG. 5C ); On the one hand, it is stacked up and down (as shown in FIG. 5D ); and the dielectric layer 53, the circuit layer 54, the connection layer 55 and at least two carrier plates 51 are penetrated by at least one plated via hole 56, which can The electroplated via holes 56 are used to electrically connect each circuit layer 54 , so that the semiconductor elements 52 embedded in the carrier board 51 are electrically connected to form a modular structure.

Example 5

Please refer to FIG. 6 , which is a schematic cross-sectional view of Embodiment 5 of a stacked structure in which a semiconductor element is embedded in a carrier plate of the present invention. An opening 61a is provided on the carrier plate 61, and a semiconductor element 62 is embedded in the opening 61a. A dielectric layer 63 is formed on the active surface 62a of the element 62 and the surface of the carrier plate 61, and a circuit layer 64 with a conductive structure 64a is formed on the surface of the dielectric layer 63, and the conductive structure 64a is electrically connected to the semiconductor element 62 The electrode pads 62b are stacked on the carrier board 61 with at least one connection layer 65 , and the circuit layer 64 is electrically connected with at least one plated via hole 66 . The structures shown in the figure are provided for illustration, but are not limited thereto, and become the above-mentioned various overlapping structures.

Then at least one circuit build-up structure 67 is formed on the surface of the circuit layer 64 and the dielectric layer 63. The circuit build-up structure 67 includes a dielectric layer 67a, a circuit layer 67b stacked on the dielectric layer 67a, and a circuit layer 67b formed on the dielectric layer 67a. The conductive blind hole 67c in the dielectric layer 67a, and the conductive blind hole 67c is electrically connected to the circuit layer 64; there is a solder resist layer 68 on the surface of the circuit layer build-up structure 67, and the solder resist layer 68 There is at least one opening 68a on the surface at the edge of the stacking structure to expose the circuit layer 67b of the circuit build-up structure 67 as an electrical connection pad 67d for conducting with external conductive elements (not shown).

The semiconductor element 62 is embedded in the opening 61a of the carrier plate 61, and a dielectric layer 63 and a circuit layer 64 are formed on the active surface 62a of the semiconductor element 62 and the surface of the carrier plate 61, and then the via hole 66 is laminated and plated. Connect to form a modular structure, and then form a circuit build-up structure 67 on it, the semiconductor element 62 can be packaged in the carrier board 61, eliminating the necessary wire bonding and sealing processes in the prior art, so the manufacturing cost can be reduced , and the semiconductor element 62 is directly embedded in the carrier board 61, the overall volume can be reduced to achieve the purpose of thinness.

In the stacking structure of the semiconductor element embedded in the carrier plate of the present invention, the semiconductor element is placed in the opening of the carrier plate, and then the carrier plate is stacked, and then a dielectric layer is formed on the active surface of the semiconductor element and the surface of the carrier plate , circuit layer and conductive structure, and the conductive structure is electrically connected to the electrode pad of the semiconductor element to form a stacked modular structure, which can avoid the increase in thickness caused by direct stacking in the prior art, and can avoid wire bonding and Encapsulation leads to a loss that cannot be reduced in size. At least one plated through hole (PTH) is penetrated through the dielectric layer, the circuit layer, the connection layer and at least two carrier plates, and the semiconductor elements in the at least two carrier plates are electrically connected through the circuit layer and the plated through hole. connection to increase its storage capacity. And it can be flexibly combined according to the usage demand to form the required storage capacity.

Claims (13)

1. A stacking structure in which a semiconductor element is embedded in a carrier plate, is characterized in that, the stacking structure in which the semiconductor element is embedded in a carrier plate comprises: Two bearing plates, each of which is formed with at least one opening, and the bearing plates are laminated into one body by a connecting layer; At least two semiconductor elements are fixed in the opening of the carrier plate, wherein the semiconductor element includes an active surface with a plurality of electrode pads and a non-active surface opposite to the active surface; At least one dielectric layer is formed on the active surface of the semiconductor element and the surface of the carrier plate, wherein at least one opening is formed on the dielectric layer corresponding to the electrode pad; and At least one conductive structure is formed in the opening of the dielectric layer. At least one circuit layer is formed on the surface of the dielectric layer. The circuit layer is electrically connected to the electrode pad of the semiconductor element through the conductive structure. 2 . The stacked structure of semiconductor components embedded in a carrier board as claimed in claim 1 , wherein the carrier board is an insulating board or a circuit board with circuits. 3 . 3 . The stacked structure of semiconductor devices embedded in a carrier plate as claimed in claim 1 , wherein the opening of the carrier plate is a non-through or through opening. 4 . 4 . The stacked structure of semiconductor devices embedded in a carrier board as claimed in claim 3 , wherein the carrier board has a first surface and a second surface. 5 . The stacked structure of semiconductor devices embedded in a carrier board as claimed in claim 4 , wherein the opening of the carrier board is one of the groups formed on the first surface and the second surface of the carrier board. 5 . 6. The stacking structure of semiconductor elements embedded in carrier boards as claimed in claim 5, characterized in that, these carrier boards are stacked on the second surface of another carrier board with one side of the first surface, so that they are stacked in the same direction up and down. catch. 7. The stacked structure for embedding semiconductor elements in carrier boards as claimed in claim 5, characterized in that, for these carrier boards, one side of the second surface is laminated to the second surface of another carrier board, which is opposite up and down. direction overlap. 8. The stacking structure for embedding semiconductor elements in carrier boards as claimed in claim 5, characterized in that, these carrier boards are one side of the first surface to be laminated to the first surface of another carrier board, which is opposite up and down. direction overlap. 9. The lamination structure for embedding semiconductor devices in a carrier board as claimed in claim 1, wherein the connection layer is formed of an organic adhesive material. 10. The stacked structure of semiconductor elements embedded in a carrier board according to claim 1, characterized in that, the stacked structure of semiconductor elements embedded in a carrier board further comprises at least one plated via hole penetrating through the dielectric layer, circuit layer, connection layer and two carrier boards to electrically connect the semiconductor element. 11. The superimposed structure of semiconductor elements embedded in a carrier board according to claim 10, characterized in that, the superimposed structure of semiconductor elements embedded in a carrier board further comprises forming at least one layer on the surface of the dielectric layer and the circuit layer. A circuit build-up structure, and a plurality of conductive blind holes are formed in the circuit build-up structure to electrically connect to the circuit layer, and a connection pad is formed on the surface of the circuit build-up structure. 12. The stacked structure of semiconductor elements embedded in a carrier board according to claim 11, wherein the stacked structure of semiconductor elements embedded in a carrier board further comprises a solder resist layer on the surface of the circuit build-up structure, And the surface of the solder resist layer has at least one opening at the edge of the lamination structure to expose the circuit layer on the surface of the circuit build-up structure as an electrical connection pad for conducting with other conductive elements. 13. The stacked structure of semiconductor elements embedded in a carrier board according to claim 12, wherein the circuit build-up structure comprises a dielectric layer, a circuit layer stacked on the dielectric layer, and a circuit layer formed on the dielectric layer. Conductive blind vias in electrical layers.