CN1971530A - Digital temperature sensing system - Google Patents

Abstract

The invention is a digital temperature sensing system, comprising: a clock generating device for generating a first clock signal with a fixed frequency; an oscillation circuit including P inverter gates such that the oscillation circuit can output a second clock signal, wherein P is an odd number; a command signal generating unit connected to the clock pulse generating device for generating a reference command signal according to the first clock pulse signal, so that the reference command signal can periodically generate a counting period; and the command signal processing unit is connected to the command signal generating unit and the oscillating circuit and is used for counting the number of clock pulses of the second clock pulse signal in the counting period and determining a working temperature range according to the number of clock pulses. The invention can solve the problems that the common analog chip set temperature sensing system occupies larger area of the chip set, the cost is increased due to more complex circuit design, and the delay of the internal gate of the chip set can not be actually measured.

Description

Digital Temperature Sensing System

technical field

The present invention is a digital temperature sensing system and method, especially a digital temperature sensing system applied to detect the internal temperature of chipsets.

Background technique

In a computer system, the temperature of the environment where the chipset is located is a major factor for the stability of the chipset during operation. Once the temperature of the environment where the chipset is located exceeds a certain critical value, it will not only cause the chipset to process data In severe cases, it may even cause damage to the chipset hardware. Therefore, generally in a computer system, there will be a temperature sensing system for measuring the temperature of the chipset to monitor the temperature of the chipset at any time.

Please refer to FIG. 1 , which is a schematic functional block diagram of a temperature sensing system of a commonly used chipset. As shown in the figure, the temperature sensing system includes a conversion circuit 10 and a thermal diode (Thermal Diode) 12, wherein the conversion circuit 10 further includes an analog-to-digital conversion unit 102 connected to both ends of the thermal diode 12 , and a signal temperature mapping unit 104 connected to the analog-to-digital conversion unit 102, and the thermal diode 12 can be designed inside the chipset (not shown in the figure) or close to the surface of the chipset.

The main feature of the thermal diode 12 is that the current generated by the thermal diode 12 will change with the temperature of the thermal diode 12 . That is to say, the current generated by the thermal diode 12 has a specific relationship with the surrounding temperature of the thermal diode 12 . As shown in Figure 1, when the thermal diode 12 placed inside the chipset or close to the surface of the chipset causes the current generated by the thermal diode 12 to change due to changes in the temperature of the chipset, at this time, the analog-to-digital conversion circuit 10 The conversion unit 102 can convert the analog current into a digital signal and input it to the signal temperature mapping unit 104, and convert a corresponding temperature value output through the signal temperature mapping unit 104, so that the chipset can be measured temperature.

However, the commonly used temperature sensing system is implemented by using both analog circuits and digital circuits. Compared with digital circuits, analog circuits often occupy a larger area and more complicated circuit design. Therefore, the built-in chip set temperature Sensing systems can take up many chipset real estate.

Therefore, in order to solve the relatively large area occupied by the chip set and the more complicated circuit design of the commonly used analog temperature sensing system, the present invention proposes a digital temperature sensing system and method, and further achieves the gate delay ( Gate Delay) is the purpose of the development of the present invention.

Contents of the invention

The purpose of the present invention is to provide a digital temperature sensing system, so as to solve the problem that the commonly used analog chipset temperature sensing system occupies a large volume of the chipset, the cost of the more complicated circuit design is increased, and it is impossible to actually measure the temperature in the chipset. The problem of gate delay.

The present invention proposes a digital temperature sensing system, comprising: a clock generating device, which can generate a first clock signal with a fixed frequency; an oscillation circuit including P inverter gates, so that the The oscillating circuit can output a second clock signal, wherein P is an odd number; a command signal generating unit connected to the clock generating device for generating a reference command signal according to the first clock signal , so that the reference command signal can periodically generate a counting period; and, a command signal processing unit, the command signal processing unit is connected to the command signal generating unit and the oscillation circuit, for counting the first counting period during the counting period A clock number of the two clock signals, and a working temperature range is determined according to the clock number.

The digital temperature sensing system provided by the present invention can solve the problem that the commonly used analog chipset temperature sensing system occupies a larger area of the chipset, the increase in cost caused by the more complicated circuit design, and the inability to actually measure the internal gate delay of the chipset The problem.

Description of drawings

FIG. 1 is a schematic functional block diagram of a temperature sensing system of a commonly used chipset.

FIG. 2 is a schematic diagram of an inverter gate and its actual input and output signals.

FIG. 3 is a schematic diagram of P series-connected inverter gate groups.

FIG. 4 is a schematic functional block diagram of the digital temperature sensing system of the present invention.

FIG. 5 is a circuit diagram of the command signal generating unit.

FIG. 6 is a schematic diagram of the output signal of the command signal generation unit.

FIG. 7 is a circuit diagram of the command signal processing unit.

Detailed ways

A deeper understanding of the present invention can be obtained through the following drawings and descriptions.

Please refer to FIG. 2 , which shows a schematic diagram of an inverter gate (Not Gate) 20 and its actual input and output signals. Ideally, when the input terminal of the inverter gate 20 transitions from high level to low level, the output terminal of the inverter gate 20 should immediately transition from low level to high level. However, as shown in FIG. 2 , the transition of the input terminal of the inverter gate 20 from a high level to a low level occurs at time point t1, and the transition of the output terminal of the inverter gate 20 from a low level to a high level occurs at Time point t2 occurs. That is to say, actually the time delay (Δt) between the input and output signals is called the gate delay. Due to the physical characteristics of the integrated circuit element in the inverter gate 20, when the temperature of the environment where the integrated circuit element is located increases, the gate delay also increases. Therefore, when the temperature of the chipset changes, the The gate delay will also change accordingly. In this way, when the chip set is actually running, the signal transmission will be different from the ideal situation due to temperature changes. Since there is no device for measuring the gate delay in commonly used chipsets, usually the magnitude of the gate delay is mainly based on the estimation of the circuit during design, or through program simulation after the circuit design is completed. However, since the gate delay cannot be actually measured in the chipset, it will cause inconvenience and errors in circuit design.

The present invention utilizes the characteristics of the temperature of the inverter gate 20 to propose a digital temperature sensing system of the present invention. Please refer to FIG. 3 , which is a schematic diagram of P series-connected inverter gate groups. Where P is an odd number, and the output terminal of the Pth inverter gate is fed back to the input terminal of the first inverter gate. Since P is an odd number, assuming that the input terminal of the first inverter gate is a high level, the output terminal of the Pth inverter gate will output a low level. When fed back to the input terminal of the first inverter gate, the output terminal of the Pth inverter gate will output a clock signal that repeats low level and high level continuously. As mentioned above, as the temperature increases, the gate delay of the inverter gate also increases, and as the gate delay increases, the frequency fgate of the clock signal output by the inverter gate group decreases accordingly Therefore, the digital temperature sensing system of the present invention calculates the operating temperature and Gate delay for each inverter gate.

For example, at a specific temperature, a time course of M clock pulses generated by a clock generating device that is not disturbed by temperature and whose frequency is fixed at fosc, such as a quartz oscillator, is measured to measure the P serially connected The output terminal of the inverter gate group outputs N number of clock pulses, and it can be deduced that at this specific temperature, the gate delay of each inverter gate is M×1/fosc×1/N×1/P.

Please refer to FIG. 4 , which is a functional block diagram of the digital temperature sensing system of the present invention. The digital temperature sensing system includes a clock generator 42 , P cascaded inverter gate groups 44 , a command signal generating unit 46 and a command signal processing unit 48 . Wherein, the clock generating device 42 can output a first clock signal with a first frequency fosc, and the P cascaded inverter gate groups 44 can output a second clock signal with a second frequency fgate.

Furthermore, the command signal generating unit 46 is connected to the clock generating device 42, which generates a reference command signal, a loading command signal and a clearing command according to a first clock signal generated by the clock generating device. signal; and the command signal processing unit 48 is connected to the command signal generating unit 46 and the P series inverter gate groups 44, which are used to count the P in a counting time specified by the reference command signal The number of clocks in a second clock signal output from the output terminal of the series inverter gate group 44 is used to determine the temperature sensed by the temperature sensing system or the gate delay according to the number of clocks.

Please refer to FIG. 5 , which is a circuit diagram of the command signal generation unit. The command signal generating unit circuit includes a first counter 461, the enabling terminal (EN ₁ ) of the first counter 461 is connected to a high level and the clock input terminal is connected to a first clock signal for calculating the first A first clock number generated by a clock signal; a first comparator 462, the first input terminal (A ₁ ) of the first comparator 462 is connected to the output terminal (O ₁ ) of the first counter 461, The second input terminal (B ₁ ) then provides a first value (M); a second comparator 463, the first input terminal (A ₂ ) of the second comparator 463 is connected to the output terminal of the first counter 461 (O ₁ ), the second input terminal (B ₂ ) provides a second value (M+R), and the output terminal (A ₂ =B ₂ ) is connected to the clear terminal (C ₁ ) of the first counter 461; a first Three comparators 464, the first input terminal (A ₃ ) of the third comparator 464 is connected to the output terminal (O ₁ ) of the first counter 461, and the second input terminal (B ₃ ) provides a third value (M +Y); a fourth comparator 465, the first input terminal (A ₄ ) of the fourth comparator 465 is connected to the output terminal (O ₁ ) of the first counter 461, and the second input terminal (B ₄ ) provides A fourth value (M+X), the output terminal (A ₄ =B ₄ ) can output the load command signal (LD); an inverter gate 466, the input terminal of the inverter gate 466 is connected to the first An output terminal (A ₁ =B ₁ ) of a comparator 462; a multiplexer 467, the first input terminal (Hi) of the multiplexer 467 is connected to the output terminal of the inverter gate 466, and the second input terminal (Lo) is connected to the output terminal (A ₂ =B ₂ ) of the second comparator 463; a first D-type flip-flop 468, the input end of the first D-type flip-flop 468 is connected to the multiplexer 467 Output terminal, the clock input terminal is connected to the first clock signal, the output terminal is connected to the selection terminal (S) of the multiplexer 467 and can output the reference command signal (REF); a second D-type flip-flop 469 , the input terminal of the second D-type flip-flop 469 is connected to the output terminal of the third comparator 464 (A ₃ =B ₃ ), the clock input terminal is connected to the first clock signal, and the output terminal can output the Clear command signal (ACLR).

Moreover, when the enabling terminal (EN ₁ ) of the first counter 461 is connected to a high level, the first counter 461 can start counting the number of first clock pulses generated by the first clock signal. When the first counter 461 When the clear terminal (C ₁ ) inputs a high level, the count value of the first clock number in the first counter 461 will be reset to zero. When the two input terminals of the first comparator 462 , the second comparator 463 , the third comparator 464 and the fourth comparator 465 have the same value, the output terminal outputs a high level, otherwise the output terminal outputs a low level.

Please refer to FIG. 6 , which is a schematic diagram of the output signal of the command signal generating unit. When the clock generating device 42 generates the first clock signal, the first counter 461 will start to count the first clock and generate the first clock number, and transmit the first clock number to the first clock number through the output terminal (O ₁ ). A comparator 462 , a second comparator 463 , a third comparator 464 and a fourth comparator 465 . When the number of first clock pulses of the first counter 461 has not yet reached the M value, the output terminal (A ₁ =B ₁ ) of the first comparator 462 will output a low level to the inverter gate 466 and generate a high level Level output, and output a high level via the multiplexer 467 and the first D-type flip-flop 468, at this time the reference command signal (REF) is a high level, that is to say, calculate the first clock signal of the first clock signal When the number of clock pulses does not reach the M value, the reference command signal (REF) will be fixed at a high level.

When the first clock number of the first counter 461 reaches the M value, the output terminal (A ₁ =B ₁ ) of the first comparator 462 will output a high level to the inverter gate 466 and generate a low level level output, and output a low level via the multiplexer 467 and the first D-type flip-flop 468. At this time, the reference command signal (REF) is converted to a low level, and the selection terminal (S) of the multiplexer 467 is also The signal at the output terminal (A ₂ =B ₂ ) of the second comparator 463 is selected to be output to the first D-type flip-flop 468 .

Obviously, when the number of first clock pulses of the first counter 461 is greater than the M value and has not yet reached the M+R value, the output terminal (A ₂ =B ₂ ) of the second comparator 463 is maintained at a low level and is passed through multiple The output of the duplexer 467 and the first D-type flip-flop 468, so the reference command signal (REF) is maintained at a low level.

When the first clock number of the first counter 461 reaches the M+R value, the output terminal (A ₂ =B ₂ ) of the second comparator 463 will output a high level to the multiplexer 467 and the first D-type flip-flop 468 makes the reference command signal (REF) transition to a high level, and the selection terminal (S) of the multiplexer 467 will also select the inverted first comparator 462 output terminal (A ₁ =B ₁ ) to output to the second A D-type flip-flop 468. Obviously, when the first clock number of the first counter 461 reaches the M+R value, the output terminal (A ₁ =B ₁ ) of the first comparator 462 is maintained at a low level, so it becomes a high level after inversion. level, therefore, the reference command signal (REF) is maintained at a high level. At the same time, because the output terminal (A ₂ =B ₂ ) of the second comparator 463 simultaneously resets the first clock number in the first counter 461 to zero. Afterwards, since the number of first clocks is reset to zero and has not yet reached the M value, the output of the first comparator 462 (A ₁ =B ₁ ) remains at low level so that the reference command signal (REF) remains at high level.

Moreover, when the first clock number of the first counter 461 exceeds the M+Y value, the output terminal (A ₃ =B ₃ ) of the third comparator 464 will output a high level, so that the second D-type trigger The device 469 outputs a high level, so that the clear command signal (ACLR) generates a pulse wave with a clock width; similarly, when the first clock number of the first counter 461 reaches the value exceeding M+X, the fourth comparator The output terminal (A ₄ =B ₄ ) of the 465 will output a high level, that is, the load command signal (LD) generates a pulse wave with a clock width.

According to an embodiment of the present invention, R>Y>X. Therefore, as shown in FIG. 6 , the reference command signal (REF) periodically generates a high level for M clock times, and generates a low level for R clock times. Wherein, the number of M clocks can be defined as a counting period (Counting Duration), and the time of R clocks can be defined as a recovery period (Recovery Duration). The load command signal (LD) will periodically generate a pulse with a clock width when the first clock number is M+X. The clear command signal (ACLR) periodically generates a pulse wave with a clock width when the first clock number is M+Y.

Please refer to FIG. 7 , which is a circuit diagram of the command signal processing unit. The command signal processing unit includes a second counter 481, the enable terminal (EN ₂ ) of the second counter 481 can input the reference command signal (REF), and the clear terminal (C ₂ ) can input the clear command signal (ACLR), when The pulse input terminal can input the second clock signal; a third D-type flip-flop 482, the input terminal of the third D-type flip-flop 482 is connected to the output terminal (O ₂ ) of the second counter 481, and the clock pulse input terminal can input the load command signal (LD); j comparators 491-49j, the first input terminals of the j comparators 491-49j are connected to the output terminal of the third D-type flip-flop 482, and the j comparators The second input terminals of the comparators 491-49j can respectively input a preset comparison value (N1-Nj), and each of the j comparators 491-49j has a plurality of output terminals to represent the first input terminal of the comparator and the first input terminal of the comparator. The numerical comparison relationship between the two input terminals, for example, each comparator has three output terminals to represent that the value of the first input terminal of the comparator is less than the value of the second input terminal (A<B), and the first input terminal of the comparator The value at the terminal is equal to the value at the second input terminal (A=B), and the value at the first input terminal of the comparator is greater than the value at the second input terminal (A>B).

Furthermore, when the enabling terminal (EN ₂ ) of the second counter 481 is at a high level, the second counter 481 can start counting the number of a second clock generated by the second clock signal. When the second counter 481 When the clear terminal (C ₂ ) of the high level is input, the count value of the second clock number of the second counter 481 will be reset to zero. The j comparators 491 - 49j compare the numerical relationship between the first input terminal and the second input terminal, and output high level at the corresponding output terminals, while the other output terminals output low level.

When the command signal generation unit generates the reference command signal (REF) at a high level, that is, during the counting cycle, the second counter 481 will continue to count the second clock number of the second clock signal until the end of the counting cycle. That is, when the reference command signal (REF) is switched to a low level, the counting of the second clock signal is stopped.

When this counting cycle stops, that is, the recovery cycle starts, and the second clock number in the second counter 481 must wait for the load command signal (LD) to generate, and the second clock number will be latched (Latch ) at the output end of the third D-type flip-flop 482 . Therefore, the j comparators 491-49j can compare the numerical relationship between the second clock number of the first input terminal and the preset comparison value (N1-Nj) of the second input terminal, and respectively compare the values of the j comparators 491 ~ 49j produces comparison results.

During the recovery period, when the clear command signal (ACLR) is generated, the second clock number in the second counter 481 is reset to zero. Afterwards, when the reference command signal (REF) generated by the command signal generating unit is at a high level, the second counter 481 counts the second clock signal again and generates the second clock number again.

According to an embodiment of the present invention, the temperature of the chipset or the gate delay of the chipset can be known by monitoring the comparison results generated by the j comparators 491 - 49j. For example, assume that the relationship between the preset comparison values is N1<N2<...<Nj, and below N1 can be defined as the low temperature working range, between N1～N2 can be defined as the normal working temperature range, between N2～N3 It can be defined as the high temperature working range, and above N4 can be defined as the overheating working range. Since the load command signal and the clear command signal will be generated periodically, the second clock number will be periodically updated, and the output terminal of the third D-type flip-flop 482 will be periodically latched according to the load command signal. The number of second clocks to lock updates. Therefore, by monitoring the comparison results generated by the j comparators 491 - 49j, the temperature of the chipset or the gate delay of the chipset can be known at any time. For example, when the second clock number is less than N1, the A<B output terminal of the comparator 491 outputs a high level, and when the other output terminals are low level, the chipset can know that the chipset is in the low temperature operating range. Similarly, the chipset can also know that it is in the normal temperature working range, the high temperature working range or the overheating working range according to the comparison results generated by the j comparators 491-49j.

Furthermore, the chipset can also use the function (M×1/fosc×1/N×1/P) to estimate the gate delay in the chipset according to the comparison results generated by the j comparators 491˜49j. Wherein, (M×1/fosc) is the counting period, N is the second count value, and P is the number of inverter gates.

The spirit of the present invention is also applicable to the oscillator circuit built in the chip, and the basic components of the oscillator circuit include at least an odd number of inverter gates, for example, P inverter gates. The output terminal of the Pth inverter gate is fed back to the input terminal of the oscillator circuit. The odd number of inverter gates can be connected in series with any combination of AND gates, OR gates, etc., so that the input signal of the oscillating circuit can be output to the subsequent stage. The oscillating circuit outputs a clock signal, and the frequency of the clock signal is affected by the gate delay of the oscillating circuit or the temperature of the chip. Therefore, the gate delay of the oscillation circuit or the temperature of the chip can be obtained by receiving an external clock signal and comparing it.

To sum up, through the digital temperature sensing system and method of the present invention, the gate delay in the chip set can be estimated, and the temperature of the chip set can be obtained through the digital temperature sensing method, In this way, the common analog chipset temperature sensing system can solve the problems that the chip set takes up a large area, the cost increases caused by the complicated circuit design, and the problem that the internal gate delay of the chipset cannot be actually measured.

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements on this basis without departing from the spirit and scope of the present invention. Improvements and changes, so the protection scope of the present invention should be defined by the claims of the present application.

A brief description of the symbols in the drawings is as follows:

Conversion circuit: 10

Analog-to-digital conversion unit: 102

Signal temperature mapping unit: 104

Thermal Diodes: 12

Inverter gates: 20

Gate delay measurement device: 40

Command signal generation unit: 46

Command signal processing unit: 48

Clock generators: 42

P series inverter gate groups: 44

Claims (12)

1. a digital temperature sensing system is characterized in that, described digital temperature sensing system comprises:

One clock pulse generation device, this clock pulse generation device can produce one first clock signal of a fixed frequency;

One oscillatory circuit comprises P reverser door, makes exportable one second clock signal of this oscillatory circuit, and wherein P is an odd number;

One command signal generation unit, this command signal generation unit is connected to this clock pulse generation device, in order to produce a reference command signal according to this first clock signal, makes this reference command signal periodically to produce a count cycle; And

One command signal processing unit, this command signal processing unit are connected to this command signal generation unit and this oscillatory circuit, count a clock pulse number of this second clock signal when being used to this count cycle, and determine an operating temperature range according to this clock pulse number.

2. digital temperature sensing system according to claim 1 is characterized in that, this command signal processing unit can be estimated the gate delay time according to this clock pulse number when a restore cycle.

3. digital temperature sensing system according to claim 1 is characterized in that, the output terminal of P reverser door of this oscillatory circuit feeds back to the input end of this oscillatory circuit.

4. digital temperature sensing system according to claim 1 is characterized in that, this reference command signal can periodically produce this count cycle and a restore cycle, and determines this operating temperature range according to this clock pulse number when this restore cycle.

5. digital temperature sensing system according to claim 4, it is characterized in that, this command signal generation unit more can produce one and be written into command signal, makes this command signal processing unit to be written into command signal according to this when this restore cycle and upgrades this clock pulse number.

6. digital temperature sensing system according to claim 4, it is characterized in that, this command signal generation unit more can produce a clear command signal, make this command signal processing unit can be when this restore cycle according to this clear command signal this clock pulse number that makes zero.

7. digital temperature sensing system according to claim 1 is characterized in that, this command signal generation unit more comprises:

One first counter, the activation end of this first counter is connected to a high level, and the clock pulse input end of this first counter is connected to this first clock signal in order to calculate the one first clock pulse number that this first clock signal is produced;

One first comparer, the first input end of this first comparer is connected to the output terminal of this first counter, and second input end of this first comparer provides one first numerical value;

One second comparer, the first input end of this second comparer is connected to the output terminal of this first counter, and second input end of this second comparer provides a second value, and the output terminal of this second comparer is connected to the removing end of this first counter;

One the 3rd comparer, the first input end of the 3rd comparer is connected to the output terminal of this first counter, and second input end of the 3rd comparer provides a third value;

One the 4th comparer, the first input end of the 4th comparer is connected to the output terminal of this first counter, and second input end of the 4th comparer provides one the 4th numerical value, and the output terminal of the 4th comparer exportable is written into command signal;

One reverser door, the input end of this reverser door is connected to the output terminal of this first comparer;

One multiplexer, the first input end of this multiplexer is connected to the output terminal of this reverser door, and second input end of this multiplexer is connected to the output terminal of this second comparer;

One first D flip-flop, the input end of this first D flip-flop is connected to the output terminal of this multiplexer, the clock pulse input end of this first D flip-flop is connected to this first clock signal, and the output terminal of this first D flip-flop is connected to selecting side and exportable this reference command signal of this multiplexer; And

One second D flip-flop, the input end of this second D flip-flop is connected to the output terminal of the 3rd comparer, the clock pulse input end of this second D flip-flop is connected to this first clock signal, and the exportable clear command signal of the output terminal of this second D flip-flop.

8. digital temperature sensing system according to claim 7 is characterized in that, this is written into command signal and this clear command signal is to produce in regular turn in a restore cycle.

9. digital temperature sensing system according to claim 7 is characterized in that, this second value is greater than this third value, and this third value is greater than the 4th numerical value, and the 4th numerical value is greater than this first numerical value.

10. digital temperature sensing system according to claim 7 is characterized in that, this command signal processing unit comprises:

One second counter, the activation end of this second counter can be imported this reference command signal, and the removing end of this second counter can be imported this clear command signal, and the clock pulse input end of this second counter can be imported this second clock signal;

One the 3rd D flip-flop, the input end of the 3rd D flip-flop is connected to the output terminal of this second counter, and the clock pulse input end of the 3rd D flip-flop can be imported this and be written into command signal;

A plurality of comparers all are connected to the output terminal of the 3rd D flip-flop, and described comparer is all set different a plurality of default fiducial values, make this clock pulse number of output terminal of described default fiducial value and the 3rd D flip-flop compare, and an exportable comparative result.

11. digital temperature sensing system according to claim 10 is characterized in that, this operating temperature range is to be decided by this comparative result.

12. digital temperature sensing system according to claim 10 is characterized in that, the gate delay time is to be decided by this comparative result.

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