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CN1967897B - 管型相变化存储器形成方法 - Google Patents

管型相变化存储器形成方法 Download PDF

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CN1967897B
CN1967897B CN200610148450.0A CN200610148450A CN1967897B CN 1967897 B CN1967897 B CN 1967897B CN 200610148450 A CN200610148450 A CN 200610148450A CN 1967897 B CN1967897 B CN 1967897B
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hole
layer
programmable resistor
resistor material
phase change
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CN1967897A (zh
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龙翔澜
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/90—Bulk effect device making

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种存储器单元设备，包括下电极，包括相变化材料的管型部件及与管型部件接触的上电极。管型部件内侧有电绝缘及热绝缘材料。本发明还公开包括管型相变化存储器的集成电路。

Description

管型相变化存储器形成方法
相关申请案数据
本案于2005年11月14日申请美国临时专利申请，该申请的申请号为60/736,424，发明名称为管型相变化存储器及其制造方法。
联合研究合约的当事人
国际商业机械公司纽约公司、旺宏国际股份有限公司台湾公司及英飞凌技术公司(Infineon Technologies A.G.)德国公司为联合研究合约的当事人。
技术领域
本发明涉及可编程电阻材料为主的高密度存储器设备，例如相变化存储器材料，及制造该等设备的方法。
背景技术
硫属化物材料广泛用于读写光盘片。这些材料具有至少二种固态相，通常为非晶相及结晶相。激光脉冲用于读写光盘片以在这些状态之间切换及在相变化后读取材料的光学性质。
硫属化物材料也可以通过施加电流而改变状态。该性质有利于利用可编程电阻材料形成非易失性存储器电路。
目前发展的方向之一已经朝向利用少量的可编程电阻材料，尤其是细孔隙的绝缘材料。公开朝向细孔隙发展的专利有：Ovshinsky于1997年11月11日获得授权的美国专利5,687,112号、发明名称为“具尖形接触的多位单一单元存储器设备”(Multibit Signle Cell MemoryElement Having Tapered Contact)的专利，Zahorik等人于1998年8月4日获得授权的美国专利5,789,277号、发明名称为”制造硫属化物[sic]存储器设备的方法”(Method of Making Chalogenide[sic]Memory Device)的专利，Doan等人于2000年11月21日获得授权的美国专利6,150,253号，发明名称为”可控制双向相变化半导体存储器设备及其制造方法”(Controllable Ovonic Phase-ChangeSemiconductor Memory Device and Methods of Fabricating the Same)。
发明人的美国专利申请公开号US-2004-0026686-A1描述一种相变化存储器设备，其中相变化设备包括位于电极/介电层/电极堆栈结构上的侧壁。通过电流相变化材料在非晶与结晶状态之间做变化的方式储存数据。电流使材料提高温度，并且使状态改变。非晶变成结晶状态的变化通常是一种较低电流的操作。结晶到非晶状态的变化，在此称为重设，通常是一种较高的电流操作。使用于使相变化材料从结晶改变成非晶状态的重设电流最好是越小越好。可以通过缩小单元内有源相变化材料尺寸的方式，来减小重设所需的重设电流值。相变化存储器设备有关的问题之一为重设操作所需的电流大小视需要改变相状态的相变化材料体积而定。因此，利用标准集成电路工艺所得的单元一直被制造设备的特征尺寸所限。因此，必须发展出提供存储器单元的次平板印刷(sublithography)尺寸的技术，而此等技术可能缺乏大型高密度存储器设备所需的均匀性与可靠性。
因此，需要设计出一种利用可靠且可重复制造技术、以少量可编程电阻材料制得的存储器单元。
发明内容
本发明包括存储器设备及形成存储器单元的方法，其中存储器设备包括下电极，位于下电极上的填充层，从填充层上表面延伸至下电极上表面的通孔，及在通孔里面由例如相变化材料等可编程绝缘材料做成的共形层。共形层与下电极接触，并沿着通孔侧边延伸至上表面，在通孔内形成管状构件。与共形层接触的上电极重迭于填充层。电绝缘及热绝缘材料填满通孔的其余部分。代表性的绝缘材料包括基本上透空的材料，或低导热性固态材料，例如二氧化硅，或远小于二氧化硅导热性的材料。
本发明还包括一种制造管状相变化存储器单元的方法，包括形成具有上表面的下电极，及在电极上形成填充层，其中通孔从填充层上表面延伸至下电极上表面。在通孔内沉积可编程绝缘材料的共形层，从下电极上表面沿着通孔侧边延伸至填充层上表面。最后，在填充层上形成上电极与共形层接触。在具体实施例里，形成下电极的步骤及形成填充层的步骤包括首先在读取设备终端上形成填充层。然后，形成穿透填充层至终端的通孔。然后在通孔内填满导体，以形成导电插头。然后将导体部份从通孔移除，使通孔里面导电插头的其余部分做为下电极，因移除导电材料而曝露出的通孔部份作为其内沉积共形层的通孔。
本发明另公开一种包括存储器阵列的集成电路，包括多个以行列高密度阵列方式排列的存储器设备及存取晶体管。存取晶体管包括位于半底体衬底内的源极及漏极区域，及沿着存储器单元列向连接字线的栅极。存储器单元形成在集成电路的存取晶体管上的一层内，其中下电极与对应存取晶体管的漏极接触。利用金属化层在存储器单元上形成位线，与沿着阵列存储器单元行向存储器设备上的上电极接触。在具体实施例里，二列存储器单元共享源极通孔，共享源极线连接源极通孔并且通常经阵列平行延伸至字线。
本发明另提供一种低重设电流的可靠存储器单元结构，利用标准平板印刷蚀刻沉积工艺制成，不需要形成次平板印刷蚀刻工艺的特别技术。单元结构尤其适合于集成大规模集成电路设备上的CMOS电路。
以下详细说明本发明的结构与方法。本发明内容说明部分的目的并非在于限定本发明。本发明由权利要求所定义。凡本发明的实施例、特征、观点及优点等将可通过下列说明权利要求及附图获得充分了解。
附图说明
图1示出根据一具体实施例的一种具可编程电阻材料管型构件的存储器单元的剖面图；
图2示出根据一具体实施例的一种具可编程电阻材料管型构件的存储器单元的透视图；
图3示出包括如图1所示的存储器单元的存储器阵列电路示意图；
图4示出包括管型的根据一具体实施例的一种具可编程电阻材料管型构件的存储器单元的剖面图；
图5示出根据一具体实施例的一种最终阵列结构的剖面图；
图6至图13示出管型相变化存储器单元的制造方法的各个阶段；
图14示出用于描述存储器单元中电流及有源区域的管型相变化存储器单元；及
图15示出管型相变化存储器单元阵列的布局。
主要设备符号说明
10               管型相变化存储器单元
11               下电极
12               管型部件
13               绝缘材料
14               管型部件的顶部
15               封闭终端
36               桥段
12a              内表面
28               共享源极线
23，24           字线
41，42           位线
50，51，52，53   存取晶体管
35，36           管型存储器单元
32，33           下电极设备
34，37           上电极设备
75               集成电路
74               其它电路
60               存储器阵列
61列解码器
62字线
63行解码器
64位线
65总线
66感测放大器及数据输入结构
67数据总线
68供应电压
69偏压设置状态机
71数据输入线
72数据输出线
100，101，102，103管型相变化随机存储器单元
110半导体衬底
111，112介质沟渠
116共用源极区域(掺杂区域)
115，117漏极区域(掺杂区域)
113，114多晶硅字线
113，114                   多晶硅字线
118介质填充层
121，120插头结构(下电极)
119共用源极线
122，123金属层(接触层)
124绝缘层
101单元
99结构
131，132，134，135插头
130填充层上表面
133金属线(多晶硅字线)
140绝缘填充层
141，142，144，145通孔
148编程电阻材料共形层
149               绝缘填充层
150               管型部件的顶部
151               绝缘填充层
200               下电极
210               上表面
201               管型部件
202               接触层
203               位线层
204               界面材料
205，206，207     重设期间的电流
208，209          有源区域
300               接地线300
301，302          位线
303，304          位线
311，312，313，314管型相变化单元
具体实施方式
图1示出管型相变化存储器设备10的剖面示意图。设备包括下电极11，及管型部件12，其中管型部件12包括可编程电阻材料。管型部件12填充绝缘材料13，该绝缘材料13优选的具有低导热性。上电极(未示出)与管型部件的顶部14电连接。在具体实施例里，管型部件具有封闭终端15，该终端与下电极11的上表面电连接。管型部件内的填充部份13可包括氧化硅，氧氮化硅，氮化硅，Al2O3，其它低k值(低介电常数)介质材料，或ONO或SONO多层结构。或者是填充部份可包括电绝缘体，包括一个或多个选自一组由硅(Si)、钛(Ti)、铝(Al)、钽(Ta)、氮N及碳(C)所组成的族群构成的设备。在优选设备示例中，填充部份具低导热性，小于0.014J/cm·deg K·sec。代表性热绝缘材料包括具硅(Si)、碳(C)、氧(O)、氟(F)及氢(H)等组合。做为热绝缘覆盖层的热绝缘材料例如包括氧化硅(SiO2)、SiCOH、聚酰亚胺及氟碳聚合物。作为热绝缘覆盖层的材料的其它实例包括氟氧
化硅、倍半氧硅烷(silsesquioxane)、聚环烯醚(polyarylene ether)、对二甲苯聚体(parylene)、氟聚合物、氟化无定型碳、类钻石碳、多孔性氧化硅、介多孔(mesoporous)氧化硅、多孔性倍半氧硅烷、多孔性聚亚酰胺及多孔性环烯醚。在其它具体实施例里，热绝缘结构包括位于介质填充部分内横跨桥段36以提供热绝缘作用的填充栅极空隙。管里面的单层或多层可以提供热绝缘及电绝缘作用。
在具体实施例里，管型部件没有填充固态材料，而是以上电极(未于图中显示)封闭，但留有大致抽真空的孔洞，因而管型部件具有低导热性的空隙。
管型部件包括内表面12a及外表面12b，该内表面12a及外表面12b为圆筒状。因此，内侧及外表面12a及12b可以是基本上为柱状表面，通常定义为由平行于固定线移动及与固定曲线相交所描绘出的表面，其中对于圆柱体而言，固定线位于管型设备中心处而固定曲线为固定线位于中心处的圆形。该圆柱体的内侧及外表面12a及12b将由因管型设备壁厚度而异的半径的个别圆圈所定义，因此内侧及外表面12a及12b定义出管型设备的内侧及外侧直径。在管型设备的具体实施例里，柱体形状具有圆形、椭圆形、矩形或不规则形的外周缘，根据用以形成管型部件的制造技术而定。
在此所述的具体实施例里，管型部件通过形成于开口在填充层内的通孔侧边上的薄膜，类似沉积通孔衬层材料，例如氮化钛(TiN)薄膜，用于形成钨插头以达到改善钨的粘附性的目的。因此，管型部件壁可以非常薄，如以在通孔内沉积薄膜的方法。同样地，下电极11可以包括导体，如通孔内所沉积的钨。
图2示出图1的单元的立体图，其中以固体填充部份示出割除部份。图2中管型部件为具圆形外缘形状的圆柱体。另一具体实施例里，外缘形状基本上是方形或矩形。通常，管型部件12的外缘形状为由管型部件12形成于其内的通孔以及形成通孔的方法决定。
在此所述的管型单元10可利用标准平板印刷蚀刻及薄膜沉积工艺制造，不需要特殊步骤形成次平板印刷蚀刻图案，而可达到非常小尺寸的单元区域，其中该单元区域实际上在编程期间改变绝缘性。可编程电阻材料包括相变化材料，例如Ge2Sb2Te5或其它于以下所描述的材料。单元10内的相变化区域很小，因此，相变化所需的重设电流很小。
存储器单元的具体实施例包括相变化材料为主的存储器，包括硫化物为主的材料及其它管型部件12所用的材料。硫族元素(Chalcogen)包括氧(O)、硫(S)、硒(Se)及碲(Te)四个化学周期表上VI族的一部份元素中任何一个。硫化物包括硫族元素与多个带正电元素或取代基的化合物。硫化物合金包括硫化物与其它如过渡金属材料的组合。硫化物通常包含一种或一种以上选自元素周期表第六栏的其它元素，例如锗(Ge)及锡(Sn)。通常，硫化物合金包括含有锑(Sb)，镓(Ga)，铟(In)及银(Ag)其中一种或多种的组合。许多以相变化为主的存储器材料已经被在技术文献中公开，包括Ga/Sb，In/Sb，In/Se，Sb/Te，Ge/Te，Ge/Sb/Te，In/Sb/Te，Ga/Se/Te，Sn/Sb/Te，In/Sb/Ge，Ag/In/Sb/Te，Ge/Sn/Sb/Te，Ge/Sb/Se/Te及Te/Ge/Sb/S的合金。在Ge/Sb/Te合金族里，有许多的合金组成可以使用。组成的特征在于TeaGebSb100-(a+b)，其中a及b代表占构成元素总原子数的原子百分比。有一位研究人员指出最有用的合金为Te在已经沉积的材料内的平均浓度远低于70％，通常低于约60％且一般低到约23％而高到约58％Te，最佳为约48％到58％Te。Ge的浓度超过约5％，平均材料内的Ge浓度从约8％到约30％，一般保持低于50％。最佳地，Ge的浓度从约8％到约40％。组成内其余的主要构成元素为Sb。(Ovshinsky‘112专利第10-11栏)。特别被其它研究人员肯定的合金包括Ge2Sb2Te5，GeSb2Te4及GeSb4Te7(Noboru Yamada，“Ge-Sb-Te相变化光盘在高数据速度记录上的可能性”(Potential of Ge-Sb-Te Phase-产个Optical Disks for High-Data-Rate Recording)SPIE v.3109，pp.28-37(1997)。更一般而言，过渡金属，例如铬(Cr)，铁(Fe)，镍(Ni)，铌(Ni)，钯(Pd)，铂(Pt)及混合物或合金可与Ge/Sb/Te形成可编程绝缘性质的相变化合金。有用的存储器材料的特定实例请参考Ovshinky’112第11-13栏所述，该公开内容在此以参考方式并入本案。
相变化材料能在单元的有源通孔区域内依其位置顺序在材料为一般非晶状态的第一结构状态与为一般结晶固体状态的第二结构状态之间切换。这些相变化材料至少是双稳态的(bistable)。在此所称非晶指相当没有秩序的结构，比单晶更无秩序，具有可被检测的特征，例如比结晶状态更高的电绝缘性。在此所称的结晶性指相当有秩序的结构，比非晶结构更有秩序，具有可被检测的特征，例如比非晶状态更低的电绝缘性。典型而言，相变化材料可以在不同可被检测状态间电切换以跨越完全非晶及完全结晶状态之间的光谱。受到非晶及结晶相之间变化影响的其它材料特征包括原子顺序，自由电子密度及活化能。材料可以转换至不同固态相或转换至二个或更多的固态相，以提供介于完全非晶及完全结晶状态之间的灰色地带。此材料的电性质也可以据此对应地改变。
相变化材料可以通过施加电脉冲从一相状态变化成另一相状态。已经观察出一较短较高振幅脉冲容易使相变化材料变成一般非晶状态，一般称作为重设脉冲。较长较低振幅脉冲容易使相变化材料变成通常结晶状态，一般称作为编程脉冲。较短较长振幅脉冲内的能量高到使结晶结构的键结断裂，并且短到足以避免原子重新排成结晶状态。适合脉冲的状况可以依照经验法则判断，不需要过多的实验，而能找出适用于特定的相变化材料及设备结构的条件。
下列说明里，相变化材料称为GST，应了解其它类型相变化材料也可以使用。用以实施在此所述的存储器单元的材料为Ge2Sb2Te5。
例如相变化材料的可编程电阻材料的有用特征，包括可编程电阻材料，通过可调变电阻，且最好是可逆方式，如有着二个固态晶相的方式被以可逆方式用电流编程。这些至少二个相包括非晶及结晶相。然而，操作时可编程电阻材料可以不完全转化成非晶或结晶相。中间相或这些相的混合可以具有可被侦测的材料特征差异。这二个固态相一般应为双稳态(bistable)且具有不同电学性质。可编程电阻材料可以是硫属化物。硫属化物可以包括GST。或者，可编程电阻材料可以是上述其它相变化材料中的一种。
图3为在此实施的存储器阵列的示意图。图3的示意图里，共用源极线28，字线23及字线24通常设置于Y方向。位线41及42通常设置于X方向。因此，方块45内Y解码器与字线驱动器连接至字线23及24，而方块46内X解码器与一组感测放大器连接至位线41及42。共用源极线28连接存取晶体管50，51，52及53的源极端点。存取晶体管50的栅极连接至线23。存取晶体管51的栅极连接至字线24。存取晶体管52的栅极连接至字线23。存取晶体管53的栅极耦接至字线24。存取晶体管50的漏极连接管型存储器单元35(也具有上电极设备34)的下电极设备32。上电极设备34连接至位线41。同样地，存取晶体管51的漏极连接至管型存储器单元36(也具有上电极设备37)的下电极部件33。上电极部件37连接至位线41。存取晶体管52及53连接至对应管型存储器单元及连接至位线42上。可以看出共用源极线28与二列存储器单元共享，其中一列位于示意图中的Y方向。在其它具体实施例里，存取晶体管可以由二极管替代，或被其它控制电流至读取及写入数据阵列里所选设备的结构取代。
图4为根据本发明的具体实施例的一种集成电路的简化电路方块图。集成电路74包括利用半导体衬底上管型相变化存储器单元实施的存储器阵列60。列解码器61连接至多个字线62，并且沿着存储器阵列60的列向排列。行解码器63从阵列60内侧边管脚存储器单元连接多个沿着读取及编程数据的存储器阵列60排列的位线64。方块66内的感测放大器及数据输入结构连接行解码器63。地址会提供在总线65上给行解码器63及列解码器61。方块66内的感测放大器及数据输入结构经数据总线67连接至行解码器63。数据经数据输入线71从集成电路75上的输入/输出端口提供或从其它集成电路内部电路74或外部数据来源提供至方块66内的数据输入结构。在所示的具体实施例里，其它电路包括在集成电路上，例如通用处理器或专用应用电路，或由薄膜熔线脉冲相变化存储器单元阵列所支持提供系统上有芯片功能的模块组合。数据经数据输出线72从方块66内的感测放大器输出至集成电路75上的输入/输出端口，或输出至集成电路75内部或外部的数据终端。
本实施例里利用偏压设置状态机69实施的控制器控制偏压设置供应电压68，例如读取，编程，擦除，擦除验证及编程验证电压等的施加。控制器可以如本领域的技术人员所知，利用专用逻辑电路实施。在另一具体实施例里，控制器包括可以在相同集成电路上实施的通用处理器，执行电路编程以控制设备的操作。在又一具体实施例里，专用逻辑电路及通用处理器的组合可以用于实施控制器。
图5为多个管型相变化随机存储器单元100-103的剖面图。单元100-103形成于半导体衬底110上。隔离结构，例如浅沟渠隔离STI介质沟渠111及112将衬底110内共用源极区域116与衬底110内漏极区域115及117隔离。多晶硅字线113及114形成存取晶体管的栅极。介质填充层118形成于多晶硅字线113，114上。接触插头结构121及120与各自读取晶体管漏极接触，共用源极线119沿着阵列内的列与源极区域接触。共用源极线119接触共用源极区域116，及包括将其与金属层122，123隔离的绝缘层124。插头结构120做为单元101的下电极。插头结构121做为单元120的下电极。单元101，如单元100，102及103一样，包括含有上GST或其它图1所示相变化材料的管型部件。经图案化的金属层提供单元100-103的上电极，包括含有接触GST的材料(例如TiN)的第一接触层122，及利用标准金属化技术(包括例如Cu或Al为主的金属)所形成的第二层123。
在代表性具体实施例里，插头结构包括钨插头。其它类型的导电性金属也可以使用，例如包括铝及铝合金，氮化钛(TiN)，氮化钽(TaN)，氮化钛铝(TiAlN)或氮化钽铝(TaAlN)。可以使用的其它导体包括一种或一种以上选自钛(Ti)，钨(W)，钼(Mo)，铝(Al)，钽(Ta)，铜(Cu)，铂(Pt)，铱(Ir)，镧(La)，镍(Ni)，钌(Ru)及氧(O)组成的组。
图6-13为图5所示的管型存储器单元的制造过程图。图6为在前端制程后的结构99，在所述具体实施里对应字线形成标准CMOS设备，及形成图5阵列内的存取晶体管。此外，插头131，132，134及135也被包括，形成于对应的通孔内，经由填充层118从填充层上表面130延伸至对应存取晶体管的漏极终端(115，117)。金属线133形成于填充层118内的沟渠里，并沿着字线113及114之间的存取晶体管的列延伸。在制造过程的具体实施例里，金属线133及插头131，132，134及135使用标准的钨插头技术形成，并且具有以用于图案化插头的通孔的平板印刷蚀刻工艺定义的尺寸。在图6里，金属线133位于半导体衬底内的掺杂区域116上，其中掺杂区域116对应图标左侧第一存取晶体管的源极端点，及图示右侧第二存取晶体管的源极端点。该阶段时，金属线133延伸至填充层118的上表面。掺杂区域115对应第一存取晶体管的漏极端点。包括多晶硅的字的线113，及硅化物顶层(未示出)，作为第一存取晶体管的栅极。填充层118包括一介质电材料，例如二氧化硅并且位于多晶硅字线133上。插头132接触掺杂区域115，并且延伸至结构99的表面130。第二存取晶体管的漏极端点由掺杂区域117提供。包括多晶硅线114的字线，及硅化物顶层(未示出)作为第二存取晶体管的栅极。插头134接触掺杂区域117并且延伸至结构99的上表面130。隔离沟渠111及112使包括漏极端点115及117的二晶体管结构从二晶体管结构分离。
图7为制造过程的下一阶段。在图7所示的阶段里，利用标准平板印刷蚀刻工艺形成包括掩模136及137的光阻图案。掩模136及137保护插头132，133，134，135并且使金属线133的顶部曝露出来。将金属线133的顶部回蚀，使得其在结构的表面138低于填充层118的上表面130。剩余的结构变成图5所示的源极线119。回蚀工艺可以利用钨金属所用以氟为主的反应性离子蚀刻工艺进行。在回蚀后，移除光阻掩模136及137，且如图8所示，绝缘填充层140沉积于剩余的结构上，填充沟渠至超过源极线119。绝缘薄膜可以包括二氧化硅或利用其它一般本领域的技术人员所知的化学汽相沉积，等离子增强化学汽相沉积，高密度等离子化学汽相沉积等所沉积的介质材料。
下一制造过程阶段示于图9，在利用化学机械抛光等移除绝缘层140至填充层118的表面130下，然而留下绝缘材料140的插头在源极线119上。
如图10所示，接着，进行回蚀，以从插头131，132，134，135移除图9抛光阶段后露出的金属。可以利用上述移除钨金属插头所用以氟为主的离子蚀刻的方式进行回蚀。回蚀留下通孔141，142，144，145在由回蚀工艺后所剩钨插头形成的下电极120，121上。各具体实施例里插头120，121的高度约为100nm，插头宽度约为80nm。该实施例里，回蚀后留下的通孔141-145的深度少于200nm。
图11为例如通过溅镀一GST或其它可编程电阻材料共形层148在填充层内的通孔141-145上进行沉积后形成的结构。GST可以利用在约250℃以准直溅镀方式沉积。或者，GST可以利用金属有机化学汽相沉积(MO-CVD)工艺沉积。在代表性具体实施例里，共形层148包括薄膜，该薄膜的厚度从上表面算起约60-80nm，通孔的侧边上的厚度小于30nm，典型约为10-30nm，包括在通孔的底部内有一层。材料共形于通孔的壁上，且如图11所示，通孔里面掩模区域表示材料没有填满通孔，而是留下管型设备在上述通孔壁上。在另一技术里，原子层沉积或化学汽相沉积可以用于形成层148，根据所选可编程电阻材料及所要单元尺寸而定。
图12为下一个阶段，将绝缘填充层149沉积于图11所示的结构上。在具体实施例里，填充层149包括利用低于约200℃的工艺温度在可编程电阻材料上形成的低温衬层绝缘体，例如氮化硅层或氧化硅层(未示出)。适当的低温工艺利用等离子增强化学汽相沉积PECVD涂布二氧化硅。在形成衬层后，利用较高温度工艺，例如二氧化硅或其它类似材料的高密度等离子HDP CVD完成介质填充层149。
如图13所示，应用氧化物化学机械抛光CMP工艺进行平坦化结构的表面130或该表面附近，并使暴露管型部件的顶部(例如150)，留下绝缘填充层151在管型部件里面，并且使源极线119上的绝缘体140。在CMP后，利用位线进行金属化制程以定义上电极，如图5所示。
图14为管型相变化存储器单元的剖面图，其中管型相变化存储器单元包括下电极200，包括接触下电极200的上表面210的管型部件201，包括接触层202及位线层203的上电极。该具体实施例里，管型部件201被填满介质材料204，例如二氧化硅，或更佳地为导热性比二氧化硅低的介质材料。箭头205，206及207说明所示具体实施例里重设期间的电流。电流从与下电极200接触的读取设备的一端点，往上流向管型部件201的侧边，最后经由包括层202及203的金属线流出。有源区域通常以方块208，209表示，由于电流通过而发热进而发生相变化的相变化材料内位于管型部件远离下电极200侧边的上方。该单元的特征为通过避免下电极200与管型部件201之间界面处发生相变化的方式来改善设备的可靠性。同样地，该特征建立一小区域，其中相变化材料为有源的，由此降低重设所需的电流大小。
所述的具体实施例里，在单元周边的管型部件的侧边为连续的。或者，沉积技术应可以用于使管型部件的侧边不连续，进一步减小有源区域208，209内相变化材料的体积。
图15为包括管型相变化存储器单元的存储器阵列的布局，如图15所示。阵列包括接地线300，及位线301，302，这些线平行配置。位线303及304正交于字线301，302。管型相变化单元311，312，313，314位于位线303，304底下，相邻于字线。如图所示，该具体实施例里的管型部件为方柱体或长柱体。如上所述，管型部件可以是圆柱体或其它形状，根据形成通孔期间所用的制造技术而定。在较佳具体实施例里，利用标准平板印刷蚀刻技术制造其尺寸对应用以形成通孔的工艺最小特征尺寸的单元，而不需要形成次平板印刷蚀刻掩模。
虽然本发明已参照较佳实施例加以描述，可以了解的是，本发明创作并不受限于其详细描述内容。替换方式及修改方式已于先前描述中进行建议，并且其它替换方式及修改模式将为本领域的技术人员可想到的。特别是，根据本发明的结构与方法，所有具有实质上相同于本发明的构件结合而达成与本发明实质上相同结果的皆不脱离本发明的精神范畴。因此，所有这些替换方式及修改方式意在落入本发明所附权利要求及其等价物所界定的范畴之中。

Claims (18)

1.一种形成存储单元的方法，其包含：
在源极终端或漏极终端上形成填充层；
形成穿透该填充层至该源极终端或漏极终端的通孔；
在该通孔内填满导体，以形成导电插头；
将部分该导体从该通孔内移除，其中该通孔内的该导电插头的其余部分做为下电极；
在该通孔内形成可编程电阻材料的共形层，该共形层包含管型构件；
以及
在该填充层上形成与该管型构件相接的上电极。
2.如权利要求1所述的方法，包含密封该共形层上方的该通孔以使热绝缘空隙形成于该上电极之下的该通孔中。
3.如权利要求1所述的方法，包含以绝缘材料填充于该共形层上的该通孔。
4.如权利要求1所述的方法，包含以导热性小于0.014J/cm·degK·sec的电绝缘材料填充于该共形层上的该通孔。
5.如权利要求1所述的方法，其中该部分移除包含以氟为主的反应性离子蚀刻工艺对该导体进行蚀刻。
6.如权利要求1所述的方法，其中该通孔由该填充层的上表面至该下电极的上表面的的深度少于200nm。
7.如权利要求1所述的方法，其中该可编程电阻材料在该管型构件中的厚度小于30nm。
8.如权利要求1所述的方法，其中该可编程电阻材料包含硫属化物。
9.如权利要求1所述的方法，其中该可编程电阻材料具有至少二个可由一电流引发的可逆的固态相。
10.如权利要求1所述的方法，其中该可编程电阻材料具有至少二个固态相，一个为非晶相，另一个为结晶相。
11.如权利要求1所述的方法，其中该可编程电阻材料包括Ge2Sb2Te5。
12.如权利要求1所述的方法，其中该可编程电阻材料包括二种或二种以上从由锗、锑、碲、硒、铟、钛、镓、铋、锡、铜、钯、铅、银、硫及金所组成的族群的材料组合中选择。
13.一种形成存储单元的方法，该方法包含：
在源极终端或漏极终端上先形成填充层，该填充层具有上表面；
形成宽度少于100nm的通孔，该通孔自该填充层延伸至该源极终端或漏极终端，且该通孔在该填充层中定义一开口，并具有用在使用平版印刷以图形化该通孔的最小特征尺寸的一宽度；
在该通孔内填满一导体，以形成导电插头；
将部分该导体从该通孔内移除，其中该通孔内的该导电插头的其余部分做为具有上表面的下电极；
在该通孔内形成可编程电阻材料的共形层，该共形层与该下电极的上表面接触，并沿着该通孔侧边延伸至该填充层的上表面，其中该共形层在该通孔一侧的厚度小于30nm，并且该可编程电阻材料以具有至少二个可由一电流引发的可逆的固态相为特征；以及
在该填充层上形成与该共形层接触的上电极。
14.如权利要求13所述的方法，其中该可编程电阻材料包括Ge2Sb2Te5。
15.如权利要求13所述的方法，其中该可编程电阻材料包括二种或二种以上从由锗、锑、碲、硒、铟、钛、镓、铋、锡、铜、钯、铅、银、硫及金所组成的族群的材料组合中选择。
16.如权利要求13所述的方法，包含以绝缘材料填充于该共形层上的该通孔。
17.如权利要求13所述的方法，包含以导热性小于0.014J/cm·degK·sec的电绝缘材料填充于该共形层上的该通孔。
18.如权利要求13所述的方法，包含密封该共形层上的该通孔以使热绝缘空隙处于该上电极之下的该通孔中。
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US20070108429A1 (en) 2007-05-17

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