CN1967274A - Automatic test technology of ASIC device - Google Patents
Automatic test technology of ASIC device Download PDFInfo
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- CN1967274A CN1967274A CN 200510019839 CN200510019839A CN1967274A CN 1967274 A CN1967274 A CN 1967274A CN 200510019839 CN200510019839 CN 200510019839 CN 200510019839 A CN200510019839 A CN 200510019839A CN 1967274 A CN1967274 A CN 1967274A
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Abstract
The invention discloses an automatic ASIC device test technology, including reorganized S10 LSI test system, PC, Simulator, S10 VLSI test system and the PC, RS232 link between PC and simulator, description generated logic test procedure used in the PC, or the design source files generated test procedure, or device generated test procedures, PC and S10 VLSI test system automatically switching, automatically compiling, loading and testing on LSI testing system. Its advantages include no drawing different software for different type device with ASIC devices, as long as the use of design documents, or logical description, or the device can be tested procedure, which improve efficiency and save a lot of manpower and material resources.
Description
Technical field
The present invention relates to chip automatic test technology field, specifically a kind of automatic test technology of ASIC device.
Background technology
Present general chip automatic test technology, (for example be at test macro, the S10 test macro) in, will change a large amount of time to different chips, exploitation establishment test procedure just can be finished automatic test, workload is big like this, and very loaded down with trivial details, work efficiency is very low, and waste of human resource is very big.
Summary of the invention
The objective of the invention is on original S10 test macro basis, to link a PC and emulator, reformulate a system.In this new system, design a kind of software that can realize that test procedure generates automatically, and be loaded into the automatic test technology of the ASIC device of finishing automatic test in the S10 system automatically.
The automatic test technology of ASIC device of the present invention comprises: reorganization S10 LSI testing system, PC, emulator.Connect with RS232 between S10 LSI testing system and PC, PC and the emulator, in PC, use logical description to generate test procedure, or use the design source file to generate test procedure, or use gold vessel spare to generate test procedure, PC and S10 LSI testing system automatically switch, automatically compiling loads test on LSI testing system.
Use design source file generation test procedure to be: at first in the programming file interaction input PC in the design source file, mutual simultaneously other formation condition of importing then generates S10 graphics test sign indicating number automatically, generates test procedure automatically by the graphics test sign indicating number.
Using logical description to generate test procedure is according to logical description; To mutual entering apparatus model, PIN in the PC distribute, logical description, mutual simultaneously other formation condition of input generates S10 graphics test sign indicating number automatically in the PC, generate test procedure automatically with the graphics test sign indicating number.
Use gold vessel spare generation test block to be: utilize gold vessel spare to exchange the entering apparatus title in PC, exchange simultaneously is other formation condition of input mutually, then generates the graphics test sign indicating number in the PC automatically, generates test procedure automatically by the graphics test sign indicating number.
Used software is formed:
Operating system: DOS (PC) and M
3(S10),
Programming language: ABEL, Turbo C (PC) and FACTOR (S10).
DOS and M
3Two operating systems between switching and message exchange operation, finish by xenogenesis machine communication program.
Workflow:
Native system is one and contains the connection of xenogenesis machine, a plurality of language cross compiles, two common complication systems of supporting of operating system.It is used support programs and is divided into the two large divisions, and a part is moved under the DOS of PC environment; Another part is at the M of S-10
3Environment is operation down.
Main execution module is to comprise that input produces and the test code generator and the S-10 test procedure generator of simulated operation under the DOS environment;
At M
3Main execution module is automatic compiling, loading, test module under the environment.
Working routine title (inlet): ASICATPG
Application conditions:
Use ASICATPG, need possess one of following three conditions: one gold vessel spare/programming file/oneself knows the logical expression between the pipe leg.
Gold vessel spare be one oneself know intact device; The programming file is half formulation device is fired dedicated devices on programmable device a file; Logical expression is the logical description of chip pipe leg.They all are the inputs of logic simulation and emulation, are the keys that generates the test pattern font code automatically.
Detailed implementation procedure
The automatic generation of test procedure
The automatic generation of ASIC testing program is the key of this project.The automatic generation of test procedure divides automatic generation two parts of automatic generation of resolution chart and test procedure.
Resolution chart generates automatically, mainly relies on the logic simulation/emulation of pattern generator to the logical expression between gold vessel spare/programming file/pipe leg, generates graphic code automatically.Resolution chart occurring mode: sequential circuit: state is exhaustive, non-sequential (logic) circuit: exhaustive
The automatic generation of test procedure mainly relies on the test procedure generator to finish the automatic generation of the test procedure of chip.Test procedure feature: speed 10MHz; Test event contains at least: the DC parameter testing of the AC parameter testing that functional test, electric power pulling bias testing, TPDLH and TPDHL equal time postpone, ICC, ICCL, ICCH, IOS, IIL, IIH, II, VIK, VIL, VIH, VOL, VOH etc.Owing in the automatic generation of test procedure, implemented the design for Measurability technology, so all parameters can both quantitative description.
The graphic code of sequential circuit is reused:
The graphic code of sequential circuit can produce Different Results under different situations.So sequential circuit has figure to reuse problem.The graphic code of sequential circuit is reused problem, and I what adopt introducing sequential circuit initialization vector to solve.Obtaining of sequential circuit initialization vector adopts dynamically to reset by force or mutual bootstrap technique solution.
Dynamically reset by force and be applicable to the GAL device.Automatically reset characteristics are arranged after we utilize it to power on, guarantee that the test vector that generates can both infinitely repeatedly use.
Mutual guiding is applicable to the PAL device, and so the automatically reset characteristics in back because the PAL device does not power on are only by means of mutual guide means.In mutual guiding the user can utilize device some control characteristic such as zero clearing, reset etc., conveniently select initialization vector, submit the test code generator approval to, use.
Automatic location during DC test
In testing automatically, must solve the state uncertain problem in the dc parameter test.We adopt automatic positioning technology, solve which one leg of the device that we can't know in advance, show as high state in which bar truth table, perhaps show as low state.Thereby, realize the correct test of all test events.
Automatic switchover between system
DOS and M
3Automatic switchover between system and message exchange are finished by xenogenesis machine communication program.Its communication host-host protocol:
Use the rs-232 standard signal;
Character format;
Baud rate: 9600, verification mode: N, data bit: 8, position of rest: 1.
Here 8 of data bit are vital, and the transmission that it makes the S10 test macro finish a word length with three transmission operations becomes possibility.
Automatically compiling, loading and test
Automatic compiling, loading and test on the S10 LSI testing system are by M
3Command procedure is finished.
The detailed operation instructions of appendix: ASICATPG
The detailed operation instructions of ASICATPG
Design object
The automatic test operation platform of ASICATPG is one PC and S-10 test macro is connected as a single entity, the Auto-Test System that is specifically designed to the ASIC device that is formed by some application software supports.Its function is the logical description that provides according to the user or programming file etc., generates the test procedure of S-10 automatically, and is loaded into automatically on the S-10 test macro and tests.The functional test coverage rate can reach 100%.
Running environment
Hardware: PC and S-10 test macro
Software: operating system: DOS and M3.
Language: FACTOR and ABEL (PALASM).
The executive routine name
ASICATPG
The destination file name
S.2SC---the test source file (all existing on S-10 and the PC) that generates automatically.
T.TP---the test TP file (only on S-10, existing) that generates automatically.
The advantage of the automatic test technology of ASIC device of the present invention is: avoided will compiling different program softwares to the different model device of ASIC device, as long as utilize design document, or logical description, or gold vessel spare just can obtain test procedure, both raised the efficiency, saved great amount of manpower and material resources again.
Description of drawings
Fig. 1 is a system schematic.
Fig. 2 is a block scheme.
Embodiment
Operating process
Under the WINDOWS environment, select icon ASICATPG, change 1.1 joints (using logical description to generate test procedure).
Select icon ASICTEST, change 5.2 joints (using PLD design source file to generate test procedure).
Select icon ASICANA, change 5.3 joints (using gold vessel spare to generate test procedure)
1.1 generate the reciprocal process of test procedure automatically with logical description
0 step: system's demonstration is welcome to enter and is utilized logical description to generate test procedure.
*****Please?use?ASICATPGG?by?logical?specification*****
1 step: prompting entering apparatus name: Please input dev-name:
Answer: (example :) P7022 ↓
2 steps: prompting entering apparatus model: Please input dev-type:
Answer: (example :) P16V8R ↓
3 steps: whether demonstration and inquiry will revise device name/model of having imported:
dev-name＝P7022，dev-type＝P16V8R
Are?you?change?the?dev-name/type？(Yes＝1/No＝0)
Answer: 1 changeed for the 1st step, and 0 changeed for the 4th step.
4 steps: according to the actual pipe leg distribution input leg name (GND and VCC key in single ↓ end input) of device, system prompt:
Please?input?pin?names，acconding?to?dev-pin?order?fromsmaller→larger，if?you?enter?a?return?only，end?of?input
And prompting:
4.1 the step: Pleaes input first pin name:
Answer: keys in an actual leg name ↓, change 4.2 and go on foot,
↓ finishing input changeed for the 5th step.
4.2 the step: system prompt: Please input next pin name:
Answer: key in next actual leg name ↓, changeed for 4.2 steps,
↓ finishing input changeed for 5 steps.
5 steps: confirm whether to need to finish entering apparatus leg name.
System shows the 1st～last 1 leg name of having imported ... prompting:
Would?you?end?input?dev-name？(Y？？/No＝0)
Answer: 1 finishes input changeed for the 6th step,
0 changeed for the 4th step restarts input.
6 steps: show the leg name one by one, and require by their I/O characteristic of actual conditions input.
System prompt:
***Let’s?go，please?enter?in-pin?characters****
And prompting:
6.1 the step: xx is in-pin (0-OUT, 1-IN, 2-I/O, 3-O/I, 4-Nonuse)
Answer: 0 representative is the spy that outpin changes the next leg name of 6.1 steps prompting,
1 representative is that inpin changeed for 6.2 steps.
On behalf of elder generation, 2 change 6.1 with 0 step as the pin of out then as in.
On behalf of elder generation, 3 change 6.1 with 0 step as the pin of in then as out.
The no pin of 4 representatives changes 6.1 with 0 step.
Other is got back to 6.1 and goes on foot the selection of pointing out this pin name again.
6.2 the step: xx has fix-value (Yes=1/No=0)
Answer: 0 is represented as the characteristic that variable value changes the next leg name of 6.1 steps prompting,
1 is represented as fixed value changeed for 6.3 steps.
6.3 the step: Please input xx fix-value and reture:
Answer: K/C/P/0/1/2 ... / 9 change the characteristic of 6.1 steps and the next leg name of prompting input.
Wherein: K/C represents clock negative edge or rising edge respectively, and P represents the register preload, and 0/1 represents low/high level, 2 respectively ... 9 represent 7 super level respectively.
(note: this step generally should cannot not selected fixingly three-state control leg, and elects as in the 10th step and do not optimize, so that form correct ternary test patterns).
7 steps: classification shows the characteristic of each leg of input, and puts question to whether will revise these characteristics.System shows:
Now，you?have?xx?inpins，xx?outpins，xx?fix-value-pins，xx?nonfix-value-pins，fix-value-in-pin-names?and?values?are：
Key in: name, value
variable-value-pin-names?are：
Key in: name
out-pin-name?are：
Key in: name
gnd/vcc?is?xx/xxth?pin
And prompting: Will you change characters of them? (Yes=1/No=0)
Answer: 1 changeed for 6 steps, and 0 changeed for 8 steps.
Whether 8 steps: showing row's method of current variable formation and put question to will the row's of modification method.
System shows: You have variable pin queuing:
……
Note：variable?speed?of?them：slower→quicker
Do?you?change?the?queue？(change＝1/No＝0)
Answer: 1 changeed for 9 steps, and 0 changeed for 10 steps.
9 steps: reset variable formation (change the input earlier of slow leg name, key in single ↓ end and reset) system prompt:
Pleaes?enter?slowest?pin?name：(simple?reture，exit?input)
Answer: import the slowest leg name of variation ↓, change 9 steps import next leg name ↓ ... all imported the back up to all leg names and changeed for 8 steps;
Import single ↓ end and reset 8 steps of commentaries on classics.
10 steps: whether inquiry needs to optimize variable formation, answers a digital representing optimized number.
System prompt:
How?many?pins?will?be?optimized？pls?input?digit(0-no?optimizable)：
Answer: 0 ↓ not optimizes 11 steps of commentaries on classics,
The test patterns of the last X of X ↓ one digitized representation element needs to optimize, and changes for 10.1 steps.
10.1 the step: the optimization number of confirming the input of the 10th step:
System prompt:
X?pins?will?be?optimized，，aren’t？(yes＝1/No＝0)
Answer: 1 confirms, changes for 11 steps; 0 will revise, and changes for 10 steps.
11 steps: the status number that the prompting entering apparatus exists.Part sequential circuit or state machine need use this number to improve test patterns and generate, if you are indifferent to this numerical value, can answer numeral 0/1.
System prompt:
How?many?status?are?there?in?the?device？(please?entera?digit?number?of?status，if?you?don’t?know/care?aboutit，enter?digit?1.)
Answer: decimal number ↓, represent the device state number.Changeed for 12 steps.
12 steps: whether prompting exists initialization vector.
System prompt:
Are?there?initialize?vector(Yes＝1/No＝0)
Answer: 1 exists 12.1 steps of commentaries on classics, and 0 does not exist 13 steps of commentaries on classics.
12.1 the step: system prompt: key in the initialization test vector by display mode.
Pleaes?enter?initialize?vector，as?following?format：
[..................]→[……………]；
****please?care?about?the?format！！！****
Answer: press prompting mode key in an initial testing vector ↓, change 12.2 and go on foot.
12.2 the step: system shows whether the initialization vector and the prompting of just having keyed in will be revised.
System prompt:
Your?initialize?vector?is......
Do?you?change?it？(Yes＝1/No＝0)
Answer: 1 revises 12.1 steps of commentaries on classics keys in initialization vector again,
0 does not revise 12.3 steps of commentaries on classics.
12.3 the step: whether inquiry also has next initialization test vector.
System prompt:
Are?there?next?initialize?vector(Yes＝1/No＝0)
Answer: 1 changeed for 12.1 steps, and 0 changeed for 13 steps.
13 steps: editor's local variable file and/or logical description file.
13.1 the step: editor's local variable file.Local variable is meant needs the variable used in logical description.Available mouse moving cursor increases at cursor point, deletes, font change character, after you are satisfied, with ALT ↓, S ↓ saving result, use then ALT ↓, X ↓ withdrawing from edit mode changeed for 14 steps.(system agreement C, c, K, k, P, p, X, x, l, O represent rising edge clock, negative edge, register preload, arbitrary value, high level, low level respectively, can no longer illustrate when the user uses.)
13.2 the step: editorial logic expression formula.
Use-pattern is with 13 steps, but when you will use truth table/constitutional diagram to replace logical expression, first row must use crucial TRUTH_TABLE/STATE_DIAGRAM and accessory constituent thereof.
14 steps: show whether the special variable of usefulness and prompting need to revise the special constant of existing special constant/increase.
System prompt: There are special constant:
Pin?x＝x，......
Will?you?change/add?special?onstants(Yes＝1/No＝0)：
Prompting:
Will?you?use(add)special?constants?in?simulating
(Yes＝1/No＝0)；
Answer: 1 modification/use (increase), changeed for 14.1 steps,
0 does not change/need not (not add), changes for 15 steps.
14.1 the step: prompting:
Please?enter?first?special?constant’s?pin-order
(digit?1，2...)：
Answer: key in the actual sequence number of first special constant, changeed for 14.2 steps.
14.2 the step: prompting:
Pleaes?enter?pinxx’s?special?constant?value(C/K...)：
Answer: key in C/K/P/0/1 ... 9, changeed for 14.3 steps.
14.3 the step: prompting: whether also have special constant to import:
Are?you?contiuning?input?special?constant?order/value？(Yes＝1/No＝0)
Answer: 1 changeed for 14.4 steps, and 0 changeed for 14.5 steps.
14.4 the step: prompting:
Do?you?change?the?special?constant’s?order/value？(change＝1/No＝0)
Answer: 1 changeed for 14.1 steps, and 0 changeed for 15 steps.
15 steps: the actual leg band of the prompting ternary output control leg of input (OC).
Please?enter?OC?pin’s?order：(a?digit，0-there?isn’t?OC)
Answer: decimal number ↓, representing X leg is the OC leg, commentaries on classics 15.1,
0 ↓ no OC leg changes 15.1.
15.1 the step: confirm input just now.System shows:
Here?Xth?is?OC，isn’tit？(Yes＝1/No＝0)
Answer: 1 changeed for 16 steps, and 0 changeed for 15 steps.
16 steps: system prompt three selects one, continues/interrupt/re-enter initialization vector (only to new file).
You?must?be?select：0-continue，1-abort，2-reinputinitalize?vector：
Answer: 0 changeed for 17 steps,
1 stops whole operation changeed for 19 steps,
2 changeed for 12 steps.
17 steps: switch to the S10 system from PC, order is keyed in as is issued orders after system enters the S10 working method automatically:
File?rec↓
page?up
2↓
s.2sc↓
pid’do’↓
’s’↓
Changeed for 18 steps.
18 steps: system prompt:
If?ready：return，to?start?your?testing.
Answer: ↓ system is pointed out again:
A.C?paramter?select：0-25，1-20，2-15，3-10(NS)
Key in 0/1/2/3 ↓ enter test.
After this one of every key entry ↓ test once and show test results.
Key in ALTER/X, Y ↓ fall back on PC working method.Changeed for 19 steps.
19 steps: finish to withdraw from.System shows:
ASICATPG?END
****?Goog-By ****
1.2 directly generate the reciprocal process of test procedure automatically according to the programming file
This section will comprehensively be introduced doing one based on the operating process of the PLD device autotest program generation-ASICTESTT of ABEL source file.ASICTEST can automatically generate the test procedure of its device to the ABEL source file.If there is the PALASM language file to become the ABEL file, use the ASICTEST process then by the TOABEL command conversion.If have the .JED file to convert thereof into the ABEL file, and then use the ASICTEST process by the JEDABEL order.
1.2.1 enter ASICTEST
Activate icon ASICTEST, system just enters the ASICTEST environment automatically, and demonstration topic header and information.
ASICTEST-Automatic?test?program?generate?software
of?based?on?ABEL?source?file
design?by?709?inistitute(WuHan)
Also can directly use the ASICTEST order to enter the ASICTEST environment.
1.2.2 file input
System shows input file topic header:
″Test?generate?by?ABEL?file″。
And prompting all ABEL source files under current medium.Show simultaneously:
Pleas?enter?ABEL?file?name：
XXXXXX.ABL↓
Like this, the ABEL incoming source document that system just receives the user and provided, and test generation automatically according to the file that the user provides.
If File Open lost efficacy, system shows error message, and keys in import file name again.
Annotate: 1. the filename keyed in of user must consistent with certain filename in the middle of the system prompt (promptly existing in current medium), and band .ABL suffix, could correctly open file like this.
2. key in // or dummy file name, system withdraws from the PLDTEST state automatically.
1.2.3 optimize
PLDTEST software can be optimized test vector.
After keying in input ABEL filename and correctly opening file, system's display optimization function topic header:
″Optime?function?select″
This is a selection function, so, point out following information:
Do?you?want?to?optime?test?vectors？Y/N(y/n)
Y/N(y/n)↓
If key in N, then system enters next function.
If key in Y, then key in the leg name that will optimize, PLDTEST can be optimized any one leg of device, and system shows following information:
Enter?optime?test?vector?name?for?i＝1：
XXXXXX↓
Key in after the leg name, reresent the leg name that the next one will be optimized, be called up to keying in leg // till.Optimize mainly is to be used for as the lead leg of importing at the PLD device.Referring to 6.1 joints.
Annotate: the optimization leg name of key entry must be consistent with a certain leg name in the ABEL file, comprise large and small writing, otherwise system can require again you to key in.
1.2.4 state expansion
ASICTEST can carry out the state expansion to test vector, and this is a selection function, if key in Y, so just answers the status number (under the same input stimulus, the accessible status number of state machine) of state machine, if key in N, and the operation below so just carrying out.
1.2.5 initialization vector
PLDTEST software makes the user set initialization vector by the needs of oneself for the user provides the initialization vector function, and this is a selection function, can select also can not select.After finishing optimizational function, system enters function of initializing and selects, demonstration topic head and information:
″Initial?function?select″
Do?you?want?enter?initial?vectors？Y/N(y/n)
Y/N(y/n)↓
If key in N, then do not set initialization vector.
If key in Y, system shows below the input and output vector table so, as: ([CLK, OC, MODE, D1, D2] → [Q1, Q2, Q3, Q4]) and cursor under corresponding vector, beating automatically, the user can be under the vector at cursor place direct characters such as this vectorial value (initialization) 0,1 of key entry, C, K, H, L, X.
Initialization vector can be a delegation, also can be multirow.When keying in delegation's initialization vector, key in CR, key in next line so again.If key in //, then finish the initialization vector input.
After initialization vector was set and to be finished, system tested to initialization vector automatically, and the user can be according to assay, was to confirm the initialization vector imported, still reset initialization vector.
1.2.6 test generates
System generates test vector automatically, and then generates test procedure automatically according to the initialization vector of the ABEL source file, test vector prioritization scheme and the input that provide, and realizes that automatically being loaded into the S-10 system tests.Load 17～19 steps of test operation with 5.1 joints.
1.2.7 explanation about input file
Input file should be an ABEL linguistic source file, and delegation has only a statement.
1.2.8 suggestion
In the leg definition statement row of the ABEL source file of importing, the leg name and the leg band of the first definition of data leg of should trying one's best like this, help guaranteeing the optimization of test vector order.
For example:
A0, A1, A2, A3, B0, B1, B2, B3 PIN 2,3,4,5, and 6,7,8,9; First leg is capable
CLK, OC, CO, I1, I0, CI PIN 1,11,12,13, and 18,19; Second leg is capable
Q3, Q2, Q1, Q0 PIN 14,15,16,17; The 3rd leg is capable
Ai and Bi are the data legs, therefore Ai and Bi will be placed on the front definition of leg table, and then define clock and other control leg.Can guarantee to produce optimization like this and produce stable test vector.
1,3 use gold vessel spare to generate test procedure
Gold vessel spare is inserted emulator, select icon ASICANA, obtain the programming original.Enter ASICTEST then.Other operation is with 5,2 joints.
2 other explanations
2.1 the principle of optimality
The test vector optimizational function that ASICATPG provides is in order to improve the quality of test vector, to reach higher functional test coverage rate, shortening the length of test vector simultaneously again.Usually rule is the type packet optimization according to the ASIC lead leg, as data lead leg group, control lead leg group or the like.Generally speaking, be that all data legs are optimized.
2.2 initialization vector problem
For sequential logical circuit and state machine, must enter known state by guide device, just can effectively test it.Therefore, in the function of initializing of ASICATPG, must key entry can make device enter the initialization vector of known state really.
Claims (4)
1, a kind of automatic test technology of ASIC device comprises: reorganization S10 LSI testing system, PC, emulator, connect with RS232 between S10 LSI testing system and PC, PC and the emulator, it is characterized in that: in PC, use logical description to generate test procedure, or use the design source file to generate test procedure, or use gold vessel spare to generate test procedure, PC and SIO LSI testing system automatically switch, automatically compiling loads test on LSI testing system.
2, the automatic test technology of ASIC device according to claim 1, it is characterized in that: use design source file generation test procedure to be: at first in the programming file interaction input PC in the design source file, mutual simultaneously other formation condition of input, then generate S10 graphics test sign indicating number automatically, generate test procedure automatically by the graphics test sign indicating number.
3, the automatic test technology of ASIC device according to claim 1 is characterized in that: using logical description to generate test procedure is according to logical description; To mutual entering apparatus model, PIN in the PC distribute, logical description, mutual simultaneously other formation condition of input generates SIO graphics test sign indicating number automatically in the PC, generate test procedure automatically by the graphics test sign indicating number.
4, the automatic test technology of ASIC device according to claim 1, it is characterized in that: use gold vessel spare generation test block to be: to utilize gold vessel spare in PC, to exchange the entering apparatus title, exchange simultaneously is other formation condition of input mutually, then generate the graphics test sign indicating number in the PC automatically, generate test procedure automatically by the graphics test sign indicating number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100198390A CN100476447C (en) | 2005-11-18 | 2005-11-18 | Automatic Test Technology of ASIC Devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100198390A CN100476447C (en) | 2005-11-18 | 2005-11-18 | Automatic Test Technology of ASIC Devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1967274A true CN1967274A (en) | 2007-05-23 |
| CN100476447C CN100476447C (en) | 2009-04-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100198390A Expired - Fee Related CN100476447C (en) | 2005-11-18 | 2005-11-18 | Automatic Test Technology of ASIC Devices |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107144779A (en) * | 2017-06-29 | 2017-09-08 | 珠海全志科技股份有限公司 | PMU method of testings, device and system |
| CN108957283A (en) * | 2017-05-19 | 2018-12-07 | 龙芯中科技术有限公司 | Irradiation experiment plate, monitor terminal, asic chip irradiation experiment system |
| CN112684319A (en) * | 2020-12-16 | 2021-04-20 | 海光信息技术股份有限公司 | Chip inspection tracking method and device |
-
2005
- 2005-11-18 CN CNB2005100198390A patent/CN100476447C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108957283A (en) * | 2017-05-19 | 2018-12-07 | 龙芯中科技术有限公司 | Irradiation experiment plate, monitor terminal, asic chip irradiation experiment system |
| CN107144779A (en) * | 2017-06-29 | 2017-09-08 | 珠海全志科技股份有限公司 | PMU method of testings, device and system |
| CN112684319A (en) * | 2020-12-16 | 2021-04-20 | 海光信息技术股份有限公司 | Chip inspection tracking method and device |
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| Publication number | Publication date |
|---|---|
| CN100476447C (en) | 2009-04-08 |
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