CN1959426A - Method for processing vectors tested digitally - Google Patents
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- CN1959426A CN1959426A CN 200510116893 CN200510116893A CN1959426A CN 1959426 A CN1959426 A CN 1959426A CN 200510116893 CN200510116893 CN 200510116893 CN 200510116893 A CN200510116893 A CN 200510116893A CN 1959426 A CN1959426 A CN 1959426A
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- 239000013598 vector Substances 0.000 title claims abstract description 173
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012545 processing Methods 0.000 title claims abstract description 17
- 238000012360 testing method Methods 0.000 claims abstract description 47
- 230000005055 memory storage Effects 0.000 claims description 3
- 230000005284 excitation Effects 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000008676 import Effects 0.000 description 2
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- 238000005096 rolling process Methods 0.000 description 1
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Abstract
A method for processing digital test vector includes comparing test vector with desired vector to generate error vector, counting error vector by counter and sending count-result to upper-level computer for processing error vector, generating address of error vector and using error vector address as address input of error vector storage as well as using error vector column address as data input of error vector storage, informing upper-level computer to fetch and store result by error vector storage then carrying out treatment on error vector.
Description
Technical field
The present invention relates to a kind of method of Vector Processing in the digital test process, this method realizes with hardware circuit, is integrated in the application-specific integrated circuit chip.
Background technology
When carrying out digital test, send excited data or measurement data by digital control plate to driving dash receiver, test result sends it back digital control plate by driving dash receiver, and frequent exchanges data need be carried out in the centre.
At present, the on-line testing instrument often adopts read test result's method in batches, be to deposit a response results on each test node, after once test is finished, the read test result, in test, a global flag is arranged, indicate this whether wrong generation of test, if this test result is all identical with expectation value, then processor is not analyzed test result, if having one different with expectation value, processor analytical test result one by one then, and the position of record place expectation value, the notice host computer shows error message.
As for there being 13 outputs to need certain measured device of test, tester system is divided into 3 groups to these 13 output nodes when carrying out resources allocation, and preceding two groups are 6, and the back is 1 for 1 group.
When specifically testing, for each vector set, tester all is put into all test and excitations of this vector set and expectation value in the storer of each node that drives dash receiver, apply the excitation clock then and measure clock, the test result of 6 test points of this group all is read in the storer of digital control plate, next then vector set is all over up to institute's directed quantity of this measured device.
Whether also have a signal to indicate on the tester has at least one wrong generation in all vector test processes of 6 test points of this group, if any, then processor is handled the result of reading in again, and finds the node and the position of makeing mistakes, as do not have, processor need not be handled the result again.Carry out the test of 6 test points of next group after 6 test points of this group are all over again, so circulation is all finished up to three groups of tests.
There are two kinds of vectors tested digitally treatment technologies at present.
A kind of is that the Z1800 of Teradyne company series of tests instrument proposes.Its processing of measuring vector is carried out in master control board, and excitation vector is placed on and drives on the receiver.When handling, fix owing to drive receiver channel, measuring vector needs batch treatment.Test speed can be slack-off like this, and test is unstable.
Another kind is people's propositions such as Eddie L Williamson JR., and its publication number is US2003/0084388 A1, and the open date is on May 1st, 2003.Its disposal route is that excitation vector and measurement vector all are placed on the driving receiver, store all measurement vector results, take bigger measurement vector memory space like this, therefore the shared memory of several passages, cause the test fixture design complicated, bring inconvenience to the user.
Summary of the invention
The objective of the invention is in order to overcome existing digital test is not the shortcoming that designed in real 1: 1, and test speed is slow in the existing test of solution, the test instability, and test fixture designs problems such as complexity.
In order to realize the foregoing invention purpose, the present invention proposes a kind of new vector test disposal route: excitation vector and test vector all are placed on and drive in the receiver, only store and the processing error vector the corresponding memory of passage.Its implementation is as follows.
A kind of method for processing vectors tested digitally is characterized in that, comprising:
Step 1, host computer operation primary control program, test vector relatively produces error vector with the expectation vector, and then the error vector counter begins counting, and count results notice host computer is handled error vector;
Step 2, employing error vector address generator produce the error vector address;
Step 3, employing error vector address selector are selected the address input of error vector address as the error vector memory, and the error vector column address of error vector column address maker generation is imported as the data of error vector memory simultaneously;
Step 4, error vector memory notice host computer read the storage result, handle error vector.
If test vector does not relatively have error vector to produce with the expectation vector, then host computer continues the operation new procedures.
When the error vector signal with measuring clock as clock signal, and clock is when effective, the error vector address generator loads into the error vector address, the generation error vector address.
Measure clock as error vector column address counter clock, when effective all the time, adopt the error vector column address counter to begin counting, generate vectorial column address.
Under read-write enables control signal, when clock is effective, adopt the error vector memory that the error vector column address is deposited in the error vector address.
When opening error vector output triple gate, the error vector column position of error vector memory storage outputs on the data bus, is read by host computer.
Measure clock and error vector together as error vector number counter clock, when clock was effective, counter began counting, and the result outputs to error vector number output tri-state gate circuit.
When opening error vector number output triple gate, error vector number sum outputs on the data bus, is read by host computer.
Vector processing method proposed by the invention, only need to handle error vector, thereby saved memory space, can realize memory of a passage, really accomplished 1: 1 design in the digital test, it is simple to make digital test handle, and digital test speed is fast, test fixture is simple, the stable testing raising.
Description of drawings
Fig. 1 is the concrete embodiment process flow diagram of the present invention;
Fig. 2 is the concrete embodiment processing logic of a present invention block diagram.
Embodiment
In the concrete embodiment of the present invention, its technical scheme is achieved as follows described.
1) error vector rolling counters forward error vector number.If there is not error vector, then notify host computer not handle.If wrong vector then notifies host computer to handle error vector.
2) the error vector address generator produces the error vector address.
3) the error vector address selector selects common address or error vector address to be the input of error vector memory address.
4) the error vector column address produces the input of error vector memory data.
5) error vector memory result gives host computer and handles.
Host computer operation primary control program, when test vector relatively produced error vector with the expectation vector, then the error vector counter began counting, and count results notice host computer is handled error vector.
When wrong vector produces, the error vector address generator produces the error vector address, the error vector address selector is selected the address input of error vector address as the error vector memory, and the error vector column address of error vector column address maker generation is as the data input of error vector memory simultaneously.Error vector memory notice host computer reads the storage result.If test vector does not relatively have error vector to produce with the expectation vector, then host computer continues the operation new procedures.
Fig. 2 is the concrete embodiment logic diagram of the present invention, and enforcement in this example is described in further detail to technical scheme in conjunction with the accompanying drawings:
(1) error vector address generator circuit 101 functional descriptions: error vector address generator essence is a counter.The error vector signal is with measuring the clock signal of clock as this counter, and when clock was effective, the error vector address generator loaded into the error vector address, the generation error vector address.
(2) error vector address selector circuit 102 functional descriptions: the error vector address selector is a two-way selector switch, selects the error vector address to output in the error vector memory under control signal control and imports as the address.
(3) error vector column address generator circuit 103 functional descriptions: error vector column address maker essence is a counter.Measure clock as error vector column address counter clock, when effective all the time, the error vector column address counter begins counting, generates vectorial column address.Output in the error vector memory and import as data.
(4) error vector memory circuit 104 functional descriptions: enable under the control signal in the read-write of error vector memory, when clock is effective, the error vector column address is deposited in the error vector address, the result outputs to error vector output tri-state gate circuit.
(5) error vector output tri-state gate circuit 105 functional descriptions: when opening this, the error vector column position of error vector memory storage outputs on the data bus, is read by host computer.
(6) error vector number counter circuit 106 functional descriptions: measure clock and error vector together as error vector number counter clock, when clock was effective, counter began counting.The result outputs to error vector number output tri-state gate circuit.
(7) error vector number output tri-state gate circuit 107 functional descriptions: when opening this, error vector number sum outputs on the data bus, is read by host computer.
Claims (8)
1, a kind of method for processing vectors tested digitally is characterized in that, comprising:
Step 1, host computer operation primary control program, test vector relatively produces error vector with the expectation vector, and then the error vector counter begins counting, and count results notice host computer is handled error vector;
Step 2, employing error vector address generator produce the error vector address;
Step 3, employing error vector address selector are selected the address input of error vector address as the error vector memory, and the error vector column address of error vector column address maker generation is imported as the data of error vector memory simultaneously;
Step 4, error vector memory notice host computer read the storage result, handle error vector.
2, method for processing vectors tested digitally as claimed in claim 1 is characterized in that:
If test vector does not relatively have error vector to produce with the expectation vector, then host computer continues the operation new procedures.
3, method for processing vectors tested digitally as claimed in claim 1 is characterized in that:
When the error vector signal with measuring clock as clock signal, and clock is when effective, the error vector address generator loads into the error vector address, the generation error vector address.
4, method for processing vectors tested digitally as claimed in claim 1 is characterized in that:
Measure clock as error vector column address counter clock, when effective all the time, adopt the error vector column address counter to begin counting, generate vectorial column address.
5, method for processing vectors tested digitally as claimed in claim 1 is characterized in that:
Under read-write enables control signal, when clock is effective, adopt the error vector memory that the error vector column address is deposited in the error vector address.
6, method for processing vectors tested digitally as claimed in claim 1 is characterized in that:
When opening error vector output triple gate, the error vector column position of error vector memory storage outputs on the data bus, is read by host computer.
7, method for processing vectors tested digitally as claimed in claim 1 is characterized in that:
Measure clock and error vector together as error vector number counter clock, when clock was effective, counter began counting, and the result outputs to error vector number output tri-state gate circuit.
8, method for processing vectors tested digitally as claimed in claim 1 is characterized in that: when opening error vector number output triple gate, error vector number sum outputs on the data bus, is read by host computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101168937A CN100516913C (en) | 2005-10-31 | 2005-10-31 | Method for processing vectors tested digitally |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101168937A CN100516913C (en) | 2005-10-31 | 2005-10-31 | Method for processing vectors tested digitally |
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| Publication Number | Publication Date |
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| CN1959426A true CN1959426A (en) | 2007-05-09 |
| CN100516913C CN100516913C (en) | 2009-07-22 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101135718B (en) * | 2007-09-10 | 2010-06-02 | 中兴通讯股份有限公司 | Driver circuit |
| CN101458301B (en) * | 2007-12-13 | 2011-11-02 | 上海华虹Nec电子有限公司 | Method for implementing matching test for automatic test equipment |
| CN109581199A (en) * | 2019-01-22 | 2019-04-05 | 上海艾为电子技术股份有限公司 | Digital volume production test machine, pumping signal acquisition methods and testing data comparative approach |
| CN111208407A (en) * | 2018-11-21 | 2020-05-29 | 上海春尚电子科技有限公司 | Auxiliary test system for digital integrated circuit chip |
| CN111337820A (en) * | 2020-04-24 | 2020-06-26 | 江西联智集成电路有限公司 | Digital chip scan chain test method, device, equipment and medium |
-
2005
- 2005-10-31 CN CNB2005101168937A patent/CN100516913C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101135718B (en) * | 2007-09-10 | 2010-06-02 | 中兴通讯股份有限公司 | Driver circuit |
| CN101458301B (en) * | 2007-12-13 | 2011-11-02 | 上海华虹Nec电子有限公司 | Method for implementing matching test for automatic test equipment |
| CN111208407A (en) * | 2018-11-21 | 2020-05-29 | 上海春尚电子科技有限公司 | Auxiliary test system for digital integrated circuit chip |
| CN111208407B (en) * | 2018-11-21 | 2022-05-31 | 上海春尚电子科技有限公司 | Auxiliary test system for digital integrated circuit chip |
| CN109581199A (en) * | 2019-01-22 | 2019-04-05 | 上海艾为电子技术股份有限公司 | Digital volume production test machine, pumping signal acquisition methods and testing data comparative approach |
| CN111337820A (en) * | 2020-04-24 | 2020-06-26 | 江西联智集成电路有限公司 | Digital chip scan chain test method, device, equipment and medium |
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| Publication number | Publication date |
|---|---|
| CN100516913C (en) | 2009-07-22 |
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