CN1943117B - Power-saving multibit delta-sigma converter - Google Patents
Power-saving multibit delta-sigma converter Download PDFInfo
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- CN1943117B CN1943117B CN200580011576.7A CN200580011576A CN1943117B CN 1943117 B CN1943117 B CN 1943117B CN 200580011576 A CN200580011576 A CN 200580011576A CN 1943117 B CN1943117 B CN 1943117B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
- H03M1/182—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the reference levels of the analogue/digital converter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/004—Reconfigurable analogue/digital or digital/analogue converters
- H03M1/007—Reconfigurable analogue/digital or digital/analogue converters among different resolutions
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/32—Delta-sigma modulation with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
- H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/478—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication
- H03M3/488—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication using automatic control
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Abstract
A power-saving multi-bit delta-sigma-converter (1) has an input (2) for analog signal (ZA) and an output for a digital output signal (ZD), a D/A converter (4), a summation device (5) for providing the difference between the input signal and the feedback signal (Z3), a filter (6) for the difference signal (Z1), a clocked quantization device (7) for quantizing the filtered difference signal (Z2) tothe digital output signal (ZD) with bit-width N. The quantization device (7) has less than (2 power N)-1 comparators which compare the filtered signal (Z2) with a reference potential associated with each one of the comparators, and output the result at a decoder.Decoder produce digital output signal coming from comparison result, and update the reference potential according to the comparison result.
Description
Technical field
The present invention relates to energy-conservation many bits δ-∑ transducer, what wherein can particularly point out is to have reduced the number of comparators of digital quantizer.
Background technology
So-called δ-∑ transducer usually is used as analogue-to-digital converters, because they can provide altitude figureization and high s/n ratio.
The δ of a simple so-called bit-∑ transducer can provide the data flow of one one bit according to an analog input signal.If the amplitude of analog input signal increases, logic H level is the predominantly bit in the output of δ-∑ transducer, if this amplitude reduction, then logic L level predominantly bit.For constant input signal, digital output signal fluctuates between H and L level.So, can pass through integration in principle, obtain analog signal from bit stream once more.
Bit δ-∑ transducer like this comprises two data blocks basically: an analog modulator and a digital filter.In this case, modulator is a comparator that is connected with integrator at its upstream substantially.By a differential amplifier, from analog input signal, deduct by a bit number analog-to-digital converter and change the output signal of returning.This signal from differential amplifier is fed to a comparator that is connected with integrator at its upstream.So integrator constantly is reset, and produced a bit data flow.
At input level hour, because the digitlization noise under the bits switch situation is bigger,, therefore, often adopt many bits δ-∑ transducer between H level and L level because digital output signal just fluctuates fully.
Common many bits δ-∑ transducer of understanding according to prior art is in Fig. 1 illustrated.
Many bits δ-∑ transducer MDSW has the input E that is used for inserting analog input signal ZA, and the output A that is used for exporting a N bit width digital output signal ZD.Disposed and had the digital-analog convertor DAW that bit width is N, be used to change feedback signal Z3 from digital output signal ZD.By differential amplifier DV, from analog input signal ZA, deduct feedback signal Z3.Thus obtained differential signal Z1 passes through integrator S integration, and is fed to N digital bit transducer as integrated signal Z2, forms digital output signal from this transducer.
Usually also dispose an offset value analog-to-digital converter KDAW; this transducer is an analog compensation signal ZK1 with digital output signal ZD reverse conversion; the compensation factor that this signal is exaggerated among the device FBE subsequently amplifies; and signal ZK by way of compensation; by summing unit AD, from deducting through the signal Z2 of filtering.If significant time migration often took place between the sample time of the sample time of digital quantizer Q and feedback coefficient analog-to-digital converter DAW, then by this compensating signal ZK, can improve stability and signal to noise ratio.Described time migration is also referred to as excessive loop delay, can cause unstable and bad signal to noise ratio, particularly under high clock frequency.By means of this compensating for path, quality of output signals is improved with same N bit width offset value analog-to-digital converter KDAW.Because offset value analog-to-digital converter KDAW must have the bit width N same with digital quantizer, thereby circuit cost is considerable.
Digital quantizer Q is embodied in quick analogue-to-digital converters usually.The related circuit setting of a specific digital quantizer Q is shown in Fig. 2.
This diagram describes by the example of one three digital bit transducer Q, and this transducer has an input A who is used to receive integrated signal Z2, and an output D who is used to export digital output signal D.7 comparator K1......K7 have been equipped with in addition, each comparator has first an input L1......L7 who receives integrated signal Z2, a second input M1......M7 who is connected with separately reference potential U1......U7, and the output U1......U7 of an output comparative result P1......P7.Comparative result P1......P7 passes to decoder DEK, forms digital output signal ZE.
Reference potential U0......U6 is tap between the resistance R 1......R7 of the resistor chain that connects between last reference potential VREFP and the following reference potential VREFN.Therefore, the comparative result that each comparator presented is not that the H level is exactly the L level.According to the level of integration analog input signal Z2, each comparator forwards a H level or a L level result as a comparison to decoder.
Therefore comparative result is with the thermometer code performance, and decoder form thus suitable, for instance, binary code digital output signal ZD.
The remarkable shortcoming of this digital quantizer Q of prior art is that its current drain is very high.Digital quantizer is exactly significant power consumption device.Increase because the quantity of required comparator is index with the bit width N of digital quantizer Q, therefore, also consume a large amount of power according to the many bits δ-∑ transducer with height ratio extra wide of prior art.
By example as can be known, 15 comparators of digital quantizer needs that are used for 4 bits δ-∑ transducer.In addition, also need 4 same bit width offset value analog-to-digital converters.Therefore, the power consumption device normally of the many bits δ-∑ transducer with height ratio extra wide.
Summary of the invention
Therefore, the quantity that target of the present invention provides energy-conservation many bits δ-∑ transducer, particularly its comparator is few, and the required area of integrated circuit is little.
According to the present invention, energy-conservation many bits δ-∑ transducer of the feature of this target by having claim 1 is realized.In addition, this target requires many bits δ-∑ transducer of 10 feature to realize by having identical right.
Therefore, the many bits δ-∑ transducer that is provided comprises the input and the output that is used for digital output signal that are used for analog input signal, have a N bit width and digital output signal can be converted to the digital-analog convertor of analog feedback signal, a summing unit that is used to form difference between input signal and the feedback signal, one is used for differential signal is carried out filter filtering, and a differential signal that is used to make filtering converts the timing digital switching device of the digital output signal with N bit width to.In this case, digital switching device has Y comparator, and comparator signal each reference potential relevant with each comparator of filtering compares, and each comparator is to comparative result of decoder output, decoder produces digital output signal according to comparative result.In the case, reference potential is followed former comparative result to a certain extent.
In addition, the many bits δ-∑ transducer that is provided comprises the input and the output that is used for digital output signal that are used for analog input signal, have a N bit width and digital output signal can be converted to a digital-analog convertor of analog feedback signal, a summing unit that is used to form difference between input signal and the feedback signal, one is used for differential signal is carried out filter filtering, and a differential signal that is used to make filtering converts the timing digital switching device of the digital output signal with N bit width to.In this case, digital switching device applies a potential shift to filtering signal, and Y comparator arranged, the comparator signal of filtering compares with the described potential shift that is applied to each reference potential relevant with each comparator, each comparator is to comparative result of decoder output, decoder produces digital output signal according to comparative result.And this potential shift is followed former comparative result to a certain extent.
The notion of institute of the present invention foundation is the data by preceding comparative result in a flash, or the data of transducer result's data and consequent digital output signal, reduces the quantity of comparator.Because the analog input signal of filtering of digital switching device has only slow variation with regard to clock frequency, only in a comparator, take place by the variation of the thermometer code of comparator output.Therefore, according to the present invention, as long as make according to the output result comparator with different variations of clock cycle in the past takes place, it is just passable to be limited to the part.Therefore as long as the respective digital in the retening temperature meter code and a few other comparator only.From the clock cycle to the clock cycle, only possess comparative result in the variation of following feature and be only suitably, promptly the switching threshold of corresponding comparator is near the level of filtered analog signals.According to the present invention, also can apply a potential shift, thereby the signal that will apply described potential shift passes to the comparator of digital switching device, the potential level of this signal to filtering signal, according to the present invention, always be retained near the threshold voltage of the comparator that quantity reduces.Owing to lack than the comparator according to the wide digital quantizer of respective N-bit of prior art according to the digital switching device of energy-conservation many bits δ of the present invention-∑ transducer, therefore, energy-conservation many bits δ-the ∑ transducer is very energy-conservation according to of the present invention.In addition, required area is also little a lot of than other common transducer on semiconductor chip.
In a preferred embodiment, summing unit has a differential amplifier, is used for the difference between amplification input signal and the feedback signal, and/or filter, and filter has the integrator of the differential signal that is used to accumulate amplification.
According to the comparator of the digital switching device of many bits δ of the present invention-∑ transducer most preferably less than 2N-1.
In a preferred extension of many bits δ-∑ transducer, digital switching device has an on-off controller, change the reference potential of comparator to a certain extent according to previous comparative result, therefore, if in input signal (ZA), change, then have at least a comparator will change its comparative result.Preferably to install a memory, in order to the buffer-stored digital output signal.If comparator and thermometer code is digital corresponding, and its switching threshold and the level of filtering signal is the most approaching, then this comparator can be localized from the digital output signal of having stored.
On-off controller preferably and the memory binding and according to the output signal of buffer-stored, is switched to comparator with reference potential.
In a preferred embodiment of many bits δ of the present invention-∑ transducer, digital switching device has first, second, third comparator at least, and each comparator all has one first input, one second input, and an output.In this case, the signal of filtering is applied to first input, and first, second, third reference potential puts on second input respectively.The output of each comparator provides a comparative result, and the following selection of reference potential: second reference potential is between the first and the 3rd reference potential, and second reference potential approaches the current potential of filtering signal most.
In an embodiment of the digital switching device that has only three comparators, might be in each situation, adjusting or during the track reference current potential, make second or middle comparator from the clock cycle to its comparative result of clock cyclomorphosis.Then, in three bit thermometer codes, correspond respectively to whole comparative results demonstration raisings of three comparators of filtering analog input signal, or remain unchanged, or show reduction.Decoder can constitute the corresponding digital output signal, perhaps thus according to known former transducer result, constitutes complete thermometer code.The major advantage of this preferred embodiment is to have only three comparators just fully enough, even also is like this under the situation of height ratio extra wide.
In addition, its advantage is equidistantly to select reference potential, and has 2N-1 different reference potential to change.
In another preferred extension of the present invention, digital-analog convertor and digital switching device can be that N and bit width are M=ln (Y+1)/ln (2) operation by bit width, and wherein bit width M is corresponding to the quantity Y of comparator.
Thereby can make many bits δ of the present invention-∑ transducer is to turn round under first mode of operation of M at bit width, and digital switching device plays simple analogue-to-digital converters fast, adopts the scheme of simplifying in other words.In on-state, if particularly because former clock or the transducer cycle also do not draw reliable transformation result, thereby the reference potential of comparator is in initially when unknown, this point is favourable.Just turn round up to many bits δ-∑ transducer under second mode of operation with the reference potential of whole bit width N and tracking.This point has played effect to the stability according to whole many bits δ of the present invention-∑ transducer.
Digital-analog convertor and digital switching device are preferably changed between bit width N and M.In favourable expansion scheme, switching controller preferably has a counting device, is used for according to comparative result, produces a digital average value signal in 2N-Y numerical digit thermometer code.Particularly counting device preferably has a up-down counter.
Up-down counter is represented several times to change simply, all is present in that a part of output signal in the thermometer code all the time, on this signal, increase again with from comparative result, basically with the corresponding differential signal of Y numerical digit thermometer code.This work is preferably finished by decoder, and decoder has summing unit, can be used for according to comparative result and average value signal, forms N bit width output signal.
In a preferred embodiment, switching controller also has a control logic part, the control logic part is according to comparative result, perhaps with comparative result as digital output signal, be converted to Y numeral M bit width thermometer code, perhaps comparative result is combined with average value signal,, be converted to 2N numeral M bit width thermometer code as digital output signal.The thermometer code that has the 2N numeral can transmit on 2N-1 bar data wire.
Control logic partly plays the capture circuit effect, digital switching device is controlled, digital switching device or as the quick analogue-to-digital converters of M bit, perhaps as N bit analogue-to-digital converters, wherein the reference potential of used comparator is followed the tracks of according to the transducer result, perhaps can apply a potential shift to input signal.Its advantage is, only when the stable operating point of the control loop that has found digital switching device, just can follow the tracks of reference potential.
In a further preferred embodiment, switching controller has a reference number analog-to-digital converter, is used for producing drift potential from the digital averaging value signal.Because on 2N-Y-1 bar data wire, average value signal exists as 2N-Y numerical digit thermometer code signal, so the reference number analog-to-digital converter is the device that very simply produces potential shift.
In another preferred extension of many bits δ of the present invention-∑ transducer, digital switching device has an offset value analog-to-digital converter, be used for comparative result is converted to a digital compensating signal at least, also have a summing unit, be used for deducting the analog compensation signal from the differential signal of filtering.
Compensating analog-digital quantizer, for for analog feedback signal, and the excessive loop-delay between the sample time of sample time of timing digital switching device and digital-analog convertor can compensate effectively.
The bit width of compensating analog-digital quantizer is corresponding with the quantity of comparator in the digital switching device, is favourable like this.Therefore, in expansion scheme of the present invention, compared with prior art, can adopt a feedback coefficient analog-to-digital converter, can significantly reduce bit number like this, at first significantly improve the signal quality of output signal thus, next makes many bits δ-∑ transducer become energy-conservation.This is that tracking digital quantizer of the present invention or analogue-to-digital converters only need converter unit seldom because in the feedback coefficient analog-to-digital converter.
In this improved preferred embodiment, returning apparatus an amplifier, be used for amplifying the analog compensation signal with compensation factor.A kind of like this amplifier allows compensation factor is set in the best way, therefore, even under the situation of excessive loop-delay, good especially signal quality or extra high signal to noise ratio can both occur.Thereby also need can be specially adapted to the system of high bandwidth and high clock frequency, for example application in xDSL or UMTS according to many bits δ of the present invention-∑ transducer.
Improvement that the present invention is further favourable and expansion embodiment part and the theme of illustration with reference to the accompanying drawings.
Description of drawings
According to schematic diagram and typical embodiments, the present invention will be described in more detail below.In the drawings:
Fig. 1: the many bits δ-∑ transducer of expression prior art;
Fig. 2: 3 digital bit transducers of expression prior art;
Fig. 3: expression is according to an embodiment of energy-conservation many bits δ of the present invention-∑ transducer;
Fig. 4: expression is according to an embodiment of digital switching device of the present invention;
Fig. 5: expression is according to second embodiment of energy-conservation many bits δ of the present invention-∑ transducer;
Fig. 6: expression is according to a typical embodiments of comparison means of the present invention;
Fig. 7: expression is according to first expansion scheme of energy-conservation many bits δ of the present invention-∑ transducer;
Fig. 8: expression is according to energy-conservation many bits δ of the present invention-∑ transducer distinctive output signal under two mode of operations;
Fig. 9: expression is according to second expansion scheme of energy-conservation many bits δ of the present invention-∑ transducer;
Figure 10: expression is according to the 3rd expansion scheme of energy-conservation many bits δ of the present invention-∑ transducer;
Figure 11: expression is according to the expansion scheme of digital switching device of the present invention.
Same element or function components identical have identical reference symbol in the drawings.
Embodiment
Fig. 3 represents according to energy-conservation many bits δ of the present invention-∑ transducer.
Many bits δ-∑ transducer 1 has an input 2 that is used for inserting analog input signal ZA, and the output 3 that is used for picking out digital output signal ZD.Be equipped with digital-analog convertor 4 in addition, be used for digital output signal ZD is converted to analog feedback signal Z3.The bit width of digital-analog convertor 4 is N.Differential amplifier 5 is used as summing unit, is used for deducting from analog input signal ZA feedback signal Z3, and the difference between analog input signal ZA and the feedback signal Z3 is amplified.The differential signal Z1 of this amplification is by a filter integration, and this filter is specially integrator 6 at this.A timing digital switching device 7 forms digital output signal ZD according to the filtering or the differential signal Z2 of integration.
Digital switching device provides digital output signal, and its bit width is identical with the bit width N that digital-analog convertor 4 is had.
Thermometer code constitutes conventional number format.In this case, 2N state is corresponding to 2N orderly numerical digit, each digit representation logic state 0 or 1.It is corresponding that ten of the quantity of the numeral of setting and digital signal corresponding advanced bit value.Metric 4 is 011 in N=3 bit width binary code, then is mapped as 00001111 in 2N=8 numerical digit thermometer code.Because 0 is represented as 00000000 thermometer code symbol in this case, the required data wire of then each transmission lacks 1 than numeral, i.e. 2N-1 bar data wire.
Fig. 4 represents a preferred embodiment of switch of the present invention and comparison means 8.Switch among the figure and comparison means 8 are digital switching devices that design provides N=3 bit width digital output signal ZD, and this is an example.In the 2N-1 of one 3 bit digital switching device, must keep 7 comparators to use usually in other words.
Switch and comparison means 8 have the output 10 that 9, one of an input that are used to insert integrated signal Z2 is used to pick out digital output signal ZD, are used to receive the control input 11 of one or more control signal SCT.
Further equipment comprises 7 resistance 14-20, and these resistance are connected in series between last reference potential VREFP and following reference potential VREFN.6 reference potential U1, U2, U3, U4, U5, U6 can tell between resistance 14-20.Descend reference potential VREFN also as 0 reference potential U0 in addition.
Equipment comprises y=3 comparator 21,22,23, and each comparator has first input 24,25,26, applies integrated signal Z2 in the above; Each comparator also has second input 27,28,29, and is used to export comparative result V1, V2 separately, the output 30,31,32 of V3.
Comparative result is transferred to decoder, and decoder produces digital output signal ZD according to encoded control signal SCD.Decoding control signal SCD, SCT is the same with control signal, can be provided by control logic part 12.By the switching device 34 of switching signal SCT control, at every turn with reference potential U0, U1, U2, U3, U4, U5, among the U6 one, second input 27,28,29 of receiving comparator 21,22,23.
12 pairs of switching devices 34 of control signal SCT or corresponding control logic part are controlled, its mode is as follows, if from a clock cycle to the next clock cycle, integrated signal Z2 changes, switching point middle or second comparator 22 always approaches most the level of integrated signal Z2.For instance, if during first transducer cycle or clock cycle, the level of integrated signal Z2 is between reference potential U1 and the U2, and the switching threshold of first comparator 21 is at U3, the switching threshold of second comparator 22 is at U2, and the switching threshold of the 3rd comparator is at U1, and then comparative result is V1=L, V2=L, V3=H.If second, afterwards clock cycle, the level of integrated signal Z2 is brought up between U2 and the U3, and threshold voltage unchanged, the comparative result that comparator provides is V1=L, V2=H, V3=H.
The threshold voltage of three comparators 21,22,23 is set to cover the shared part of 3 complete bit width thermometer codes (8 numerical digits, each has H or L), wherein, from H to L, change, from less significant bit to more significant bit.Yet, because former comparative result is considered to the result of buffer-stored, for example, result in the buffer storage shown in Figure 3,3 bit widths of a complete thermometer code, promptly have 8 numerical digits, can be rebuild by encoder 33, encoder also can produce a for example binary accordingly digital output signal ZD.
Reference potential U0-U6 always is switched to second input 27,28,29 of comparator 21,22,23, thereby the switching threshold that makes the switching threshold of first comparator 21 be higher than 22, the second comparators of second comparator is higher than the 3rd comparator 23.
Switching threshold between first and second comparators 21,22, and the difference of switching threshold between second and the 3rd comparator 22 and 23, each is just in time corresponding to a numerical digit in the thermometer code, and this is predetermined by equidistant reference potential U0-U6.
From the clock cycle to the clock cycle, the reference potential of comparator 21,22,23 or switching threshold or upwards or offset downward a numerical digit in the thermometer code, perhaps, if there has been the transformation from H to the L level between comparative result V1 and U2 or V2 and U3, then this reference potential or switching threshold remain unchanged.
34 pairs of reference potentials of switching device by 12 controls of control logic part are followed the tracks of, and control logic part 12 is according to former comparative result or transducer result, follow the tracks of each reference potential, its result makes the switching threshold of y=3 comparator 21,22,23 controlled, make it level near integrated signal Z2, according to the present invention, can save comparator greatly thus.
3 digital bit transducers of a routine as shown in Figure 2, probably should have 7 comparators, and each comparator needs very big area, and consume very big energy.
In this case, " approaching level " is understood that to represent the level of integrated signal Z2, is in the position between the low reference potential of the next one of switching threshold of the next high reference potential of switching threshold of first comparator and the 3rd comparator at least.
In addition, according to the present invention, the digital switching device that is used for many bits δ-∑ transducer has tangible linearity, because digital conversion results only depends on three or comparator still less.In other words, the digital translation indicatrix always has the identical digital translation level of size.Because prior art uses many comparators, this point can not be guaranteed usually, because comparator has fluctuation between mutually.Therefore, reduce the quantity of comparator, also improved the signal quality of many bits δ-∑ transducer.
Fig. 5 represents second embodiment of many bits δ of the present invention-∑ transducer.
Element among many bits δ of the present invention-∑ transducer 107 and Fig. 3 is basic identical, but digital switching device 107 will apply a potential shift PO on the integrated signal Z2 of filtering of importing or amplification.
Switch and control signal SCT are produced by the control logic part 112 that is connected to buffer storage 113.Potential shift PO is provided by control logic part 112, and is added on the filtering signal Z2 by adder 106.
Fig. 6 represents a typical embodiments according to comparison means 108 of the present invention.
110, one of the outputs that switch and comparison means 108 have 109, one of an input that are used for inserting the signal Z4 that has accepted described potential shift to be used for picking out digital output signal ZD are used to receive the control input 111 of one or more control signal SCT.
Equipment comprises three comparators 121,122,123, and each comparator has one first input 124,125,126, and the signal Z4 that has accepted described potential shift is added in first input; Each comparator also has one second input 127,128,129, and is used to export comparative result V101, V102 separately, the output 130,131,132 of V103.
Comparative result is fed to decoder 133, and decoder produces digital output signal ZD according to coding control signal SCD.Decoding control signal SCD is the same with control signal SCT, can be provided by control logic part 112.Second input 127,128,129 that is switched to comparator 121,122,123 is arranged among reference potential U101, U102, the U103 at every turn.Described reference potential is set up in equidistant mode and is proposed at this.
112 couples of potential shift PO of corresponding control logic part control, if its result from a clock cycle to the next clock cycle, filtering signal Z2 changes, then in the middle of or the switching point of second comparator 122 always approach most to have applied the level of the signal Z4 of potential shift PO.Corresponding result V101, V102, V103, by decoding device 133 according to may be on the occasion of also may be the potential shift PO of negative value and buffer-stored in buffer storage before comparative result, handle.This operation is controlled by control signal SCT.
Owing to according to former comparative result, potential shift is followed the tracks of,, compared with prior art, can also be reduced the quantity of comparator according to the present invention.
Fig. 7 represents to have a special digital conversion equipment 207 according to a favourable expansion scheme of many bits δ of the present invention-∑ transducer.
The basic structure of many bits δ-∑ transducer 200 is substantially corresponding to the explanation about Fig. 3 and Fig. 5.But digital switching device 207 and digital-analog convertor 204 can be with different bit width work.
Average value signal X is provided by up-down counter 239, and up-down counter 239 is connected in the output of comparator 221,222,223 by three data wires.In its output 240, up-down counter 239 provides the digital signal of 2N-Y-numerical digit thermometer code on 2N-Y-1 bar data wire.If from a clock cycle to the next clock cycle, comparative result V201, V202, V203 become big, then the up-down counter counting increases; If comparative result reduces, then up-down counter 239 reduces average value signal X a numerical digit of thermometer code.An if selected herein quantity y=3 comparator 221,222,223, then a kind of suitable counting mode is as follows, if from a clock cycle to another clock cycle, the comparative result V202 of intermediate total device 222 changes, then the value of the output 240 of up-down counter 239 remains unchanged; If but on/comparative result V201, the V202 of following comparator 221,223, perhaps the comparator 221,223 with the highest/minimum reference potential work changes, a numerical digit that then should value increase/minimizing thermometer code.The potential window that is covered by three comparators always is in the input signal of digital switching device 207 or near the current potential of the signal Z2 of filtering.
In addition, also be equipped with a control logic part 212, this circuit also is used for estimating comparative result V201, V202, the V203 of Y=3 number position thermometer code.Comparative result also can be understood as differential signal.
In a favourable expansion scheme of many bits δ of the present invention-∑ transducer 200, two kinds of mode of operations can be arranged.Follow the tracks of or the servo-actuated pattern under, the same as described in prior figures 3～Fig. 6 explanation, digital switching device 207 is exported 210 at it N=3 bit width digital output signal with 2N=8 number position thermometer code is provided.Therefore feedback loop output signal ZD is passed to digital-analog convertor 204 usually on 7 data wires.
Second kind of mode of operation---under the quick mode, digital switching device 207 is worked as one the 2 quick analogue-to-digital converters of bit.Bit width M=ln (Y+1)/ln (2), corresponding with the quantity Y=3 of the comparator 221,222,223 that is adopted.This if represent with thermometer code, needs Y=3 bar data wire from the 2 bit width differential signals of comparative result V201, V202, V203.In quick mode, control logic part 212 is opened gate-controlled switch 241, therefore the summing unit 238 of decoder 233 just passes on differential signal, and comparative result V201, the V202 of comparator 221,222,223, V203 just carry out work as quick analogue-to-digital converters in other words.Under quick mode, control logic part 212 is sent signal to digital-analog convertor 204, digital-analog convertor 204 can carry out work as 2 bit converter to a certain extent, only the thermometer code signal of the digital output signal ZD that presents on corresponding Y=3 bar data wire is prescribed and is converted to analog feedback signal.
The quick mode of many bits δ-∑ transducer 200 is at the starting or the connection stage advantageous particularly of many bits δ-∑ transducer.In the servo-actuated pattern during starts, comparator 221,222,223 always forms difference with former conversion value, and this species diversity is ignorant under situation about connecting.Then, counter increases on up-down counter 239 or reduces, so that follow the input signal Z2 of digital switching device 207.The output signal feedback that produces subsequently is sent to digital-analog convertor 204.If under tracing mode, digital quantizer increases output signal ZD, and the reverse Z2 of filtering signal just reduces, thereby may set up stable working point never.
Therefore, control logic part 212 can specifically become a capture circuit, thus make digital switching device 207 at start-up period as a sampler job.In the selected herein typical embodiments of this point, be to realize by the quick analogue-to-digital converters of 2 bits that three comparators 221,222,223 constitute.
The control logic part preferably can make full use of by the given whole modulation ranges of the difference of the highest reference potential and minimum reference potential by control signal SCT changeover switch controller 234 time.Under the situation that is similar to the selected reference potential setting of Fig. 4, select quick mode then, reference potential U0, U3, U6 are switched to comparator 223,222,221.Under this quick stage or quick mode, it is not too accurate that resolution becomes.In case set up stable working point, control logic part 212 just changes the tracing mode that the front had been put forward into, and the result of average value signal X or up-down counter 239 passed to decoder 233, the N bit width output signal ZD of the differential signal that comparative result V201, V202, the V203 of decoder 233 comparators of autotracking in the future is represented, X combines with average value signal.
A type signal distribution map of digital output signal is shown in Fig. 8.
Comparative result V201, V202, the V203 of control logic part 212 comparators 221,222,223 monitor, and when reaching the predetermined value of described differential signal, change the servo-actuated pattern into from quick mode.During quick mode, output signal ZD is two bits through digital translation.If control logic part 212 is found digital quantizer input signals or the zero crossing of filtering signal Z2, then control logic part 212 changes digital switching device 207 into the servo-actuated pattern.Just begin to carry out digital translation during from change with three bits.
Fig. 9 represents the replacement embodiment of a favourable expansion scheme of many bits δ-∑ transducer 300.
Its structure corresponds essentially to the concrete scheme described in Fig. 7.But the configuration of digital switching device 307 changes into filtering signal Z2 is applied a potential shift PO.Equipment comprises the comparison means 308 that has comparator 321,322,323, decoder 333, adder 306.Comparative result V301, V302, the V303 of comparator 321,322,323 is fed to decoder 333, control logic part 312 and a up-down counter 339.
An output 340, up-down counter 339 provides the average value signal X of the thermometer code that has 2N-Y numerical digit on 2N-Y-1 bar data wire.The latter is fed to comparison means 308 by the gate-controlled switch 341 in control input 311, is fed to decoder 333 again from comparison means 308.
Average value signal X is passed to reference number analog-to-digital converter 342 in addition, produces simulation potential shift PO from reference number analog-to-digital converter 342.Described potential shift is by adder 306, is added on the filtering signal Z2.
Control logic part 312 is changed first gate-controlled switch 341 and second gate-controlled switch 243 by switching signal STS, and second gate-controlled switch is connected the downstream of reference number analog-to-digital converter 342.
Under quick mode, control logic part 312 separates potential shift PO by gate-controlled switch 343 from adder 306; And control logic part 312 separates average value signal X by gate-controlled switch 341 from decoder 333.
Therefore, as the front about described in the explanation of Fig. 7, the replacement embodiment of the favourable expansion scheme of many bits δ-∑ transducer 300, under quick mode, carry out work as 2 many bits of bit δ-∑ transducers, and carry out work as 3 bits δ-∑ transducer in that the servo-actuated pattern is next, have only three comparators 321,322,323 under two kinds of patterns, all will keep and can use at every turn.Digital-analog convertor 304 can switch between 2 bits and 3 bit converter patterns by control logic part 312 by control signal SCK equally.
Figure 10 represents another favourable expansion scheme of many bits δ-∑ transducer 400.
Its structure corresponds essentially to the described embodiment of Fig. 5, be equipped with a compensating analog-digital quantizer 404, be used for time migration between sample time of sample time of compensating digits conversion equipment 407 and feedback coefficient analog-to-digital converter 4, described compensating analog-digital quantizer, with forming comparative result V401, V402, the V403 of digital thermometer code signal Z6, be converted to compensating signal ZK1.Timing digital switching device 407 has one and is used for filtered analog signals Z2 or the input 410 of filter difference signal Z2, and the output 411 that is used for digital output signal ZD.
In the described herein embodiment, be equipped with three comparators 21,22,23, the reference link 27,28,29 of comparator is connected to reference signal generating unit 406.Reference signal generating unit 406 provides suitable constant reference potential.Apply the Z5 of filtered analog signals of potential shift PO and compensating signal ZK2, be fed to second input 24,25,26 of comparator 21,22,23.
Three other comparative result of branch V401, V402, V403 form bit and reduce digital signal Z6, and this signal is fed to counting device 439, and is fed to 3 bit width feedback coefficient analog-to-digital converter 404 and summing units 438.
Counting device 439 provides average value signal X known in the foretype embodiment in its output 440, and this signal also is fed to summing unit 438.
Summing unit 438 adds average value signal X and comparative result, the perhaps digital signal Z6 that constitutes by comparative result V401, V402, V403, and form the digital output signal ZD of corresponding many bits δ-∑ transducer 400, and be sent to the output 411 of digital switching device 407.
Average value signal X also is fed to reference number analog-to-digital converter 442, forms simulation migration current potential PO from reference number analog-to-digital converter 442, and described drift potential PO is by adder 409, is applied on the filtered analog signals Z2.
Bit reduces digital signal Z6 and also is fed to offset value analog-to-digital converter 404, and the bit width of offset value analog-to-digital converter 404 conforms to the quantity of comparator 21,22,23.Offset value analog-to-digital converter 404 provides the first compensating signal ZK1, and this signal is exaggerated device 405 and amplifies by compensation or gain coefficient.The first compensating signal ZK1 that has amplified by second adder 408, combines with the filtering signal that is applied in potential shift PO, becomes compensating signal ZK2.The second analog compensation signal ZK2 deducts from the filtering signal that is applied in described potential shift basically and gets.
The path that is made of offset value analog-to-digital converter 404, amplifier 405, second adder 408 etc. compensates the time migration between the sample time of the comparator 21,22,23 of sample time of feedback coefficient analog-to-digital converter 4 and digital switching device 407.Can obtain extra high signal quality thus.
Be equipped with compensating for path according to the present invention in digital switching device 407 inside, highly beneficial in this case, because being illustrated in, this only needs to be equipped with three digital-analog convertor unit in offset value analog-to-digital converter 404.
Obviously, can combine with the typical embodiments among Fig. 3,5,7,9 too according to method of the present invention.Bit reduces the application of offset value analog-to-digital converter 404, only is to represent with example in Figure 10, and the tracking of digital quantizer window is to realize by the potential shift PO that is used for input signal Z2.
Figure 11 illustrates second favourable expansion scheme of digital switching device 507.
Seven resistor 501-506 that are connected in series, 508 resistance chains of forming are connected between reference potential VREFP and the following reference potential VREFN.Similar example as shown in Figure 4, reference potential can be told between resistor 501-506,508, and is fed to gate-controlled switch device 534.Switching device 534 same receptions are simulated filtering signal Z2, as input signal.
First (work) amplifier 515 is connected to line node XP, and second amplifier 516 is connected to mid line circuit node XM, and the 3rd amplifier 517 is connected to down line node XN.Amplifier 515,516,517 can feed back connection respectively by gate-controlled switch 518,519,520.
First, second, third comparator 521,522,523 is connected in the further signal path of amplifier 515,516,517, and each described comparator provides comparative result V501, V502, V503.Three comparative result V501, V502, V503 form digital signal Z6, herein as example, have three bit widths.Digital signal Z6 is fed to codimg logic circuit 524, and codimg logic circuit 524 produces the signal UD that a voltage rises or descends thus, and is fed to counting device 539.If from a clock cycle to the next clock cycle, the digital signal Z6 that exists with the thermometer code form numerical digit that raises, then codimg logic circuit 524 provides a voltage rising signals, if the value of thermometer code indication is lower than former comparative result, then provide a voltage reduction signal.Therefore counting device 539 provides average value signal X.
Described average value signal also is fed to control logic part 512, control logic part 512 is passed through according to mode of the present invention, the reference potential of conversion or follower amplifier-comparator system 515,521,516,522,517,523 reduces the servo-actuated analogue-to-digital converters thereby finished bit at last.An adder 538 that is connected to counting device 539 downstreams with the digital signal Z6 addition of average value signal X and comparator 521,522,523, forms digital output signal ZD, and this signal can be told from exporting 510.
For the conversion of filtered analog signals Z2, for example, in sampling and maintenance stage, in the first half of clock cycle, simulate that filtering signal Z2 is switched to upper and lower line node XP, XN, feedback switch 518,519,520 closures of amplifier 515,516,517.Therefore in all inputs that the signal Z2 that should change or its current potential appear at amplifier 515,516,517.Result as feedback has set up a kind of poised state in each signal path that comprises an amplifier and a comparator.In the input of each comparator, this situation is also referred to as virtual ground.
At translate phase, in other words when each clock cycle later half, simulate filtering signal Z2 and disconnect, go up each reference potential that in the resistance chain of seven resistor 501-508 formations, to tell and connect, to replace above-mentioned signal by capacitor 510,511 from line node XP, XN.At this translate phase, feedback switch 518,519,520 is opened, and amplifier 515,516,517 amplifications appear at line node XP, the XM of each input, the current potential of XN.
Then, the comparator 521,522,523 that is connected the downstream is checked the current potential that occurred before whether the respective input signals of line node XP, XM, XN is greater than or less than, promptly simulate the current potential of filtering signal Z2.A corresponding result can be used as comparison signal V501, V502, V503 then, tells from the output of comparator 521,522,523.Thereby three comparison signals 501,502,503 form one 3 bit thermometer code signal Z6.
In the typical embodiments of digital switching device 507 shown here, middle comparator 522 and amplifier 516 are fed a reference potential that is in translate phase at every turn, and this reference potential is between the reference potential that is fed to top amplifier 515 and following amplifier 517.This operation is herein finished by 513,514 or voltage divider that capacitive character connects.
Controlled feedback switch 518,519,520 can be by a clock signal conversion, and for example, switch is opened in back half clock cycle in preceding half clock cycle closure.
In one of digital switching device 507 favourable expansion scheme, also be provided with a circuit arrangement 504, for the time migration between the sample time of sample time of digital switching device 507 and the digital-analog convertor 4 that uses in the interlock circuit of many bits δ-∑ transducer, circuit arrangement 504 provides compensation.
The circuit arrangement that is used for described offset value analog-to-digital converter 4 has a resistance chain that comprises seven resistor 527-533, and selected herein resistance all is duplicate, and is connected in series between upper and lower compensate for reference current potential VREFP0 and VREFN0.Each compensate for reference current potential can be told between resistor 527-533, and is fed to switching device 526.Another compensate for reference current potential VREF0 also is fed to switching device 526.
Conversion in the control logic part 525 control switch devices 526 makes or descends compensating signal ZK1, ZK2 to correspond respectively to the analogue value of digital thermometer code signal Z6.And, on-off controller 525 transfer switch units 526, make voltage drift often takes place between the current potential of upper and lower compensating signal ZK1, ZK2, this voltage drift is proportional with the drift of the digital switching device that has amplifier and comparator 515,516,517,521,522,523 corresponding reference potential under transition status.Divide other proportionality factor or compensation factor to realize by changing compensate for reference current potential VREFP0, VREFN0.
Therefore, according to the present invention, the comparative result of digital-to-analog reverse conversion or the digital signal Z6 of digital switching device, the same with compensating signal ZK1, ZK2 with compensation factor, be added on the Z2 of filtered analog signals that will change, perhaps from wherein deducting.
Therefore circuit arrangement 504 is 3 feedback coefficient analog-to-digital converter corresponding to having bit width, and by adjustable reference potential VREFP0 and VREFN0, circuit arrangement 504 amplifies in proportion simultaneously or dwindles ZK1, ZK2, or provides a compensation factor to it.
A favourable expansion scheme of digital switching device 507 has particularly advantageously been utilized the following fact: the bit form that subtracts that relies on digital switching device, that is only adopt three comparators 521,522,523 and amplifier 515,516,517, just can only need a device 3 favourable bit width feedback coefficient analog-to-digital converters 504 of cost that get up.
Although according to preferred typical embodiments, describe the present invention in the above, be not limited, can make amendment by different modes.
Therefore, the present invention will be not limited to have three comparators or bit width is the digital switching device of N=3.Otherwise, the present invention is about the switching threshold of following the tracks of single comparator or the notion of reference potential, under opposite extreme situations, also can under the situation of having only an independent comparator, realize, the switching threshold of single comparator can trace into the level of the signal that will compare at every turn, and comparative result was changed in each clock cycle.
Change between quick mode and the servo-actuated pattern also can realize gradually.By keeping many operable at any time reference voltages, plain mode by the compression comparator electrochemical window of working therein, and increase the quantity of the numeral in the thermometer code of average value signal simultaneously, just can increase the bit width of many bits δ of the present invention-∑ transducer, as example, can finish a series of quick mode of operation and many bit modes, or the tracing mode of bit width increase.
According to the converter structure of corresponding many bits δ-∑ transducer, filter can be embodied as continuous or discontinuous mode of time of time.
Certainly, the equipment of the reference potential of thermometer code is not to realize by resistor ladder, but can finish with different modes.And decoder can depart from typical embodiments, and output temperature meter code, to replace binary code.
The invention enables and to realize energy-conservation especially and have high-resolution many bits δ-∑ transducer.The quantity that reduces comparator can be saved the area of semiconductor chip.According to the present invention, increase the bit width of many bits δ-∑ transducer, can not cause that the index of required number of comparators increases.Otherwise the present invention can be applicable to any desired bit width.According to the change between originate mode of the present invention and the tracing mode, represent that many bits δ-∑ transducer always can reach stable working point, and guarantee reliable functioning.
Reference numerals list
The δ of bit more than 1-∑ converter
2 inputs
3 outputs
4 digital-analog convertors
5 summing units
6 wave filters
7 digital switching devices
8 comparisons and switching device
9 inputs
10 outputs
11 control inputs
12 control logic parts
13 buffer storage
The 14-20 resistor
21,22,23 comparators
24,25,26 inputs
27,28,29 inputs
30,31,32 outputs
33 decoders
34 switching devices
35 differential amplifiers
107 digital switching devices
108 comparison means
109 inputs
110 outputs
111 control inputs
112 control logic parts
113 buffer storage
121,122,123 comparators
124,125,126 inputs
127,128,129 inputs
130,131,132 outputs
133 decoders
The δ of bit more than 200-∑ transducer
204 digital-analog convertors
207 digital switching devices
208 comparison means
209 inputs
210 outputs
212 control logic parts
221,222,223 comparators
233 decoders
234 switching devices
238 summing units
239 up-down counter
240 outputs
241 gate-controlled switches
The δ of bit more than 300-∑ transducer
304 digital-analog convertors
306 adders
307 digital switching devices
308 comparison means
309 inputs
310 outputs
311 control inputs
312 control logic parts
321,322,323 comparators
333 decoders
339 up-down counter
340 outputs
341 gate-controlled switches
342 reference number analog-to-digital converters
343 gate-controlled switches
The δ of bit more than 400-∑ transducer
404 feedback coefficient analog-to-digital converters
405 amplifiers
406 reference potential generating units
407 digital switching devices
408 adders
409 adders
410 inputs
411 outputs
438 summing units
439 counting devices
440 outputs
441 reference number analog-to-digital converters
504 feedback coefficient analog-to-digital converters
501-506,508 resistors
507 digital switching devices
509 inputs
510 outputs
511 capacitors
512 control logic parts
513,514 capacitors
515,516,517 amplifiers
518,519,520 gate-controlled switches
521,522,523 comparators
524 codimg logic circuit
525 on-off controllers
526 switching devices
The 527-533 resistor
534,535 outputs
536,537 capacitors
538 summing units
539 counting devices
551 capacitors
A output
The AD adder
The DEK decoder
The DV differential amplifier
The E input
The FBE amplifier
GND ground connection
The K1-K7 comparator
KADW compensating analog-digital quantizer
The L1-L7 input
The M1-M7 input
Many bits of MDSW δ-∑ transducer
O1-O7 output
The P1-P7 comparative result
The Q digital quantizer
The R1-R7 resistor
The S adder
The SCD coding control signal
The SCK switching signal
The SCS control signal
The SCT control signal
The U0-U6 reference potential
The U101-U103 reference potential
V1, V2, V3 comparative result
V201, V202, V203 comparative result
V301, V302, V303 comparative result
V401, V402, V403 comparative result
V501, V502, V503 comparative result
The VREFP reference potential
The VREFN reference potential
VREFN0 compensate for reference current potential
VREF0 compensate for reference current potential
VREFP0 compensate for reference current potential
UD voltage rising/dropping signal
The PO potential shift
The X average value signal
XN, XM, XP line node
The Z1 differential signal
Z2 is filtering signal
The Z3 feedback signal
The signal that Z4 acceptance applies
Z6 digital thermometer code signal
The ZA analog input signal
The ZD digital output signal
ZK, ZK1, ZK2 compensating signal
Claims (22)
1. energy-conservation many bits δ-∑ transducer (1) comprises:
(a) one is used for the input (2) of analog input signal (ZA) and the output (3) that one is used for digital output signal (ZD);
(b) digital-analog convertor (4) that has the N bit width and be used for digital output signal (ZD) is converted to analog feedback signal (Z3);
(c) be used for forming the summing unit (5) of difference between input signal (ZA) and the feedback signal (Z3);
(d) be used for differential signal (Z1) is carried out filter filtering (6);
(e) be used for filter difference signal (Z2) is carried out digital translation, have the timing digital switching device (7) of the digital output signal (ZD) of N bit width with formation;
Digital switching device (7) has and is less than 2
N-1 comparator (21,22,23), described comparator each reference potential under filtering signal (Z2) and the respective comparator (21,22,23) (U0 ... U6) compare, each comparator is to decoder (a 33) output comparative result (V1, V2, V3), decoder produces digital output signal (ZD) by comparative result (V1, V2, V3), and according to former comparative result to reference potential (U0 ... U6) follow the tracks of.
2. many bits of claim 1 δ-∑ transducer (1) is characterized in that: summing unit (5) has a differential amplifier (35) that is used for difference between amplification input signal (ZA) and the feedback signal (Z3).
3. many bits of claim 2 δ-∑ transducer (1) is characterized in that: filter (6) has one and is used for the integration integrator of amplified difference signal (Z1).
4. many bits of one of claim 1-3 δ-∑ transducer (1), it is characterized in that: digital switching device (7) has on-off controller (8,12), described on-off controller (8,12) is according to former comparative result, with reference potential (U0 ... U6) be switched to comparator (21,22,23), thereby, if input signal (ZA) changes, then have at least a comparator (21,22,23) to change its comparative result.
5. many bits of one of claim 1-3 δ-∑ transducer (1) is characterized in that: be provided with a memory (13) that is used for buffer-stored digital output signal (ZD).
6. many bits of one of claim 1-3 δ-∑ transducer (1), it is characterized in that: on-off controller (8,12) is connected to memory (13), and according to the output signal (ZD) of buffer-stored, with reference potential (U0 ... U6) be switched to comparator (21,22,23).
7. many bits of one of claim 1-3 δ-∑ transducer (1), it is characterized in that: digital switching device (7) have at least one first, second, the 3rd comparator (21,22,23), each comparator has first and second inputs (24-29) and an output (30,31,32), filtering signal (Z2) is applied to first input (24,25,26), these outputs (30,31,32) provide a comparative result (V1 respectively, V2, V3), and first, second and the 3rd reference potential (U0, ... U6) be switched to second input (27,28,29), second reference potential is between the first and the 3rd reference potential, and approaches the current potential of filtering signal (Z2) most.
8. many bits of one of claim 1-3 δ-∑ transducer (1) is characterized in that: reference potential (U0 ... be equidistant U6).
9. many bits of one of claim 1-3 δ-∑ transducer (1) is characterized in that: 2
N-1 difference reference potential (U0 ... U6) can change.
10. energy-conservation many bits δ-∑ transducer (100) comprises:
(a) one is used for the input (2) of analog input signal (ZA) and the output (3) that one is used for digital output signal (ZD);
(b) to have bit width be N and be used for digital output signal (ZD) is converted to the digital-analog convertor (4) of analog feedback signal (Z3);
(c) be used for forming the summing unit (5) of difference between input signal (ZA) and the feedback signal (Z3);
(d) be used for differential signal (Z1) is carried out filter filtering (6);
(e) be used for filter difference signal (Z2) is carried out digital translation, have the timing digital switching device (7) of the digital output signal (ZD) of N bit width with formation;
Digital switching device (107) applies potential shift (PO) to filtering signal, and has and be less than 2
N-1 comparator, each reference potential under the filtering signal (Z4) that comparator will apply described potential shift and the corresponding comparator (21,22,23) (U0 ... U6) compare, these comparators are respectively to decoder (a 33) output comparative result (V1, V2, V3), decoder produces digital output signal (ZD) by comparative result, and, reference potential is followed the tracks of according to former comparative result.
11. many bits of claim 10 δ-∑ transducer (100,300), it is characterized in that: be provided with on-off controller (108,112,113), on-off controller is connected with the output (130,131,132) of comparator (121,122,123), and regulates potential shift (PO) according to comparative result (V301, V302, V303).
12. many bits of one of claim 10-11 δ-∑ transducer (200,300) is characterized in that: digital-analog convertor (204,304) and digital switching device (207,307) can be that bit width M=In (the Y+1)/In (2) of Y comparator (221,222,223,321,322,323) carries out work by the N bit width with corresponding to quantity.
13. many bits of claim 12 δ-∑ transducer (200,300) is characterized in that: digital-analog convertor (204,304) and digital switching device (207,307) can switch between two kinds of bit width N and M.
14. many bits of one of claim 10-11 δ-∑ transducer (200,300) is characterized in that: on-off controller (208,212,239,308,312,339) has one and is used for producing 2 according to comparative result (V201, V202, V203, V301, V302, V303)
NThe counting device (239,339) of the digital averaging value signal (X) of-Y-numerical digit thermometer code.
15. many bits of claim 14 δ-∑ transducer (200,300) is characterized in that: counting device (239,339) has up-down counter.
16. many bits of one of claim 10-11 δ-∑ transducer (200,300), it is characterized in that: decoder (33,133) has summing unit (238,338), be used for forming N bit width output signal (ZD) by comparative result (V201, V202, V203, V301, V302, V303) is combined with average value signal (X).
17. many bits of one of claim 10-11 δ-∑ transducer (200,300), it is characterized in that: on-off controller (208,212,239,308,312,339) has a control logic part (212,312), this control logic part (212,312) according to comparative result (V201, V202, V203, V301, V302, V303), with comparative result (V201, V202, V203, V301, V302, V303) be converted to Y numerical digit, M bit width thermometer code is as digital output signal, perhaps with comparative result (V201, V202, V203, V301, V302, V303) combine with average value signal (X), as 2
NDigital output signal (ZD) individual numerical digit, N bit width thermometer code.
18. many bits of one of claim 11 δ-∑ transducer (300), it is characterized in that: on-off controller (308,312,339,342) has a reference number analog-to-digital converter (342), is used for producing drift potential (PO) from digital averaging value signal (X).
19. many bits of one of claim 10-11 δ-∑ transducer (400,500) is characterized in that: digital switching device (407,507)
-have a compensating analog-digital quantizer (404,504), be used for comparative result (V401, V402, V403) is converted at least one analog compensation signal (ZK, ZK1, ZK2);
-have a summing unit (408, XP, XN), be used for from the differential signal (Z2) of filtering, deducting analog compensation signal (ZK, ZK1, ZK2).
20. many bits of claim 19 δ-∑ transducer (400,500) is characterized in that: the bit width of compensating analog-digital quantizer (404,504) is corresponding to the quantity of comparator (21,22,23,521,522,523).
21. many bits of claim 19 δ-∑ transducer (400) is characterized in that: be provided with an amplifier (405), be used for analog compensation signal (ZK) being amplified with compensation factor.
22. many bits of claim 20 δ-∑ transducer (400) is characterized in that: be provided with an amplifier (405), be used for analog compensation signal (ZK) being amplified with compensation factor.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102004009609.0 | 2004-02-27 | ||
| DE102004009609 | 2004-02-27 | ||
| DE102004030812A DE102004030812B4 (en) | 2004-02-27 | 2004-06-25 | Power-saving multi-bit delta-sigma converter esp. for high-bandwidth and very high clock-rate systems, uses clocked quantization device for quantizing filtered difference signal |
| DE102004030812.8 | 2004-06-25 | ||
| PCT/EP2005/001165 WO2005083888A1 (en) | 2004-02-27 | 2005-02-04 | Power-saving multibit delta-sigma converter |
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| Publication Number | Publication Date |
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| CN1943117A CN1943117A (en) | 2007-04-04 |
| CN1943117B true CN1943117B (en) | 2010-11-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200580011576.7A Expired - Fee Related CN1943117B (en) | 2004-02-27 | 2005-02-04 | Power-saving multibit delta-sigma converter |
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| CN (1) | CN1943117B (en) |
| DE (1) | DE102004030812B4 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103248366A (en) * | 2013-05-04 | 2013-08-14 | 徐州柏瑞高新技术科技有限公司 | Leakage-type difference accumulation analog digital modulation converter |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005051822A1 (en) | 2005-10-28 | 2007-05-03 | Infineon Technologies Ag | Circuit arrangement e.g. sigma-delta-transducer, starting circuit, has absorbing device absorbing input signal for circuit arrangement over predetermined period during starting phase of circuit arrangement |
| WO2007107188A1 (en) * | 2006-03-23 | 2007-09-27 | Freescale Semiconductor, Inc. | Electronic device and integrated circuit comprising a delta-sigma converter and method therefor |
| FR2905008A1 (en) * | 2006-08-18 | 2008-02-22 | Stmicroelectronics Maroc | TEMPERATURE SENSOR PROVIDING A TEMPERATURE SIGNAL IN DIGITAL FORM |
| EP3143697B1 (en) * | 2014-05-15 | 2021-09-08 | Elmos Semiconductor SE | Fast reduced-current digitization, conditioning and filtering of analogue signals from a sensor or detector |
| CN109495112A (en) * | 2017-09-11 | 2019-03-19 | 联发科技股份有限公司 | Analog-to-digital conversion method and delta-sigma modulator |
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|---|---|---|---|---|
| US6346898B1 (en) * | 2000-08-07 | 2002-02-12 | Audio Logic, Inc. | Multilevel analog to digital data converter having dynamic element matching in a reference data path |
| US6642873B1 (en) * | 2002-06-03 | 2003-11-04 | Wensheng Vincent Kuang | Multi-level D/A converter incorporated with multi-level quantizer in multi-bit sigma-delta A/D converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3147409A1 (en) * | 1981-11-30 | 1983-06-01 | Siemens AG, 1000 Berlin und 8000 München | METHOD AND ARRANGEMENT FOR A / D CONVERSION |
| US5257026A (en) * | 1992-04-17 | 1993-10-26 | Crystal Semiconductor, Inc. | Method and apparatus for calibrating a multi-bit delta-sigma modular |
| US5528239A (en) * | 1992-04-17 | 1996-06-18 | Crystal Semiconductor Corporation | Low noise transmission of output data from a delta-sigma modulator |
| US5451949A (en) * | 1993-02-16 | 1995-09-19 | Dolby Laboratories Licensing Corporation | One-bit analog-to-digital converters and digital-to-analog converters using an adaptive filter having two regimes of operation |
| US5621408A (en) * | 1995-02-24 | 1997-04-15 | Lecroy Corporation | Delta sigma analog-to-digital converter with temporally interleaved architecture |
-
2004
- 2004-06-25 DE DE102004030812A patent/DE102004030812B4/en not_active Expired - Fee Related
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2005
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6346898B1 (en) * | 2000-08-07 | 2002-02-12 | Audio Logic, Inc. | Multilevel analog to digital data converter having dynamic element matching in a reference data path |
| US6642873B1 (en) * | 2002-06-03 | 2003-11-04 | Wensheng Vincent Kuang | Multi-level D/A converter incorporated with multi-level quantizer in multi-bit sigma-delta A/D converter |
Non-Patent Citations (1)
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| 全文. |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103248366A (en) * | 2013-05-04 | 2013-08-14 | 徐州柏瑞高新技术科技有限公司 | Leakage-type difference accumulation analog digital modulation converter |
| CN103248366B (en) * | 2013-05-04 | 2016-01-13 | 徐州柏瑞高新技术科技有限公司 | A kind of Leakage-type difference accumulation analog digital modulation converter |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102004030812A1 (en) | 2005-09-29 |
| DE102004030812B4 (en) | 2006-01-05 |
| CN1943117A (en) | 2007-04-04 |
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