CN1936502A - Optical fiber gyro front-set amplification and modification output circuit with signal differential amplification - Google Patents

Abstract

The invention discloses a fiber optic gyroscope preamplification and modulation output circuit with signal differential amplification. A signal processor; it is made up of a differential amplifier, an operational amplifier and a 12-bit parallel AD converter; the modulation output circuit receives the digital modulation information output by the digital signal processor, and amplifies it and outputs it to the waveguide modulator; its It consists of 16-bit parallel DA converter, 10-bit serial DA converter, reference voltage source, differential amplifier and operational amplifier. The step wave voltage output by the modulation output circuit of the present invention ranges from 0V to ±4V. Unique double differential current-voltage conversion circuit design. The differential current signal output by the DA is directly converted into a differential output voltage signal without other intermediate links, which saves components, expands the dynamic range, and reduces the introduction of noise.

Description

Fiber optic gyroscope preamplification and modulation output circuit with signal differential amplification

technical field

The present invention relates to a preamplification and driving circuit, more particularly, to a fiber optic gyroscope preamplifying and modulating driving circuit with signal differential transmission and amplification capabilities.

Background technique

Most of the existing preamplifier circuits for fiber optic gyroscopes adopt the form of single-ended amplification, using one or several stages of operational amplifiers to perform single-ended amplification on the output signal of the PIN and then transmit it to the AD converter, convert it into a digital signal, and pass the digital signal After processing, the modulated signal is converted into an analog staircase wave signal by a DA converter, which is converted into a differential signal by a multi-stage operational amplifier and output to the modulator. This kind of circuit uses many devices, the circuit is complex, the power consumption is large, and the amplification and transmission of analog signals pass through many devices, which is easy to introduce noise; and because most of them use single-ended amplification, the amplification factor needs to be Compared with the differential amplification, it is doubled, and the performance of the existing AD converter and DA converter is not fully utilized, and the common film noise is relatively large.

Using this kind of preamplification and modulation drive circuit makes the fiber optic gyroscope have a larger volume and power consumption, and uses more components; because the noise of the analog circuit part is relatively large, the common film noise at the input end of the AD converter has not been effectively suppressed. More digital filters are needed in the signal processing process, which increases the difficulty of digital signal processing. Since the output of the modulated step wave uses a single-ended mode, the amplification capability of the analog circuit is limited, which increases the burden on the drive amplifier circuit, and easily causes the gyro output step wave to be offset.

Contents of the invention

The object of the present invention is to provide a fiber optic gyroscope preamplification and modulation drive circuit with signal differential transmission and amplification capabilities, which belongs to the fiber optic gyroscope signal processing circuit. The output signal of the PIN in the fiber optic gyroscope is subjected to a first-stage differential amplification and a DC blocking filter. Digital signal processing is carried out after the AD converter, and the modulated signal is converted into an analog staircase wave signal by the DA converter, which is converted into a differential staircase wave signal by a first-stage differential amplifier and output to the modulator.

The present invention is a fiber optic gyroscope preamplification and modulation output circuit with signal differential amplification. The preamplification circuit receives the light intensity voltage information output by the photodetector, amplifies it, and outputs it to a digital signal after filtering. A processor; it is made up of a differential amplifier, an operational amplifier and a 12-bit parallel AD converter; the modulation output circuit receives the digital modulation information output by the digital signal processor, and amplifies it and outputs it to the waveguide modulator; it is composed of 16-bit parallel DA converter, 10-bit serial DA converter, reference voltage source, differential amplifier and operational amplifier.

In the preamplification circuit of the detection circuit of the fiber optic gyroscope, the photodetector outputs the PIN_OUTPUT signal to the high-pass DC blocking filter circuit. After superimposing the DC boost voltage generated by the AD converter, the differential amplifier performs differential amplification. The output signal is low-pass filtered and then transmitted to the AD converter for analog-to-digital conversion to generate a digital signal output. At the same time, the PIN_OUTPUT signal is amplified by the PIN (photodetector) output voltage detection amplifier circuit after being low-pass filtered and superimposed to raise the level, and then output to the optical power detection circuit.

In the modulation output circuit of the detection circuit of the fiber optic gyroscope, the parallel DA converter performs DA conversion on the received digital signal output of the fiber optic gyroscope to become a differential output current signal. The amplifying circuit performs differential amplification, and the output signal of the amplifier is low-pass filtered by the differential low-pass filter circuit to form a fiber optic gyro modulation signal output; the reference voltage generation circuit provides reference voltage to the 16-bit parallel DA converter, including reference voltage source, 10-bit Serial DA converter and drive amplifier circuit. The 10-bit serial DA converter receives the digital reference voltage signal provided by the digital signal input of the fiber optic gyroscope, generates a reference voltage according to the output level of the reference voltage source, and outputs it to the reference voltage input terminal of the parallel DA converter after driving the amplifying circuit.

The advantages of the pre-amplification and modulation driving circuit of the present invention are: (1) The PIN output signal is directly converted into a differential signal input to the AD converter, which greatly reduces the common film noise, reduces power consumption and the number of devices. (2) The voltage range of the output ladder wave is from 0V to ±4V, and the output adjustment range is large. (3) Unique double differential current-voltage conversion circuit design. The differential current signal output by the DA is directly converted into a differential output voltage signal without other intermediate links, which saves components, expands the dynamic range, and reduces the introduction of noise. (4) It has a PIN output signal detection circuit, which can detect the state of the gyro optical path, and is convenient for compensation control of the gyro optical path device.

Description of drawings

Figure 1 is a schematic diagram of the detection circuit in the fiber optic gyroscope.

Fig. 2 is a structural block diagram of the preamplifier circuit in the present invention.

Fig. 3 is a structural block diagram of the modulation output circuit in the present invention.

FIG. 4A is a schematic circuit diagram of the preamplifier circuit in the present invention.

FIG. 4B is a schematic circuit diagram of the modulation output circuit in the present invention.

Detailed ways

The present invention will be further described in detail with reference to the accompanying drawings and embodiments.

The invention is a fiber optic gyroscope pre-amplification and modulation output circuit with signal differential amplification, which belongs to the detection circuit part of the fiber optic gyroscope. The detection circuit generally includes a preamplifier circuit, a digital signal processor, an optical power detection circuit, and a modulation output circuit (see Figure 1). The preamplifier circuit receives the light intensity and voltage information output by the photodetector, and performs After amplification and filtering, the output is sent to the digital signal processor; the modulation output circuit receives the digital modulation information output by the digital signal processor, amplifies it and outputs it to the waveguide modulator. The optical power detection circuit realizes the monitoring of the performance of the optical path.

Please refer to Fig. 2, the preamplifier circuit in the present invention is a preamplifier circuit for a fiber optic gyro with signal differential amplification and transmission capabilities, and the circuit also has the ability to monitor PIN output signals. The pre-amplification part in the present invention is composed of a differential amplifier, an operational amplifier and a 12-bit parallel AD converter. The photodetector outputs the PIN_OUTPUT signal to the high-pass DC blocking filter circuit. After superimposing the DC boost voltage generated by the AD converter, the differential amplifier performs differential amplification. The output signal of the differential amplification is low-pass filtered and then transmitted to the AD converter for further processing. Analog-to-digital conversion to generate a digital signal output. At the same time, the PIN_OUTPUT signal is amplified by the PIN (photodetector) output voltage detection amplifier circuit after being low-pass filtered and superimposed to raise the level, and then output to the optical power detection circuit.

Please refer to shown in Fig. 3, the modulating output circuit in the present invention is a kind of optical fiber gyroscope with signal overall differential current-voltage conversion and amplifying ability to drive amplifying circuit with ladder wave, by 16 parallel DA converters, 10 serial DA Converter, reference voltage source, differential amplifier and operational amplifier. The parallel DA converter performs DA conversion on the received digital signal output of the fiber optic gyroscope, and turns it into a differential output current signal. The fiber-optic gyroscope modulation signal output is formed after low-pass filtering by the pass filter circuit; the reference voltage generation circuit provides the reference voltage to the 16-bit parallel DA converter, including the reference voltage source, 10-bit serial DA converter and drive amplifier circuit. The 10-bit serial DA converter receives the digital reference voltage signal provided by the digital signal input of the fiber optic gyroscope, generates a reference voltage according to the output level of the reference voltage source, and outputs it to the reference voltage input terminal of the parallel DA converter after driving the amplifying circuit.

Please refer to Fig. 4A, the connection of each terminal of the preamplifier circuit in the present invention is as follows: the PIN output signal PIN_OUTPUT of the fiber optic gyroscope is connected to the high-pass filter capacitor C1, after the high-pass filter, the signal is transmitted to the differential amplifier U1 through the resistor R2 The 8-terminal of the differential amplifier U1; the elevated level XADVREF signal generated by the AD converter U2 is directly connected to the 2-terminal of the differential amplifier U1, and the XADVREF signal is connected to the 1-terminal of the differential amplifier U1 after passing through the resistor R7. Filter capacitor C7; resistor R3 and capacitor C9 are connected in parallel between terminal 8 and terminal 5 of differential amplifier U1, resistor R10 and capacitor C10 are connected in parallel between terminal 1 and terminal 4 of differential amplifier U1; terminal 3 of differential amplifier U1 is connected to + 5V power supply level, a filter capacitor C11 is connected between the +5V power supply level and the ground, the 6-terminal of the differential amplifier U1 is connected to the -5V power supply level, and a filter capacitor C12 is connected between the -5V power supply level and the ground; the differential amplifier U1 Resistor R5 is directly connected between terminal 5 and terminal 9 of the AD converter U2, and a filter capacitor C2 is connected between terminal 9 of the AD converter U2 and ground, and terminal 4 of U1 is directly connected with terminal 10 of the AD converter with a resistor R13. At the same time, a filter capacitor C14 is connected between terminal 10 of the AD converter U2 and the ground; terminal 2 of U2 is connected to +3.3V, terminal 3 is grounded, terminal 4 outputs an elevated level XADVREF signal, and terminal 5 is connected to the ground through capacitor C20. Terminals are connected to ground through capacitor C19, capacitors C16 and C17 are connected in parallel between terminals 5 and 6, terminals 7 and 12 are connected to +3.3V, terminals 8, 11 and 14 are grounded, terminal 13 is connected to the input clock signal XAD, Terminal 23 is grounded, terminal 24 is connected to +3.3V, terminals 24 and 23 are connected in parallel with capacitors C21 and C24, terminals 15, 16, 17, 18, 19, 20, 21, 22, Terminals 25, 26, 27 and 28 are respectively connected to output signals XADDT0-XADDT11. There are resistors R4 and R8 in series between the PIN output signal PIN_OUTPUT of the fiber optic gyroscope and the 2 terminals of the operational amplifier U3, a filter capacitor C25 is connected between R4, R8 and the ground, and a resistor R9 is connected in parallel between the 2 terminals and 1 terminal of U3 And capacitor C26, resistor R6 is connected between terminal 3 of U3 and the external signal XGK, and capacitor C8 is connected between terminal 3 of U3 and ground; terminal 8 of U3 is connected to +5V power supply level, +5V power supply level The filter capacitor C18 is connected between the ground and the ground, the 4 terminals of U3 are connected to the -5V power supply level, and the filter capacitor C13 is connected between the -5V power supply level and the ground; the 1 terminal of U3 is connected to the output signal GKA_OUT through the resistor R14, and the output signal GKA_OUT Connect filter capacitor C22 with ground.

See also shown in Fig. 4B, the connection of each terminal in the modulation output circuit among the present invention is: digital signal XDADT15～XDADT0 is input from 27 terminals, 28 terminals and 1 terminal～14 terminal of 16-bit parallel DA converter U4, clock signal XDA is input from terminal 26 of U4, terminal 25 of U4 is connected to +5V power supply voltage, capacitors C33 and C40 are connected in parallel between the +5V power supply voltage and ground, terminal 24 of U4 is grounded, terminal 23 is connected to -5V power supply voltage, and -5V power supply Capacitors C32 and C39 are connected in parallel between the voltage and ground, terminal 22 of U4 is connected to the -5V power supply voltage by capacitor C31, terminal 21 of U4 is connected to the -5V power supply voltage by capacitor C38, terminal 20 of U4 is connected to 8 of the differential amplifier U5 Terminal 20 of U4 is directly connected to the ground with resistor R22, terminal 19 of U4 is connected to terminal 1 of the differential amplifier U5, terminal 19 of U4 is indirectly connected to the ground with resistor R21, terminals 18 and 17 of U4 are grounded, and terminal 16 of U4 is connected to the ground. Terminal 1 is connected to reference voltage signal XADVREF through resistor R26, and capacitors C35 and C36 are connected in parallel between reference voltage XADVREF and ground, and terminal 15 of U4 is connected to ground through capacitor C37. Terminal 2 of differential amplifier U5 is grounded, resistor R41 and capacitor C34 are connected in parallel between terminal 8 and terminal 5, resistor R42 and capacitor C41 are connected in parallel between terminal 1 and terminal 4; terminal 3 of U5 is connected to +5V power supply level, + The filter capacitor C42 is connected between the 5V power supply level and the ground, the 6-terminal of U5 is connected to the -5V power supply level, and the filter capacitor C43 is connected between the -5V power supply level and the ground; the 5-terminal of U5 is connected to the output terminal XJTB1 through a resistor R45 A filter capacitor C51 is connected between the output terminal XJTB1 and the ground, terminal 4 of U5 is connected to the output terminal XJTB2 through a resistor R44, and a filter capacitor C52 is connected between the output terminal XJTB2 and the ground. Terminal 1 and terminal 2 of the reference voltage source JP1 are connected to +5V power supply level, terminal 5 is grounded, a filter capacitor C44 is connected between the +5V power supply level and the ground, terminal 3 and terminal 4 of JP1 are connected to the serial DA converter U6 Terminal 7 and terminal 8, filter capacitor C47 is connected between terminal 7 and terminal 8 of U6 and the ground, terminal 1 of U6 is connected to input digital control signal XDONE, terminal 2 of U6 is connected to input digital control signal XLDDA, terminal 3 of U6 and terminal 10 The terminal is connected with +5V power supply level, the 15 terminal of U6 is connected with the input digital control signal XLDREG, the 14 terminal of U6 is connected with the input clock signal XLDCLK, the 13 terminal of U6 is connected with the input digital control signal XSDI, the 12 terminal and 9 terminal of U6 are grounded, and the U6 terminal 13 is connected with the input digital control signal XSDI. Terminal 4 of U7 is connected to terminal 3 of the operational amplifier U7 through resistor R23, a filter capacitor C48 is connected between terminal 3 of U7 and the ground, a resistor R25 is connected between terminal 2 of U7 and the ground, and terminal 2 and terminal 1 of U7 are connected in parallel There are resistor R24 and capacitor C49, 8 terminals of U7 are connected to +5V power supply level, and filter capacitor C53 is connected between +5V power supply level and ground, 4 terminals of U7 are connected to -5V power supply level, and -5V power supply level is connected to ground A filter capacitor C50 is connected between them; terminal 1 of U7 outputs the reference voltage signal XADVREF to the resistor R26.

In the pre-amplification part in the present invention, the formula for calculating the output voltage of the differential operational amplifier is as follows:

$\left\{\begin{array}{c}\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 8</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="R"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">R</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; VIP</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}\\ \frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="10"\; label="R"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">R</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; VIN</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 7</span>}}\\ \mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="8"\; label="V"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 8</span>}\\ \mathrm{<span\; class="notranslate">\; VIP</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; HPF</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; PIN</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; )</span>\\ \mathrm{<span\; class="notranslate">\; VIN</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; XADVREF</span>}}\end{array}\right.$

Among them, V _{PIN_OUT} represents the external fiber optic gyroscope PIN output signal PIN_OUTPUT, HPF (V _{PIN_OUT} ) represents the DC blocking filtering of the PIN_OUTPUT signal; V _XADVREF represents the 1V raised level generated by the AD converter U2.

In the pre-amplification part in the present invention, the output voltage calculation formula of the voltage detection amplifier circuit is as follows:

$<span\; class="notranslate">\; \{</span>\underset{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; wxya</span>}}}{\overset{\mathrm{<span\; class="notranslate">\; VI</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; LPF</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; PIN</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; OUTPUT</span>}}<span\; class="notranslate">\; )</span>}{\frac{\mathrm{<span\; class="notranslate">\; VI</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="8"\; label="R"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">R</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 8</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="V"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">V</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 9</span>}}}}$

Among them, V _{PIN_OUT} represents the external fiber optic gyroscope PIN output signal PIN_OUTPUT, LPF (V _{PIN_OUT} ) represents the low-pass filtering of the PIN_OUTPUT signal; V _XGK represents the external raised level signal.

The output voltage calculation formula of the stepped wave drive amplifier circuit output by the modulation output circuit of the present invention is as follows:

The output voltage range of the parallel DA converter U4 is ±V, the output current range is 0-10mA,

When U4 input digital quantity is DAC_CODE

IOUTA＝IOUTFS·(DAC_CODE/65536)

IOUTB＝IOUTFS·(65536-DAC_CODE)/65536

Where IOUTFS is the total output current of the two differential ports $\mathrm{IOUTFS}=8\frac{\mathrm{<figure-callout\; id="26"\; label="XADVREF\; R"\; filenames="A20061011354300131.png"\; state="\{\{state\}\}">XADVREF</figure-callout>}}{R}=\mathrm{IOUTA}+\mathrm{IOUTB}$

1.1K is the internal resistance of U4.

Available:

$\left\{\begin{array}{c}\mathrm{<span\; class="notranslate">\; IOUTA</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 5</span>}\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; a</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 41</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; a</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; a</span>}}{\mathrm{<span\; class="notranslate">\; 1.1</span>}\mathrm{<span\; class="notranslate">\; K</span>}}\\ \mathrm{<span\; class="notranslate">\; IOUTB</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 42</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}}{\mathrm{<span\; class="notranslate">\; 1.1</span>}\mathrm{<span\; class="notranslate">\; K</span>}}\\ \mathrm{<span\; class="notranslate">\; IOUTA</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; IOUTB</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 8</span>}\frac{\mathrm{<span\; class="notranslate">\; XADVREF</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 26</span>}}\\ \mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; a</span>}\\ \end{array}\right.$

When adopting the ladder wave drive amplifying circuit of the present invention to output the voltage signal, the maximum digital value is output by the parallel DA converter U4, and the reference voltage signal provided by the serial DA converter U6 is adjusted, and the output voltage values of the output terminal JTB1 and the output terminal JTB2 are as follows: Table 1:

Table 1 Output voltage table of ladder wave drive amplifier circuit

U6 input digital value U4 reference voltage XDAVREF (unit: V) V8 (V1) (unit: V) VJTB1VJTB2 (unit: V) 180 0.36 -0.30 ±0.50 280 0.59 -0.48 ±0.78 380 0.80 -0.66 ±1.08

480 1.02 -0.84 ±1.40 580 1.24 -1.02 ±1.70 680 1.44 -1.22 ±2.00 780 1.66 -1.38 ±2.30 880 1.86 -1.60 ±2.60 980 2.06 -1.78 ±2.90 A80 2.28 -1.96 ±3.20 B80 2.50 -2.14 ±3.50 C80 2.72 -2.32 ±3.80 CC0 2.90 -2.50 ±4.02

Wherein, VJTB1 and VJTB2 represent the voltage values output by the output terminals JTB1 and JTB2. It can be seen from the above table that the design goal of output voltage range of 0V to ±4V can be achieved.

Claims (4)

1, a kind of preposition amplification of optical fibre gyro and modification output circuit with signal differential amplification is characterized in that:

Described pre-amplification circuit receives the light intensity information of voltage of photodetector output, and it is amplified, exports to digital signal processor after the Filtering Processing; It is made up of differential amplifier, operational amplifier and 12 bit parallel AD converter;

Described modification output circuit receives the digital modulation information by digital signal processor output, and exports to waveguide modulator after it is amplified; It is made up of 16 bit parallel DA converters, 10 bit serial DA converters, reference voltage source, differential amplifier and operational amplifier.

2, preposition amplification according to claim 1 and modification output circuit, it is characterized in that: each terminal of pre-amplification circuit is connected to, the PIN output signal PIN_OUTPUT end of optical fibre gyro is connected with high-pass filtering capacitor C 1, through after the high-pass filtering, signal transfers to 8 ends of differential amplifier U1 through resistance R 2; AD converter U2 produces raises 2 ends that level XADVREF signal is connected directly to differential amplifier U1, and the XADVREF signal is connected to filter capacitor C7 through being connected to 1 end of differential amplifier U1 after the resistance R 7 between XADVREF signal and the ground; Be parallel with resistance R 3 and capacitor C 9 between 8 ends of differential amplifier U1 and 5 ends, be parallel with resistance R 10 and capacitor C 10 between 1 end of differential amplifier U1 and 4 ends; 3 terminations of differential amplifier U1+5V power supply electrical level are connected to filter capacitor C11 between+5V power supply electrical level and the ground, 6 terminations of differential amplifier U1-5V power supply electrical level are connected to filter capacitor C12 between-5V power supply electrical level and the ground; 5 ends of differential amplifier U1 and 9 ends of AD converter U2 directly are connected with resistance R 5, be connected to filter capacitor C2 between 9 ends of AD converter U2 and the ground simultaneously, 4 ends of U1 and 10 ends of AD converter directly are connected with resistance R 13, are connected to filter capacitor C14 between 10 ends of AD converter U2 and the ground simultaneously; 2 terminations of U2+3.3V, 3 end ground connection, level XADVREF signal is raised in the output of 4 ends, 5 ends are connected with ground through capacitor C 20,5 ends are connected with ground through capacitor C 19, be parallel with capacitor C 16 between 5 ends and 6 ends, C17,7 ends and 12 terminations+3.3V, 8 ends, 11 ends and 14 end ground connection, 13 termination input clock signal XAD, 23 end ground connection, 24 terminations+3.3V, 24 ends and 23 ends also are connected with capacitor C 21 and C24,15 ends of U2,16 ends, 17 ends, 18 ends, 19 ends, 20 ends, 21 ends, 22 ends, 25 ends, 26 ends, 27 ends are connected output signal XADDT0～XADDT11 respectively with 28 ends.Be in series with resistance R 4 and R8 between PIN output signal PIN_OUTPUT of optical fibre gyro and 2 ends of operational amplifier U3, between R4, R8 and ground, be connected with filter capacitor C25, be parallel with resistance R 9 and capacitor C 26 between 2 ends of U3 and 1 end, 3 ends of U3 and external raising are connected with resistance R 6 between level signal XGK, be connected with capacitor C 8 between 3 ends of U3 and the ground; 8 terminations of U3+5V power supply electrical level are connected to filter capacitor C18 between+5V power supply electrical level and the ground, 4 terminations of U3-5V power supply electrical level are connected to filter capacitor C13 between-5V power supply electrical level and the ground; 1 end of U3 meets output signal GKA_OUT by resistance R 14, meets filter capacitor C22 between output signal GKA_OUT and the ground.

3, preposition amplification according to claim 1 and modification output circuit, it is characterized in that: being connected to of each terminal in the modification output circuit: digital signal XDADT15～XDADT0 is from 27 ends of 16 bit parallel DA converter U4,28 ends and 1 end～14 ends input, clock signal XDA is from the 26 ends input of U4,25 terminations of U4+5V supply voltage, be parallel with capacitor C 33 and C40 between+5V supply voltage and the ground, the 24 end ground connection of U4,23 terminations-5V supply voltage, be parallel with capacitor C 32 and C39 between-5V supply voltage and the ground, 22 ends of U4 have capacitor C 31 to be connected with-5V supply voltage, 21 ends of U4 have capacitor C 38 to be connected with-5V supply voltage, 20 ends of U4 are connected with 8 ends of differential amplifier U5, be connected to resistance R 22 between 20 ends of U4 and ground, 19 ends of U4 are connected with 1 end of differential amplifier U5, be connected to resistance R 21 between 19 ends of U4 and ground, 18 ends of U4 and 17 end ground connection, 16 ends of U4 are connected with reference voltage signal XADVREF by resistance R 26, reference voltage XADVREF is parallel with capacitor C 35 and C36 with ground, and 15 ends of U4 pass through capacitor C 37 and are connected with ground.The 2 end ground connection of differential amplifier U5 are parallel with between 8 ends and 5 ends between resistance R 41 and capacitor C 34,1 ends and 4 ends and are parallel with resistance R 42 and capacitor C 41; 3 terminations of U5+5V power supply electrical level are connected to filter capacitor C42 between+5V power supply electrical level and the ground, 6 terminations of U5-5V power supply electrical level are connected to filter capacitor C43 between-5V power supply electrical level and the ground; 5 ends of U5 link to each other with output terminal XJTB1 by resistance R 45, are connected to filter capacitor C51 between output terminal XJTB1 and the ground, and 4 ends of U5 link to each other with output terminal XJTB2 by resistance R 44, are connected to filter capacitor C52 between output terminal XJTB2 and the ground.1 end of reference voltage source JP1 and 2 terminations+5V power supply electrical level, 5 end ground connection, be connected to filter capacitor C44 between+5V power supply electrical level and the ground, 7 ends and 8 ends of 3 ends of JP1 and 4 terminated serial DA converter U6, be connected to filter capacitor C47 between 7 ends of U6 and 8 ends and the ground, the 1 termination input digit control signal XDONE of U6, the 2 termination input digit control signal XLDDA of U6,3 ends of U6 and 10 terminations+5V power supply electrical level, the 15 termination input digit control signal XLDREG of U6, the 14 termination input clock signal XLDCLK of U6, the 13 termination input digit control signal XSDI of U6,12 ends of U6 and 9 end ground connection, 4 ends of U6 link to each other with 3 ends of operational amplifier U7 by resistance R 23, be connected to filter capacitor C48 between 3 ends of U7 and the ground, be connected to resistance R 25 between 2 ends of U7 and the ground, be parallel with resistance R 24 and capacitor C 49 between 2 ends of U7 and 1 end, 8 terminations of U7+5V power supply electrical level, be connected to filter capacitor C53 between+5V power supply electrical level and the ground, 4 terminations of U7-5V power supply electrical level are connected to filter capacitor C50 between-5V power supply electrical level and the ground; The 1 end output reference voltage signal XADVREF of U7 is to resistance R 26.

4, preposition amplification according to claim 1 and modification output circuit is characterized in that: output staircase voltage scope be 0V～± 4V.

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