CN1925146A - Driver chip package structure and driver chip using multilayer bump bonding - Google Patents
Driver chip package structure and driver chip using multilayer bump bonding Download PDFInfo
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
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Abstract
Description
技术领域technical field
本发明涉及一种驱动芯片封装构造,特别是涉及一种利用多层凸块接合的驱动芯片封装构造以及具有多层凸块的驱动芯片。The invention relates to a driving chip packaging structure, in particular to a driving chip packaging structure utilizing multi-layer bump bonding and a driving chip with multi-layer bumps.
背景技术Background technique
现有习知的驱动芯片封装构造包括有卷带封装构造(Tape CarrierPackage,TCP)或薄膜覆晶封装构造(Chip On Film,COF),其是先在驱动芯片的焊垫形成金凸块,再热压合至卷带(Tape)或薄膜(Film),而在封装过程中,因金凸块的硬度值的变化太大,制程参数必须控制在较小的范围内,即制程窗(process window)较小,现有习知金凸块的硬度值在维氏硬度(Hv)35至65之间,即变动范围为维氏硬度30,可容许的内引脚接合(Inner Lead Bond,ILB)参数变化较小。The existing conventional driver chip packaging structures include Tape Carrier Package (TCP) or Chip On Film (COF), in which gold bumps are first formed on the pads of the driver chip, and then Thermal compression bonding to tape or film, and during the packaging process, because the hardness value of the gold bump changes too much, the process parameters must be controlled within a small range, that is, the process window (process window) ) is small, and the hardness value of the conventional gold bump is between Vickers hardness (Hv) 35 to 65, that is, the variation range is Vickers hardness 30, and the allowable inner lead bond (ILB) The parameter changes are small.
一种现有习知的凸块构造,是如中国台湾专利公告第488052号“无电镀形成双层以上金属凸块的制程”所揭示,其是在一设有若干焊垫的基板上形成一内层金属凸块,该内层金属凸块的材质是为镍,其高度是在15μm以上,一材质为金的外围金属层是完全包覆住该内层金属凸块外围,使得该双层以上金属凸块的总厚度在18μm以上,当一芯片的复数个焊垫形成该些凸块之后,必须再经过晶圆测试的步骤,在晶圆测试过程中,必须将探针插入该些焊垫上的双层以上金属凸块,由于该外围金属层(金)的高度是为该内层金属凸块(镍)的五分之一以下,即金层的厚度较薄,探针会因容易刺穿金层而抵触到硬度较硬的镍层,使得探针容易磨耗,严重时,甚至会因金层的厚度太薄,使得整个凸块的材质太硬而使探针无法插入凸块,无法作晶圆测试,此外,由于凸块与内引脚热压合是利用金与内引脚上所镀的锡产生共晶(eutectic)接合,若该双层以上金属凸块的金层的厚度太薄,会使得共晶不良而影响内引脚接合的强度。A known bump structure is as disclosed in Taiwan Patent Announcement No. 488052 "Process of Forming Metal Bumps with More than Two Layers by Electroless Plating". Inner metal bumps, the material of the inner metal bumps is nickel, and its height is more than 15 μm, and a peripheral metal layer made of gold completely covers the outer periphery of the inner metal bumps, so that the double layer The total thickness of the above metal bumps is more than 18μm. After the bumps are formed on a plurality of solder pads of a chip, the wafer test step must be performed. During the wafer test process, the probes must be inserted into these solder pads. For the metal bumps with more than two layers on the pad, because the height of the peripheral metal layer (gold) is less than one-fifth of the inner layer metal bump (nickel), that is, the thickness of the gold layer is thinner, and the probe will be easily pierced. Penetrating the gold layer and touching the harder nickel layer makes the probe easy to wear. In severe cases, even the thickness of the gold layer is too thin, making the material of the entire bump too hard so that the probe cannot be inserted into the bump and cannot be inserted into the bump. For wafer testing, in addition, since the thermal compression bonding between the bump and the inner lead is to use gold and the tin plated on the inner lead to produce eutectic (eutectic) bonding, if the thickness of the gold layer of the metal bump with more than two layers If it is too thin, it will make the eutectic poor and affect the strength of the inner pin joint.
由此可见,上述现有的驱动芯片封装构造在结构与使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。为了解决驱动芯片封装构造存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般产品又没有适切的结构能够解决上述问题,此显然是相关业者急欲解决的问题。因此如何能创设一种新型结构的驱动芯片封装构造,便成了当前业界极需改进的目标。It can be seen that the above-mentioned existing driver chip package structure obviously still has inconveniences and defects in structure and use, and needs to be further improved urgently. In order to solve the problems existing in the packaging structure of the driver chip, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure for general products to solve the above problems. Obviously, it is a problem that relevant industry players are eager to solve. Therefore, how to create a driver chip package structure with a new structure has become a goal that needs to be improved in the current industry.
有鉴于上述现有的驱动芯片封装构造存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,并配合学理的运用,积极加以研究创新,以期创设一种新型的利用多层凸块接合的驱动芯片封装构造及驱动芯片,能够改进一般现有的驱动芯片封装构造及驱动芯片,使其更具有实用性。经过不断的研究、设计,并经反复试作样品及改进后,终于创设出确具实用价值的本发明。In view of the defects in the above-mentioned existing driver chip packaging structure, the inventor actively researches and innovates based on years of rich practical experience and professional knowledge in the design and manufacture of such products, and cooperates with the application of academic theories, in order to create a new type of driver chip. Utilizing the driver chip package structure and driver chip bonded by multi-layer bumps can improve the general existing driver chip package structure and driver chip, making it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.
发明内容Contents of the invention
本发明的目的在于,提供一种新型的利用多层凸块接合的驱动芯片封装构造及驱动芯片,所要解决的技术问题是使得该驱动芯片与该电路薄膜热压合时,防止该些连接端过份溃陷于该些多层凸块内,从而更加适于实用。The purpose of the present invention is to provide a new driver chip packaging structure and driver chip utilizing multi-layer bump bonding. The technical problem to be solved is to prevent the connecting terminals from Excessive collapse in these multi-layer bumps is more suitable for practical use.
本发明的另一目的在于,提供一种新型的利用多层凸块接合的驱动芯片封装构造及驱动芯片,所要解决的技术问题是使该些多层凸块的硬度值的变动范围缩小,而能在热压合该驱动芯片时具有较大的制程窗(processwindow),从而更加适于实用。Another object of the present invention is to provide a novel drive chip package structure and drive chip utilizing multilayer bump bonding. The technical problem to be solved is to reduce the variation range of the hardness values of these multilayer bumps, and It can have a larger process window (process window) when thermally pressing the driver chip, so it is more suitable for practical use.
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种利用多层凸块接合的驱动芯片封装构造,其包括:一电路薄膜,其包括有一电绝缘软膜本体及一导电线路层,该导电线路层是形成于该电绝缘软膜本体并具有复数个连接端;一驱动芯片,其具有一主动面,该主动面是形成有复数个焊垫;及复数个多层凸块,其是设在该驱动芯片的该主动面上,以供热压合该些连接端,每一多层凸块包括一基础金属层及一接合金属层,该些基础金属层是设在该些焊垫上,该些接合金属层是形成在该些基础金属层上且其硬度是小于该些基础金属层,当该电路薄膜的该些连接端共晶接合于该些接合金属层时,该些基础金属层是可防止该些连接端过份溃陷于该些多层凸块内。The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to the present invention, a driving chip packaging structure utilizing multi-layer bump bonding includes: a circuit film, which includes an electrically insulating soft film body and a conductive circuit layer, and the conductive circuit layer is formed on the electrically insulating The soft film body has a plurality of connection ends; a driving chip has an active surface, and the active surface is formed with a plurality of welding pads; and a plurality of multi-layer bumps are arranged on the active surface of the driving chip For thermal compression bonding of the connecting ends, each multi-layer bump includes a basic metal layer and a bonding metal layer, the basic metal layers are set on the pads, and the bonding metal layers are formed on These basic metal layers and its hardness is less than these basic metal layers, when the connection terminals of the circuit film are eutectically bonded to the bonding metal layers, these basic metal layers can prevent the connection terminals from being too Parts are collapsed in the multi-layer bumps.
本发明的目的及解决其技术问题还采用以下技术措施来进一步实现。The purpose of the present invention and the solution to its technical problems also adopt the following technical measures to further realize.
前述的利用多层凸块接合的驱动芯片封装构造,其中所述的该些基础金属层是包含镍,且该些接合金属层是包含金。In the aforementioned driving chip package structure using multi-layer bump bonding, the basic metal layers include nickel, and the bonding metal layers include gold.
前述的利用多层凸块接合的驱动芯片封装构造,其中所述的该些基础金属层的硬度是不小于该电路薄膜的该些连接端的硬度。In the aforementioned driving chip package structure utilizing multi-layer bump bonding, the hardness of the basic metal layers is not less than the hardness of the connection ends of the circuit film.
前述的利用多层凸块接合的驱动芯片封装构造,其中所述的该些基础金属层的厚度是不大于该些接合金属层的二倍厚度。In the aforementioned driver chip package structure utilizing multi-layer bump bonding, the thickness of the base metal layers is not greater than twice the thickness of the bonding metal layers.
前述的利用多层凸块接合的驱动芯片封装构造,其中所述的该些基础金属层的维氏硬度(Hv)是介于280~350,而该些接合金属层的维氏硬度(Hv)是介于45~75。In the aforementioned driving chip package structure utilizing multi-layer bump bonding, the Vickers hardness (Hv) of the base metal layers is between 280-350, and the Vickers hardness (Hv) of the bonding metal layers is It is between 45 and 75.
前述的利用多层凸块接合的驱动芯片封装构造,其中所述的该些焊垫上是形成有一凸块下金属层。In the aforementioned driver chip package structure utilizing multi-layer bump bonding, an UBM layer is formed on the pads.
前述的利用多层凸块接合的驱动芯片封装构造,其另包括一封胶体,其是包覆该些多层凸块。The aforementioned driver chip package structure utilizing multi-layer bump bonding further includes an encapsulant encapsulating the multi-layer bumps.
前述的利用多层凸块接合的驱动芯片封装构造,其中所述的电路薄膜是为卷带承载封装(TCP)的卷带(Tape),该电路薄膜具有一开口,该些连接端是悬空形成于该开口内。The aforementioned driving chip package structure utilizing multi-layer bump bonding, wherein the circuit film is a tape (Tape) of a tape carrier package (TCP), the circuit film has an opening, and the connecting ends are formed in the air in the opening.
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种具有多层凸块的驱动芯片,其具有一主动面,该主动面是形成有一焊垫,该焊垫是形成有一多层凸块,该多层凸块包括一基础金属层及一接合金属层,该基础金属层是接合于该些焊垫,而该接合金属层是形成在该基础金属层上,该基础金属层的硬度是大于该接合金属层,且该基础金属层的厚度是不大于该接合金属层的二倍厚度。The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. According to the present invention, a driver chip with multi-layer bumps has an active surface, and the active surface is formed with a pad, and the pad is formed with a multi-layer bump, and the multi-layer bump includes a A basic metal layer and a bonding metal layer, the basic metal layer is bonded to the pads, and the bonding metal layer is formed on the basic metal layer, the hardness of the basic metal layer is greater than that of the bonding metal layer, and the The thickness of the basic metal layer is not greater than twice the thickness of the bonding metal layer.
本发明的目的及解决其技术问题还采用以下技术措施来进一步实现。The purpose of the present invention and the solution to its technical problems also adopt the following technical measures to further realize.
前述的具有多层凸块的驱动芯片,其中所述的焊垫与该基础金属层之间是形成有一凸块下金属层。In the aforementioned driver chip with multi-layer bumps, an under-bump metal layer is formed between the pad and the basic metal layer.
本发明与现有技术相比具有明显的优点和有益效果。由以上技术方案可知,本发明的主要技术内容如下:Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from above technical scheme, main technical content of the present invention is as follows:
为了达到上述目的,本发明提供了一种利用多层凸块接合的驱动芯片封装构造,其包括一电路薄膜,该电路薄膜包括有一电绝缘软膜本体及一导电线路层,该导电线路层是形成于该电绝缘软膜本体,并具有复数个连接端,以电性导接一驱动芯片,该驱动芯片具有一主动面,该主动面是朝向该导电线路层的该些连接端,该主动面是形成有复数个焊垫,该些焊垫是对应该些连接端,且该些连接端与该些焊垫之间是形成有复数个多层凸块,每一多层凸块包括一基础金属层及一接合金属层,该些基础金属层的硬度是大于该些接合金属层,该些基础金属层的维氏硬度(Hv)是介于280~350,该些接合金属层的维氏硬度是介于45~75,利用多层次金属硬度的不同(往凸块底部渐硬),来达到维持凸块的大体外形(即基础层)与共晶接合(接合层)的功效。而该些基础金属层是接合于该些焊垫,该些接合金属层是共晶接合于该些连接端,以使该驱动芯片的该些焊垫与该电路薄膜的该些连接端电性连接。In order to achieve the above object, the present invention provides a driver chip packaging structure utilizing multi-layer bump bonding, which includes a circuit film, the circuit film includes an electrically insulating soft film body and a conductive circuit layer, the conductive circuit layer is It is formed on the main body of the electrically insulating soft film, and has a plurality of connecting ends to electrically connect a driving chip. The driving chip has an active surface, and the active surface is facing the connecting ends of the conductive circuit layer. A plurality of welding pads are formed on the surface, and the welding pads are corresponding to the connecting ends, and a plurality of multi-layer bumps are formed between the connecting ends and the welding pads, and each multi-layer bump includes a The basic metal layer and a bonding metal layer, the hardness of the basic metal layers is greater than that of the bonding metal layers, the Vickers hardness (Hv) of the basic metal layers is between 280-350, and the Vickers hardness (Hv) of the bonding metal layers is The hardness ranges from 45 to 75. Using the difference in hardness of the multi-layered metal (gradually hardening towards the bottom of the bump), the effect of maintaining the general shape of the bump (that is, the base layer) and the eutectic bonding (bonding layer) is achieved. The basic metal layers are bonded to the pads, and the bonding metal layers are eutectic bonded to the connecting ends, so that the bonding pads of the driver chip are electrically connected to the connecting ends of the circuit film. connect.
借由上述技术方案,本新型驱动芯片封装构造以及具有多层凸块的驱动芯片至少具有下列优点:By virtue of the above technical solutions, the novel driver chip packaging structure and the driver chip with multi-layer bumps have at least the following advantages:
本发明是利用复数个多层凸块形成在一驱动芯片的复数个焊垫上,每一多层凸块包括一基础金属层及一接合金属层,该些基础金属层是接合于该驱动芯片的复数个焊垫,当该驱动芯片与该电路薄膜热压合时,该些接合金属层是共晶接合于一电路薄膜的复数个连接端,由于该些基础金属层的硬度是大于该些接合金属层,可以防止该些连接端过份溃陷于该些多层凸块内,且不会因共晶不良而影响内引脚接合的强度。The present invention uses a plurality of multi-layer bumps to be formed on a plurality of welding pads of a driver chip, each multi-layer bump includes a base metal layer and a bonding metal layer, and the base metal layers are bonded to the drive chip A plurality of welding pads, when the driver chip and the circuit film are thermocompressed, the bonding metal layers are eutectically bonded to a plurality of connection ends of a circuit film, because the hardness of the basic metal layers is greater than that of the bonding The metal layer can prevent the connecting ends from being excessively collapsed in the multi-layer bumps, and will not affect the bonding strength of the inner pins due to poor eutectic.
本发明利用复数个多层凸块形成在一驱动芯片的复数个焊垫上,每一多层凸块包括一基础金属层及一接合金属层,且该些基础金属层的硬度是大于该些接合金属层,以使该些多层凸块的接合金属层均能确实接合连接端且不会过份溃陷,而能在一电路薄膜与该驱动芯片热压合时具有较大的制程窗(process window)。The present invention utilizes a plurality of multilayer bumps to be formed on a plurality of welding pads of a driver chip, each multilayer bump includes a basic metal layer and a bonding metal layer, and the hardness of the basic metal layers is greater than that of the bonding metal layer, so that the bonding metal layers of these multi-layer bumps can surely bond the connection ends without excessive collapse, and can have a larger process window when a circuit film and the driver chip are thermocompressed ( process window).
综上所述,本发明特殊结构的利用多层凸块接合的驱动芯片封装构造及驱动芯片,其具有上述诸多的优点及实用价值,并在同类产品中未见有类似的结构设计公开发表或使用而确属创新,其不论在产品结构或功能上皆有较大的改进,在技术上有较大的进步,并产生了好用及实用的效果,且较现有的驱动芯片封装构造及驱动芯片具有增进的多项功效,从而更加适于实用,而具有产业广泛利用价值,诚为一新颖、进步、实用的新设计。To sum up, the drive chip packaging structure and drive chip with the special structure of the present invention using multi-layer bump bonding have the above-mentioned many advantages and practical value, and there is no similar structural design published or published in similar products. It is indeed an innovation because of its use, which has greatly improved both in product structure and function, and has made great progress in technology, and has produced easy-to-use and practical effects, and is more advanced than the existing driver chip packaging structure and The driver chip has multiple enhanced functions, so it is more suitable for practical use, and has wide application value in the industry. It is a novel, progressive and practical new design.
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.
附图说明Description of drawings
图1是本发明的利用多层凸块接合的驱动芯片封装构造的截面示意图。FIG. 1 is a schematic cross-sectional view of a driving chip package structure utilizing multi-layer bump bonding according to the present invention.
图2是本发明的驱动芯片封装构造的部分放大截面示意图。FIG. 2 is a partially enlarged schematic cross-sectional view of the packaging structure of the driving chip of the present invention.
100:驱动芯片封装构造100: driver chip package structure
110:电路薄膜 111:电绝缘软膜本体110: Circuit film 111: Electric insulation soft film body
112:导电线路层 113:开口112: Conductive circuit layer 113: Opening
114:连接端 120:驱动芯片114: Connection terminal 120: Driver chip
121:主动面 122:保护层121: active surface 122: protective layer
123:焊垫 124:凸块下金属层123: Welding pad 124: UBM layer
130:多层凸块 131:基础金属层130: Multi-layer bump 131: Basic metal layer
132:接合金属层 140:封胶体132: Joint metal layer 140: Sealant
具体实施方式Detailed ways
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的利用多层凸块接合的驱动芯片封装构造及驱动芯片其具体实施方式、结构、特征及其功效,详细说明如后。In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, in conjunction with the accompanying drawings and preferred embodiments, the driving chip packaging structure and the driving chip using multi-layer bump bonding proposed according to the present invention will be described below. Specific embodiments, structures, features and effects thereof are described in detail below.
请参阅图1及图2所示,是本发明的一具体实施例,该利用多层凸块接合的驱动芯片封装构造100,其包括一电路薄膜110,该电路薄膜100是可为卷带承载封装(TCP)的卷带(Tape)或薄膜覆晶封装(COF)的薄膜(Film),在本实施例中是以卷带例举,该电路薄膜110,包括有一电绝缘软膜本体111及一导电线路层112,且该电绝缘软膜本体111具有一开口113,该电绝缘软膜本体111的材质是为聚亚酰胺(polyimide,PI)或聚酯(polyester,PET),该导电线路层112的材质是可为铜等金属,并形成于该电绝缘软膜本体111,该导电线路层112具有复数个连接端114,较佳的,该些连接端114是电镀有一锡层(图中未示),该些连接端114是形成于开口113,以电性导接一驱动芯片120;Please refer to FIG. 1 and FIG. 2, which is a specific embodiment of the present invention. The driving
该驱动芯片120,具有一主动面121,该主动面121是朝向该导电线路层112的该些连接端114,该主动面121是形成有一保护层122及复数个焊垫123,该些焊垫123上是形成有一凸块下金属层124,且该些焊垫123是对应该些连接端114;The
复数个多层凸块130是形成在该些焊垫123的凸块下金属层124而设于该些连接端114与该些焊垫123之间,该些多层凸块的高度是介于15至30μm,每一多层凸块130包括一基础金属层131及一接合金属层132,该些基础金属层131是接合于该些焊垫123的凸块下金属层124,而该些接合金属层132是共晶接合于该些连接端114,以使该驱动芯片120的该些焊垫123与该电路薄膜110的该些连接端114电性连接,在本实施例中,该些基础金属层131的硬度是大于该些接合金属层132,该些基础金属层131的维氏硬度(Hv)是介于280~350,例如镍等较硬材质,而该些接合金属层132的维氏硬度是介于45~75,例如金等较软材质,使得该些多层凸块130的维氏硬度是介于80至100之间,且该些基础金属层131的厚度是不大于该些接合金属层132的二倍厚度为佳,即该些基础金属层131的厚度是不超过该些多层凸块130的高度的三分之二,较佳的,该驱动芯片封装构造100另包括一封胶体140,该封胶体140是设于该开口113,以包覆该些多层凸块130与该些连接端114。A plurality of
由于接合于该些焊垫123的该些基础金属层131的硬度是大于接合于该些连接端114的该些接合金属层132,当该驱动芯片120与该电路薄膜110热压合时,可防止该些连接端114过份溃陷于该些多层凸块130内,而能有效控制该些多层凸块130结合后的高度。因此,在该驱动芯片120与该电路薄膜110热压合时的制程参数可容许的变化范围较大,具有较大的制程窗(process window)。Since the hardness of the
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的结构及技术内容作出些许的更动或修饰为等同变化的等效实施例,但是凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the structure and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.
Claims (10)
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US8053906B2 (en) | 2008-07-11 | 2011-11-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for processing and bonding a wire |
US8076786B2 (en) | 2008-07-11 | 2011-12-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for packaging a semiconductor package |
US8110931B2 (en) | 2008-07-11 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Wafer and semiconductor package |
CN108962914A (en) * | 2017-05-19 | 2018-12-07 | 启耀光电股份有限公司 | Electronic device and manufacturing method thereof |
CN113035966A (en) * | 2021-03-11 | 2021-06-25 | 业成科技(成都)有限公司 | Photoinduction structure and preparation method thereof, solar cell and electronic equipment |
-
2005
- 2005-08-30 CN CNA2005100938111A patent/CN1925146A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8053906B2 (en) | 2008-07-11 | 2011-11-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for processing and bonding a wire |
US8076786B2 (en) | 2008-07-11 | 2011-12-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for packaging a semiconductor package |
US8110931B2 (en) | 2008-07-11 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Wafer and semiconductor package |
CN108962914A (en) * | 2017-05-19 | 2018-12-07 | 启耀光电股份有限公司 | Electronic device and manufacturing method thereof |
CN113035966A (en) * | 2021-03-11 | 2021-06-25 | 业成科技(成都)有限公司 | Photoinduction structure and preparation method thereof, solar cell and electronic equipment |
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