CN1912633A - Semiconductor test board structure for preventing noise interference - Google Patents
Semiconductor test board structure for preventing noise interference Download PDFInfo
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- CN1912633A CN1912633A CN 200510089799 CN200510089799A CN1912633A CN 1912633 A CN1912633 A CN 1912633A CN 200510089799 CN200510089799 CN 200510089799 CN 200510089799 A CN200510089799 A CN 200510089799A CN 1912633 A CN1912633 A CN 1912633A
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Abstract
一种用于防止噪声干扰的半导体测试板结构，其包括：多个探针层、多个隔板、多个接地的隔离针及多个空隔。每一个探针层设置有多个具有相同信号功能的探针；该等隔板接地且分别设置于每二个探针层之间，以防止这些探针层间的噪声干扰；这些接地的隔离针分别连接于这些探针的一部分，用于隔绝另一部分探针间的噪声干扰；这些空隔分别设置于一部分探针的探针间，以增加该部分探针间彼此的距离及噪声干扰。再者，通过一信号延伸基板的使用，可缩短传统探针的长度，并降低探针间噪声的干扰。
A semiconductor test board structure for preventing noise interference, comprising: multiple probe layers, multiple partitions, multiple grounded isolation needles and multiple spacers. Each probe layer is provided with multiple probes with the same signal function; the partitions are grounded and respectively arranged between every two probe layers to prevent noise interference between these probe layers; the grounded isolation needles are respectively connected to a part of these probes to isolate the noise interference between another part of the probes; the spacers are respectively arranged between the probes of a part of the probes to increase the distance and noise interference between the probes of this part. Furthermore, by using a signal extension substrate, the length of the traditional probe can be shortened and the noise interference between the probes can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor test plate structure that is used to prevent noise (noise) interference, especially refer to that a kind of probe that will have the same signal function is arranged in in one deck, and the isolation pin by dividing plate, ground connection (grounding), empty every (space) and/or signal extension substrate, with the semiconductor test plate structure of the noise resisting ability that increases probe (probe needle).
Background technology
Usually, wafer (wafer) make finish after, just need enter the wafer sort stage to guarantee whether conformance with standard of its function.Generally, whether wafer sort is to utilize tester table and probe (probe card) to come each crystal grain on the test wafer, have according to original design specification with electrical specification and the usefulness of guaranteeing crystal grain.And along with chip functions is stronger more complicated, also just more important with accurate testing requirement at a high speed.
Moreover probe is applied to integrated circuit (IC) as yet before the encapsulation, does function test at naked crystalline substance with probe (probeneedle), filtering out defective products, and then the encapsulation engineering after carrying out.Therefore, it is in the integrated circuit manufacturing manufacturing cost to be influenced one of sizable important process.
In the general test process, at first, again probe is fixed on the tester table on the tester table crystal grain on the wafer being located, so that the weld pad on the crystal grain is aimed at the probe of probe, and contact with it.
See also Figure 1 and Figure 2, it is respectively the vertical view of conventional semiconductors test board and the probe diagrammatic cross-section that tradition is used for semiconductor test board.By among the figure as can be known, traditional semiconductor test board includes: a circuit board (PCB) 10a, a probe base 20a, and a plurality of probe 30a.Wherein, the distance that these probes 30a difference each interval one is scheduled to, and be arranged in this probe base 20a, and these probes 30a is arranged in a plurality of probe layer 31a (as shown in Figure 2) with matrix-style.In addition, these probes 30a is electrically connected on this circuit board 10a, in order to do different types of performance test at wafer (figure does not show).
And, traditional these probes 30a is hypotelorism and the relation (for example the probe 30 of digital signal (digital signal) D, simulating signal (analog signal) A or power supply signal (power signal) P is mingled with arrangement) that is mingled with of digital/analog signal to each other to each other, make these probes 30a produce mutual noise, and then influence is to the test quality of wafer.
Therefore, as from the foregoing, above-mentioned traditional semiconductor test plate structure on reality is used, obviously has inconvenience and exists with shortcoming, and wait for and being improved.
So the inventor remains to be improved part thoughts on above-mentioned shortcoming, and according to the correlation experience of being engaged in for many years in this respect, the concentrated observation and research, and cooperate utilization of science, and propose a kind of reasonable in design and effectively improve the present invention of above-mentioned shortcoming.
Summary of the invention
Technical matters to be solved by this invention provides a kind of semiconductor test plate structure that is used to prevent noise (noise) interference.The probe that the present invention will have the same signal function is arranged in in one deck, and the isolation pin by dividing plate, ground connection (grounding), empty every modes such as (space) and/or signal extension substrates, to increase probe (probe needle) noise resisting ability to each other.That is, when probe structure of the present invention carries out performance test at wafer, can be because of these probes mutual noise to each other, and influence the quality of wafer sort; In addition, the probe that will have the same signal function is arranged in in one deck, the qualification rate in the time of more increasing the degree of stability when using probe and promote test wafer; Moreover, by the use of this signal extension substrate, can shorten the length of conventional probe greatly, and reduce interference of noise between probe.
In order to solve the problems of the technologies described above, according to wherein a kind of scheme of the present invention, a kind of semiconductor test plate structure that is used to prevent that noise (noise) from disturbing is provided, and it comprises: a substrate, a probe base, a plurality of probe (probe needle) layer, and a plurality of dividing plates.Wherein, substrate has a plurality of signal contacts; This probe base is arranged on this substrate; Each probe layer is provided with a plurality of probes with same signal function, and an end of these probes is arranged in this probe base and exposes this probe base, and the other end of these probes is electrically connected at these signal contacts respectively; And these dividing plates are arranged at respectively between per two probe layers, and these dividing plate ground connection (grounding) wherein are to be used to prevent the noise between these probe layers.
In order to solve the problems of the technologies described above, according to wherein a kind of scheme of the present invention, a kind of semiconductor test plate structure that is used to prevent that noise (noise) from disturbing is provided, and it comprises: a substrate, a probe base, a plurality of probe (probe needle) layer, and the isolation pin of a plurality of ground connection (grounding).Wherein, substrate has a plurality of signal contacts; This probe base is arranged on this substrate; Each probe layer is provided with a plurality of probes with same signal function, and an end of these probes is arranged in this probe base and exposes this probe base, and the other end of these probes is electrically connected at these signal contacts respectively; And the isolation pin of these ground connection is electrically connected at the part of these probes respectively, is used for the noise between isolated another part probe.
In order to solve the problems of the technologies described above, according to wherein a kind of scheme of the present invention, a kind of semiconductor test plate structure that is used to prevent that noise (noise) from disturbing is provided, and it comprises: a substrate, a probe base, a plurality of probe (probe needle) layer, and a plurality of skies every (space).Wherein, substrate has many signal contacts; This probe base is arranged on this substrate; Each probe layer is provided with a plurality of probes with same signal function, and an end of these probes is arranged in this probe base and exposes this probe base, and the other end of these probes is electrically connected at these signal contacts respectively; And these skies increasing between this part probe distance each other, and are used for the noise between isolated this part probe every between the probe that is arranged at a part of probe respectively.
In order to solve the problems of the technologies described above, according to wherein a kind of scheme of the present invention, a kind of semiconductor test plate structure that is used to prevent that noise (noise) from disturbing is provided, and it comprises: a substrate, a probe base, a plurality of probe (probe needle) layer, a plurality of dividing plate, a plurality of wire probe, reach a signal extension substrate.Wherein, this substrate has a plurality of signal contacts; This probe base is arranged on this substrate; Each probe layer is provided with a plurality of probes with same signal function, and an end of these probes is arranged in this probe base and exposes this probe base; These dividing plates are arranged at respectively between per two probe layers, and these dividing plate ground connection (grounding) wherein are to be used to prevent the noise between these probe layers; One end of these wire probe is electrically connected at these signal contacts respectively; And this signal extension substrate is electrically connected at respectively between the other end of the other end of these probes and these wire probe.In order to solve the problems of the technologies described above, according to wherein a kind of scheme of the present invention, a kind of semiconductor test plate structure that is used to prevent that noise (noise) from disturbing is provided, and it comprises: a substrate, a probe base, a plurality of probe (probe needle) layer, a plurality of dividing plate, reach a signal extension substrate.Wherein, this probe base is arranged on this substrate; Each probe layer is provided with a plurality of probes with same signal function, and an end of these probes is arranged in this probe base and exposes this probe base; These dividing plates are arranged at respectively between per two probe layers, and these dividing plate ground connection (grounding) wherein are to be used to prevent the noise between these probe layers; And this signal extension substrate is electrically connected at respectively between the other end and this substrate of these probes.
Reach technology, means and the beneficial effect that predetermined purpose is taked in order further to understand the present invention, see also following about detailed description of the present invention and accompanying drawing, believe purpose of the present invention, feature and characteristics, go deep into and concrete understanding when getting one thus, yet appended graphic reference and the explanation usefulness of only providing not is to be used for the present invention is limited.
Description of drawings
Fig. 1 is the vertical view of conventional semiconductors test board;
Fig. 2 is used for the probe diagrammatic cross-section of semiconductor test board for tradition;
Fig. 3 is used to prevent the vertical view of the semiconductor test plate structure that noise (noise) disturbs for the present invention;
Fig. 4 is used to prevent the probe diagrammatic cross-section of first embodiment of the semiconductor test plate structure that noise (noise) disturbs for the present invention;
Fig. 5 is used to prevent the probe diagrammatic cross-section of second embodiment of the semiconductor test plate structure that noise (noise) disturbs for the present invention;
Fig. 6 is used to prevent the probe diagrammatic cross-section of the 3rd embodiment of the semiconductor test plate structure that noise (noise) disturbs for the present invention;
Fig. 7 is used to prevent the probe diagrammatic cross-section of the 4th embodiment of the semiconductor test plate structure that noise (noise) disturbs for the present invention;
Fig. 8 is used to prevent the vertical view of the 5th embodiment of the semiconductor test plate structure that noise (noise) disturbs for the present invention; And
Fig. 9 is used to prevent the vertical view of the 6th embodiment of the semiconductor test plate structure that noise (noise) disturbs for the present invention.
Wherein, description of reference numerals is as follows:
[prior art]
Circuit board 10a
Probe base 20a
Probe 30a probe layer 31a
Simulating signal A
Power supply signal P
Pin footpath h, H
[the present invention]
Substrate 1 signal contact 10
Dividing plate 4
The isolation pin 6 of ground connection
Empty every 7
Wire probe 9
Digital signal D
Simulating signal A
Power supply signal P
Pin footpath h, H
Embodiment
See also Fig. 3 and shown in Figure 4, it is respectively the present invention and is used to prevent the vertical view of the semiconductor test plate structure that noise (noise) disturbs and the probe diagrammatic cross-section of first embodiment of the invention.By among the figure as can be known, the invention provides a kind of semiconductor test plate structure that is used to prevent that noise (noise) from disturbing, it comprises: a substrate 1, a probe base 2, a plurality of probe (probe needle) layer 3, and a plurality of dividing plates 4.
Wherein, this substrate 1 is to have the circuit board that circuit distributes, and this substrate 1 has a plurality of signal contacts 10.Moreover, this probe base 2 is arranged on this substrate 1, and each probe layer 3 is provided with a plurality of probes 30 with same signal function, and wherein this semiotic function comprises: digital signal (digitalsignal) D, simulating signal (analog signal) A and power supply signal (power signal) P.In addition, these probes 3 are the predetermined distance of each intervals one respectively, and an end of these probes 3 is arranged in this probe base 2 and exposes this probe base 2, and the other end of these probes 3 is electrically connected at these signal contacts 10 respectively.
In addition, these dividing plates 4 are arranged at respectively between per two probe layers 3, these dividing plate 4 ground connection (grounding) wherein, and to be used to prevent the noise between these probe layers, it is made that wherein these dividing plates 4 can be the metal material of tool noise screening effect.These signal wires 5 are electrically connected at respectively between these probes 30 and these signal contacts 10.In addition, the part of these probes 30 has the pin footpath H bigger than general pin footpath h, the work efficiency that is used to reduce the resistance of this part probe and increases this part probe.
See also Fig. 3 and shown in Figure 5, it is respectively the present invention and is used to prevent the vertical view of the semiconductor test plate structure that noise (noise) disturbs and the probe diagrammatic cross-section of second embodiment of the invention.By among the figure as can be known, the invention provides a kind of semiconductor test plate structure that is used to prevent that noise (noise) from disturbing, it comprises: a substrate 1, a probe base 2, a plurality of probe (probe needle) layer 3, and the isolation pin 6 of a plurality of ground connection (grounding).
Wherein, second embodiment is with first the different of embodiment maximum: the isolation pin 6 of these ground connection is electrically connected at the part of these probes 30 respectively, is used for the noise between isolated another part probe.These signal wires 5 are electrically connected at respectively between these probes 30 and these signal contacts 10.
See also Fig. 3 and shown in Figure 6, it is respectively the present invention and is used to prevent the vertical view of the semiconductor test plate structure that noise (noise) disturbs and the probe diagrammatic cross-section of third embodiment of the invention.By among the figure as can be known, the invention provides a kind of semiconductor test plate structure that is used to prevent that noise (noise) from disturbing, it comprises: a substrate 1, a probe base 2, a plurality of probe (probe needle) layer 3, and a plurality of skies every (space) 7.
Wherein, second embodiment is with first the different of embodiment maximum: these skies are arranged at respectively between the probe of a part of probe 30 every 7, increasing between this part probe distance each other, and are used for the noise between isolated this part probe.These signal wires 5 are electrically connected at respectively between these probes 30 and these signal contacts 10.
See also shown in Figure 7ly, it is used to prevent the probe diagrammatic cross-section of the 4th embodiment of the semiconductor test plate structure that noise (noise) disturbs for the present invention.By among the figure as can be known, the 4th embodiment be the first～three execute the example combination, it provides a kind of semiconductor test plate structure that is used to prevent noise (noise) interference, and it comprises: the isolation pin 6 of a plurality of probes (probe needle) layer 3, a plurality of dividing plate 4, a plurality of ground connection (grounding) and a plurality of sky are every (space) 7.
Wherein, these dividing plates 4 are arranged at respectively between per two probe layers 3, these dividing plate 4 ground connection (grounding) wherein, and to be used to prevent the noise between these probe layers, it is made that wherein these dividing plates 4 can be the metal material of tool noise screening effect.The isolation pin 6 of these ground connection is electrically connected at the part of these probes 30 respectively, is used for the noise between isolated another part probe.These skies are arranged at respectively between the probe of a part of probe 30 every 7, increasing between this part probe distance each other, and are used for the noise between isolated this part probe.In addition, the part of these probes 10 has the pin footpath H bigger than general pin footpath h, the work efficiency that is used to reduce the resistance of this part probe and increases this part probe.
See also shown in Figure 8ly, it is used to prevent the vertical view of the semiconductor test plate structure that noise (noise) disturbs for the present invention.By among the figure as can be known, the 5th embodiment is with the different of the foregoing description maximum: set up a signal extension substrate 8 and a plurality of wire probe 9.By this, one end of these wire probe 9 is electrically connected at these signal contacts 10 respectively, and this signal extension substrate 9 is electrically connected at respectively between the other end of the other end of these probes 30 and these wire probe 9, the qualification rate when being used to increase the degree of stability when using probe and promoting test wafer.
See also shown in Figure 9ly, it is used to prevent the vertical view of the semiconductor test plate structure that noise (noise) disturbs for the present invention.By among the figure as can be known, the 6th embodiment is with the 5th the different of embodiment maximum: this signal extension substrate 8 is electrically connected at respectively between the other end and this substrate 1 of these probes 30, in order to the electric connection that reaches these probes and this substrate, and qualification rate when increasing the degree of stability when using probe and promoting test wafer.Moreover, by the use of this signal extension substrate 8, can shorten traditional signal wire 40a length that electrically conducts between probe 30a and circuit board 10a greatly, and reduce by 30 interference of noise of probe.
By the foregoing description as can be known, the present invention can be according to user's needs, and use a kind of or in conjunction with multiple above-mentioned embodiment, to reach when the test wafer, produce different antinoise effects.
In sum, the probe that the present invention will have the same signal function is arranged in in one deck, and the isolation pin 6 by dividing plate 4, ground connection (grounding), empty every modes such as (space) 7 and/or signal extension substrates 8, to increase probe (probe needle) 30 noise resisting ability to each other.Therefore, when probe structure of the present invention carries out performance test at wafer, can be because of these probes mutual noise to each other, and influence the quality of wafer sort; In addition, the probe that will have the same signal function is arranged in in one deck, the qualification rate in the time of more increasing the degree of stability when using probe 30 and promote test wafer; Moreover, by the use of this signal extension substrate 8, can shorten the length of conventional probe 30 greatly, and reduce interference of noise between probe.
Therefore, the present invention is a rare invention product in fact, has novelty and progressive, meets the application for a patent for invention requirement fully, and the spy files an application according to Patent Law, would like to ask detailed survey and grants accurate this case patent, to ensure inventor's rights and interests.
And, the above, only be one of the detailed description of the specific embodiment of the best of the present invention and accompanying drawing, and feature of the present invention is not limited thereto, be not in order to restriction the present invention, all scopes of the present invention should be as the criterion with claim, all closing in the embodiment of the spirit variation similar of the present patent application claim with it, all should be contained in the category of the present invention, anyly be familiar with this skill person in the field of the invention, can think easily and variation or modify and all can be encompassed in claim of the present invention.
Claims (41)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100897997A CN100424514C (en) | 2005-08-09 | 2005-08-09 | Semiconductor test board structure for preventing noise interference |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100897997A CN100424514C (en) | 2005-08-09 | 2005-08-09 | Semiconductor test board structure for preventing noise interference |
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| Publication Number | Publication Date |
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| CN1912633A true CN1912633A (en) | 2007-02-14 |
| CN100424514C CN100424514C (en) | 2008-10-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100897997A Expired - Fee Related CN100424514C (en) | 2005-08-09 | 2005-08-09 | Semiconductor test board structure for preventing noise interference |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102788911A (en) * | 2012-09-06 | 2012-11-21 | 电子科技大学 | Heat-sensitive film noise testing method |
| CN102998497A (en) * | 2012-12-11 | 2013-03-27 | 北京确安科技股份有限公司 | Production method of skip type probe card |
| CN103411648A (en) * | 2013-08-12 | 2013-11-27 | 苏州市正步机器制造有限公司 | Anti-interference probe box |
| CN104614658A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | Method for testing high-frequency chip wafers through multi-channel probe card |
| CN111033271A (en) * | 2017-08-11 | 2020-04-17 | 李诺工业股份有限公司 | Testing device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5552563A (en) * | 1995-03-17 | 1996-09-03 | Sharp Microelectronics Technology, Inc. | Shielded low noise multi-lead contact |
| CN1248551C (en) * | 2001-05-30 | 2006-03-29 | 神达电脑股份有限公司 | Circuit board and suppressing method for suppressing electromagnetic wave interference |
| KR100545189B1 (en) * | 2001-11-01 | 2006-01-24 | 주식회사 유림하이테크산업 | Probe card for LCD inspection |
| JP3791689B2 (en) * | 2004-01-09 | 2006-06-28 | 日本電子材料株式会社 | Probe card |
| CN2711898Y (en) * | 2004-07-22 | 2005-07-20 | 美亚国际电子股份有限公司 | High frequency cantilever probe card |
| CN1281104C (en) * | 2004-08-23 | 2006-10-18 | 倚天资讯股份有限公司 | Printed circuit layout method, printed circuit board, and electronic device |
-
2005
- 2005-08-09 CN CNB2005100897997A patent/CN100424514C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102788911A (en) * | 2012-09-06 | 2012-11-21 | 电子科技大学 | Heat-sensitive film noise testing method |
| CN102788911B (en) * | 2012-09-06 | 2015-07-22 | 电子科技大学 | Heat-sensitive film noise testing method |
| CN102998497A (en) * | 2012-12-11 | 2013-03-27 | 北京确安科技股份有限公司 | Production method of skip type probe card |
| CN102998497B (en) * | 2012-12-11 | 2015-12-02 | 北京确安科技股份有限公司 | A kind of production method of skip type probe card |
| CN103411648A (en) * | 2013-08-12 | 2013-11-27 | 苏州市正步机器制造有限公司 | Anti-interference probe box |
| CN104614658A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | Method for testing high-frequency chip wafers through multi-channel probe card |
| CN104614658B (en) * | 2015-01-28 | 2017-04-26 | 山东华翼微电子技术股份有限公司 | Method for testing high-frequency chip wafers through multi-channel probe card |
| CN111033271A (en) * | 2017-08-11 | 2020-04-17 | 李诺工业股份有限公司 | Testing device |
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|---|---|
| CN100424514C (en) | 2008-10-08 |
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Granted publication date: 20081008 Termination date: 20130809 |