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CN1904841A - 向根节点分发输入输出构件错误消息的方法、系统和装置 - Google Patents

向根节点分发输入输出构件错误消息的方法、系统和装置 Download PDF

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CN1904841A
CN1904841A CNA2006101006227A CN200610100622A CN1904841A CN 1904841 A CN1904841 A CN 1904841A CN A2006101006227 A CNA2006101006227 A CN A2006101006227A CN 200610100622 A CN200610100622 A CN 200610100622A CN 1904841 A CN1904841 A CN 1904841A
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里纳托·J·雷西奥
史蒂文·W·亨特
威廉·T·博伊德
史蒂文·M·瑟伯
马德琳·维加
威廉·G·霍兰
道格拉斯·M·弗赖穆斯
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766Error or fault reporting or storing
    • G06F11/0784Routing of error reports, e.g. with a specific transmission path or data flow
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0712Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a virtual computing platform, e.g. logically partitioned systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L2001/0092Error control systems characterised by the topology of the transmission link
    • H04L2001/0093Point-to-multipoint

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Abstract

本发明提供了一种方法、机制和计算机可用介质,用于向多根环境中的适当根节点分发输入/输出构件错误。本发明处理把I/O构件附接到多于一个根节点和每个根可以潜在地与其它根共享被附接到所述I/O的I/O适配器(IOA)资源的情况。另外,本发明提供一种方法、机制和计算机可用介质,通过所述方法、机制和计算机可用介质,可以把在输入/输出构件中检测的错误路由传输到可能被所述错误影响的所有根节点,同时不向未被那些错误影响的根节点报告。具体是,处理使用PCI Express协议来通过I/O构件通信的分布式计算系统。

Description

向根节点分发输入输出构件错误消息的方法、系统和装置
技术领域
本发明总体上涉及一种通过I/O构件在主计算机和输入/输出(I/O)适配器之间的通信。具体地,本发明处理如下情况:I/O构件附接到多于一个根节点,并且每个根可以潜在地与其它根共享附接到所述I/O的I/O适配器(IOA)资源。
背景技术
共享I/O构件的多根配置在过去还没有充分地处理,并且,在I/O构件中检测的错误总体上使得可能正在使用那个构件的所有系统崩溃,这是由于不知道哪个I/O设备被影响以及哪些根节点正在使用那个I/O。
因此,提供一种用于对I/O构件定义哪些错误影响哪些I/O设备、以及那些I/O设备被分配到哪些根节点的机制是有益的。
发明内容
本发明提供了一种方法、装置和计算机可用介质,用于在多根的环境中向适当根节点分发输入/输出构件错误。本发明处理I/O构件附接到多于一个根节点并且每个根可以潜在地与其它根共享被附接到所述I/O构件的I/O适配器资源的情况。另外,本发明提供一种机制和方法,通过该机制和方法,可以把在输入/输出构件中检测的错误路由传输到可能被所述错误影响的所有根节点,同时不向未被那些错误影响的根节点报告。具体是,本发明具体处理使用PCI Express(表述)协议来在I/O构件上通信的分布式计算系统。
附图说明
在所附的权利要求中给出了认为是本发明特性的新颖特征。然而,通过结合附图来在下面详细说明示例性实施例,将最佳地理解本发明本身以及优选的实施方式、另外的目的及其优点。
图1是图解按照本发明的示例性实施例的分布式计算系统的图;
图2是描绘其中可以实施本发明的方面的示例逻辑分区平台的方框图;
图3是按照本发明的示例性实施例的消息请求分组的总体布局;
图4描绘了按照本发明的示例性实施例的可以执行错误相关和路由传输的方法;
图5描绘了按照本发明的示例性实施例的需要把路由表划分为多个级联的路由表的配置;
图6示出了按照本发明的示例性实施例的可以在路由表中找到的路由表条目的示例布局;
图7是描述按照本发明的示例性实施例的路由机制的一层的操作的流程图;以及
图8描述按照本发明的示例性实施例的用于路由表建立处理的高层流程图。
具体实施方式
本发明的方面用于分发I/O构件错误至多根环境中的适当根节点。所处理的是将I/O构件附接到多于一个根节点并且每个根可以潜在地与其它根共享被附接到所述I/O的I/O适配器资源的情况。另外,提供一种机制,通过该机制,可以把在输入/输出构件中检测的错误路由传输到可能被所述错误影响的所有根节点,同时不向未被那些错误影响的根节点报告。具体是,处理使用PCI Express协议来通过I/O构件通信的分布式计算系统。
现在参见附图,具体参见图1,图解了按照本发明的示例性实施例的分布式计算系统。在图1中所示的分布式计算系统100采用了一个或多个根复形(complex)108、118、128、138和139的形式,所述一个或多个根复形108、118、128、138和139通过I/O链路110、120、130、142和143而附接到I/O构件144,并且附接到根节点(RN)160、161、162和163的存储器控制器104、114、124和134。I/O构件144通过链路151、152、153、154、155、156、157和158而附接到I/O适配器145、146、147、148、149和150。I/O适配器145、146、147、148、149和150可以是诸如在145、146和149中的单个功能I/O适配器、或诸如在147、148和150中的多功能I/O适配器。而且,I/O适配器145、146、147、148、149和150可以如在145、146、147和148中经由单个链路而连接到I/O构件144、或如在149和150中通过冗余的多个链路而连接到I/O构件144。
根复形108、118、128、138和139是根节点160、161、162和163的一部分。可以如在根节点163中那样每个根节点存在多于一个根复形。除了根复形之外,每个根节点包括:一个或多个中央处理单元(CPU)101、102、111、112、121、122、131和132;存储器103、113、123和133;以及存储器控制器104、114、124和134,其连接CPU 101、102、111、112、121、122、131和132、存储器103、113、123和133、以及I/O根复形108、118、128、138和139,并且执行诸如处理存储器的相干业务(coherency traffic)的功能。
根节点160和161可以通过它们的存储器控制器104和114而在连接159连接在一起,以形成一个相干域,可以作为单个的对称多处理(SMP)系统,或可以是具有分离的相干域的独立节点,如在根节点162和163中。
配置管理器164可以分离地附接到I/O构件144,或可以是根节点160、161、162和163的一个或多个的一部分。配置管理器164配置I/O构件144的共享资源,并且向根节点160、161、162和163分配资源。
可以使用各种商业可得的计算机系统来实现分布式计算系统100。例如,可以使用从国际商业机器公司可得的IBM eServerTM iSeries Model(模型)840系统来实现分布式计算系统100。这样的系统可以使用也可以从国际商业机器公司获得的OS/400操作系统来支持逻辑分区。
本领域内的普通技术人员可以明白,图1中所描绘的硬件可以改变。例如,除了所描绘的硬件之外,或替代所描绘的硬件,也可以使用诸如光盘驱动器等的其它外围设备。所描绘的例子不意味着暗示对于本发明的构架限制。
现在参见图2,描绘可以实现本发明的示例逻辑分区平台的方框图。在逻辑分区平台200中的硬件可以被实现为例如图1中的分布式计算系统100。逻辑分区平台200包括分区硬件230、操作系统202、204、206和208以及分区管理固件210。操作系统202、204、206和208可以是单个操作系统的多个拷贝、或者同时运行在逻辑分区平台200上的多个异种操作系统。可以使用OS/400来实现这些操作系统,它们被设计来与诸如系统管理程序(Hypervisor)之类的分区管理固件相接口。OS/400仅仅被用作这些示例性实施例中的示例。也可以根据具体实施而使用诸如AIX和Linux之类的其它类型的操作系统。
操作系统202、204、206和208位于分区203、205、207和209中。Hypervisor软件是可以用于实施分区管理固件210的软件的示例,并且从国际商业机器公司可获得。固件是在存储芯片中存储的“软件”,所述存储芯片在无电源情况下保持其内容,诸如只读存储器(ROM)、可编程ROM(PROM)、可擦除可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)和非易失性随机存取存储器(NVRAM)。
另外,分区203、205、207和209也包括分区固件211、213、215和217。可以使用初始引导代码、IEEE-1275标准开放固件、和可以从国际商业机器公司获得的运行时间抽象软件(RTAS)来实现分区固件211、213、215和217。当例示(instantiate)分区203、205、207和209时,引导代码的拷贝被平台固件210载入分区203、205、207和209。其后,控制被传送到引导代码,所述引导代码然后载入开放固件和运行时间抽象软件。与分区203、205、207和209相关联、或被分配到分区203、205、207和209的处理器然后被分派到分区的存储器,以执行分区固件211、213、215和217。
分区硬件230包括:多个处理器232、234、236和238;多个系统存储单元240、242、244和246;多个I/O适配器248、250、252、254、256、258、260和262;存储单元270;非易失性随机存取存储器298。处理器232、234、236和238、存储单元240、242、244和246、非易失性随机存取存储器298和I/O适配器248、250、252、254、256、258、260和262的每个或其一部分可被分配到逻辑分区平台200内的多个分区之一,其中每个对应于操作系统202、204、206和208之一。
分区管理固件210执行分区203、205、207和209的多个功能和服务,以创建和强制(enforce)逻辑分区平台200的分区。分区管理固件210是与底层硬件相同的固件实现虚拟机。因此,分区管理固件210通过虚拟化逻辑分区平台200的硬件资源而允许同时执行独立的操作系统映像202、204、206和208。
服务处理器290可以用于提供各种服务,诸如处理在分区203、205、207和209中的平台错误。这些服务也可以作为服务代理器,用于向诸如国际商业机器公司之类的卖方回告错误。可以通过诸如硬件管理控制台280之类的硬件管理控制台来控制分区203、205、207和209的操作。硬件管理控制台280是分离的分布式计算系统,系统管理员可以从其执行各种功能,包括向不同的分区重新分配资源。可以被控制的操作包括例如相对于被分配到分区的部件而配置该分区,而不论所述分区正在运行与否。
在逻辑分区(LPAR)环境中,不允许在一个分区中的资源或程序影响在另一个分区中的操作。而且,有益的是,资源的分配需要细密进行(fine-grained)。例如,经常不可接受的是,向同一分区分配在特定PCI主桥(PHB)下的所有I/O适配器,因为这将限制系统的可配置性,包括动态地在分区之间移动资源的能力。
因此,在将I/O适配器连接到I/O总线的桥中需要一些功能,以便能够向分离的分区分配资源,诸如个别的I/O适配器或部分I/O适配器;并且,同时,防止所分配的资源通过诸如获得对其它分区的资源的访问而影响其它的分区。
现在转向图3,描述了按照本发明的示例性实施例的消息请求分组的总体布局。在消息请求分组300中,关键字段是请求方ID(标识符)301和消息代码302。在消息请求分组300中特别有意义的是消息代码302,它可以表示已经由被请求方ID 301所代表的实体所识别的错误。请求方ID 301提供了错误的检测器的指示,但是不需要是可能被错误影响的实体。因此,需要一种方式来对丢失的(missing)信息相关。
图4描述了按照本发明的示例性实施例的一种可以执行错误相关和路由传输的方法。I/O构件401包括根端口402、403、404、405和406以及辅助端口407、408、409、410、411、412、413和414。进入的事务418包含由错误检测逻辑415检测的错误,用于错误检测的控制逻辑然后产生消息请求分组,诸如图3的消息请求分组300,它向其中置入请求方ID 416。请求方ID 416由配置代码在构件初始化时设置。作为本发明的示例方面,请求方ID416在PCI Express的情况下可以是总线编号、设备编号和设备的功能编号。消息请求分组然后在连接419处通过I/O构件401,直到它达到路由逻辑422,路由逻辑422位于I/O构件401中可以访问所有根端口402、403、404、405和406的位置。此处,在消息请求分组中的请求方ID 416用于访问错误路由表417,并且在路由表417中的信息用于对于被影响的每个根端口403和405产生一个错误分组420和421。路由表417可以是任何类型的存储信息的数据结构。
图5描述了按照本发明的示例性实施例的、需要把路由表划分为多个级联的路由表的配置。在这种情况下,I/O构件501具有多于一个开关或桥515和517,其与根端口502、503、504、505和506相接口。如果存在多于一个开关或桥,则诸如图4的路由表417之类的路由表需要被划分为路由表516和518。在路由表516和518之间的连接经由中间链路526。
另外,可以有辅助桥或开关519,其可以包含路由表520。在这种配置中,错误检测器521产生具有在请求方ID中的错误检测器的ID的错误分组522。路由表520使用在错误分组522中的这个请求方ID来查找路由,然后该路由如在连接523中所示地路由传输错误分组522。同样,路由表518确定错误分组522的正确路由是经由连接524和525而到根端口505和506,并且到开关或桥515。当经由中间链路526而在开关或桥515接收到错误分组522时,路由表516确定应当经由连接527将错误分组522路由传输到根端口503。
图6示出了按照本发明的示例性实施例的、可以在诸如图4的路由表417之类的路由表中找到的路由表条目的示例布局。路由表条目600包括请求方ID 601,所述请求方ID 601可以是消息请求分组上的一个可能的请求方ID并对应于图4的请求方ID 416,并且在图4的错误检测器415或图5的错误检测器521中被检测。而且,在路由表条目600中有根端口比特阵列602,其中,每个比特对应于错误可能需要路由传输至的可能的根端口,并且,在路由表条目600中还有中间端口比特阵列603,其中,每个比特对应于错误可能需要路由传输至的可能的中间端口。
图7是描述按照本发明的示例性实施例的通过路由机制的一层的操作的流程图。当操作开始时,由路由机制接收错误消息(步骤702)。然后,在路由表中搜索错误消息中的请求方ID(步骤704)。本领域内的技术人员可以认识到,可以以许多方式来执行路由表中正确条目的搜索。或者,路由表可以是任何类型的存储信息的数据结构。例如,内容可寻址存储器、对于等于错误消息中的请求方ID的表中的请求方ID字段的值的表的扫描、作为在路由表中的索引的错误消息中的请求方ID的使用,等等。在找到正确的请求方ID条目时,对于相关联的根端口比特阵列检查置位的任何比特(步骤706)。如果在所述根端口比特阵列中置位了任何比特,那么,对于置位的每个比特,使用在原始消息中的请求方ID来产生错误消息,并且通过搜索路由表而确定哪个或哪些端口与错误消息相关联,并且把每个错误消息路由传输到与根端口比特阵列中的所述比特的位置对应的一个或多个根端口(步骤708)。
然后,对于中间端口比特阵列检查任何被置位的比特(步骤710)。如果在根端口比特阵列中没有被置位的比特,则步骤706也进行到步骤710。如果在中间根端口比特阵列中置位了任何比特,则对于每个被置位的比特,使用在原始消息中的请求方ID来产生错误消息,并且通过搜索路由表而确定哪个或哪些端口与错误消息相关联,并且把每个错误消息路由传输到与在中间端口比特阵列中的所述比特的位置对应的一个或多个中间端口(步骤712),其后操作结束。如果在中间端口比特阵列中没有被置位的比特,则步骤710也进行到操作终止。
图8描述了按照本发明的示例性实施例的路由表建立处理的高层流程图。当操作开始时,I/O构件配置代码探测或“游动(walk)”I/O构件,记住路由表在何处与I/O构件请求方ID和末端请求方ID相关联(步骤802)。作为示例,PCI Express的请求方ID可以是总线编号、设备编号或功能编号。即,请求方ID“树(tree)”被配置软件记住。这个树确定哪些错误将潜在地影响哪些其它的ID。即,在处理给定ID的错误中,软件需要假定这个错误会影响在那个ID下的树中的所有其它ID,因此,如果对于影响多个ID的ID发生了错误,并且该多个ID被分配到多个根节点,则在本发明中所述的机制需要复制那些错误消息,并且将它们提供到所有被影响的根节点。
当I/O构件配置代码探测或“游动”I/O构件完成时,I/O构件被配置,并且向多个根节点分配多个末端(步骤804)。分配表示根节点在末端的控制下,包括任何错误恢复。用于确定分配的方法在本发明的范围之外。
然后,根据哪些错误将影响哪些末端请求方ID和哪些末端请求方ID被分配到哪些根节点,而建立路由表(步骤806)。所述路由表基于在步骤802和804中保留的信息。所述路由表将包含树中在其下的每个I/O构件请求方ID的条目,并且这些条目的每个也指定那个特定请求方ID上的错误影响哪些根节点。如何访问所述表以把来自这个步骤的信息置于它们之中在本发明的范围之外,但是本领域内的技术人员可以明白,用于设置所述构件的配置机制可以被扩展以允许这样的访问。
本领域内的技术人员可以明白,这种机制和方法替换了被定义为把错误消息向上路由传输到单个根端口的PCI Express机制和方法。本发明中公开的所述机制和方法因此允许另外控制方向以及复制消息,以路由传输到可能被所述错误影响的多个根端口。
本发明可以采取完全硬件的实施例、或包含硬件和软件元件二者的实施例的形式。在优选实施例中,以硬件和软件来实现本发明,所述硬件和软件包括但不限于固件、驻留软件、微代码等。
而且,本发明的方面可以采取从计算机可用或计算机可读介质可访问的计算机程序产品的形式,所述计算机可用或计算机可读介质提供由计算机或任何指令执行系统使用或与计算机或任何指令执行系统相结合的程序代码。对于本说明的目的,计算机可用或计算机可读介质可以是能够包含、存储、通信、传播或传送由指令执行系统、装置或设备使用或与其相结合的程序的任何装置。
所述介质可以是电、磁、光、电磁、红外或半导体系统(或装置或设备)或传播介质。计算机可读介质的示例包括半导体或固态存储器、磁带、可移动计算机盘、随机存取存储器(RAM)、只读存储器(ROM)、刚性磁盘和光盘。光盘的当前示例包括致密盘——只读存储器(CD-ROM)、致密盘——读/写(CD-R/W)和DVD。
适合于存储和/或执行程序代码的数据处理系统将包括至少一个处理器,所述处理器直接地或通过系统总线而间接地连接到存储器元件。所述存储器元件可以包括在程序代码的实际执行期间使用的本地存储器、大容量存储器和高速缓冲存储器,它们提供至少一些程序代码的临时存储,以便降低在执行期间必须从大容量存储器提取代码的次数。
输入/输出或I/O设备(包括但不限于键盘、显示器、指示设备等)可以直接地或通过介入的I/O控制器而连接到系统。
网络适配器也可以连接到系统,以使得数据处理系统能够变为通过介入专用或公用网络而连接到其它的数据处理系统或远程打印机或存储设备。调制解调器、电缆调制解调器和以太网卡仅仅是一些当前可用类型的网络适配器。
本发明的描述已经被给出以用于图解和描述的目的,并且不意欲以所公开的形式穷尽或限于本发明。许多修改和改变对于本领域内的普通技术人员是显而易见的。所述实施例被选择和描述以便最佳地说明本发明的原理、实际应用,并且使得本领域内的其它普通技术人员能够针对带有适合于所考虑的具体使用的各种修改的各种实施例而理解本发明。

Claims (33)

1.一种计算机实施的方法,用于在多根环境中向根节点分发输入/输出构件错误,所述计算机实施的方法包括:
接收在输入/输出构件中的错误消息,其中,所述错误消息包含请求方标识符;
从数据结构提取与请求方标识符相关联的数据;
确定是否所述数据指示所设置的一个或多个条件;
响应于所设置的一个或多个条件,产生针对每个所设置的条件的根端口错误消息;
通过使用所述数据结构来确定与所述一个或多个根端口错误消息相关联的适当端口;以及
把所述一个或多个根端口错误消息路由传输到与每个根端口错误消息相关联的适当端口,其中,输入/输出构件错误适当时被进一步路由传输。
2.按照权利要求1的计算机实施的方法,其中,所述适当端口是一个或多个根端口。
3.按照权利要求1的计算机实施的方法,其中,所述适当端口是一个或多个中间端口。
4.按照权利要求1的计算机实施的方法,其中,所述数据是至少一个比特阵列。
5.按照权利要求4的计算机实施的方法,其中,所设置的条件是在与所述至少一个比特阵列相关联的多个比特内的至少一个比特置位。
6.按照权利要求4的计算机实施的方法,其中,所述根端口与在所述至少一个比特阵列中的比特位置对应。
7.按照权利要求4的计算机实施的方法,其中,所述至少一个比特阵列是根端口比特阵列。
8.按照权利要求4的计算机实施的方法,其中,所述至少一个比特阵列是中间端口比特阵列。
9.按照权利要求1的计算机实施的方法,其中,所述根端口错误消息包括所述请求方标识符。
10.按照权利要求1的计算机实施的方法,其中,所述数据结构是路由表。
11.按照权利要求10的计算机实施的方法,还包括:
探测所述输入/输出构件;
存储在多个路由表和多个请求方标识符之间的关系;
向与所述多个请求方标识符相关联的多个根节点分配多个末端;以及
根据将影响在所述多个请求方标识符中的每个请求方标识符的多个错误的每个,来建立错误路由表,以形成所述路由表。
12.一种数据处理系统,包括:
总线系统;
通信系统,连接到所述总线系统;
存储器,连接到所述总线系统,其中,所述存储器包括一组指令;以及
处理单元,连接到所述总线系统,其中,所述处理单元执行所述组的指令,以接收在输入/输出构件中的错误消息,其中,所述错误消息包含请求方标识符;从数据结构提取与所述请求方标识符相关联的数据;确定是否所述数据指示所设置的一个或多个条件;响应于一个或多个所设置的条件而产生针对每个所设置的条件的根端口错误消息;通过使用所述数据结构而确定与所述一个或多个根端口错误消息相关联的适当端口;以及把所述一个或多个根端口错误消息路由传输到与每个根端口错误消息相关联的适当端口,其中,输入/输出构件错误适当时被进一步路由传输。
13.按照权利要求12的数据处理系统,其中,所述适当端口是一个或多个根端口。
14.按照权利要求12的数据处理系统,其中,所述适当端口是一个或多个中间端口。
15.按照权利要求12的数据处理系统,其中,所述数据是至少一个比特阵列。
16.按照权利要求15的数据处理系统,其中,所设置的条件是在与所述至少一个比特阵列相关联的多个比特内的至少一个比特置位。
17.按照权利要求15的数据处理系统,其中,所述根端口与在所述至少一个比特阵列中的比特位置对应。
18.按照权利要求15的数据处理系统,其中,所述至少一个比特阵列是根端口比特阵列。
19.按照权利要求15的数据处理系统,其中,所述至少一个比特阵列是中间端口比特阵列。
20.按照权利要求12的数据处理系统,其中,所述根端口错误消息包括所述请求方标识符。
21.按照权利要求12的数据处理系统,其中,所述数据结构是路由表。
22.按照权利要求21的数据处理系统,还包括一组指令,用于:探测所述输入/输出构件;存储在多个路由表和多个请求方标识符之间的关系;向与所述多个请求方标识符相关联的多个根节点分配多个末端;以及根据将影响在所述多个请求方标识符中的每个请求方标识符的多个错误的每个,来建立错误路由表,以形成所述路由表。
23.一种用于在多根环境中向根节点分发输入/输出构件错误的装置,所述装置包括:
接收装置,用于接收在输入/输出构件中的错误消息,其中,所述错误消息包含请求方标识符;
提取装置,用于从数据结构提取与所述请求方标识符相关联的数据;
确定装置,用于确定是否所述数据指示所设置的一个或多个条件;
产生装置,用于响应于所设置的一个或多个条件而产生针对每个所设置的条件的根端口错误消息;
确定装置,用于通过使用所述数据结构来确定与所述一个或多个根端口错误消息相关联的适当端口;以及
路由传输装置,用于把所述一个或多个根端口错误消息路由传输到与每个根端口错误消息相关联的适当端口,其中,输入/输出构件错误适当时被进一步路由传输。
24.按照权利要求23的装置,其中,所述适当端口是一个或多个根端口。
25.按照权利要求23的装置,其中,所述适当端口是一个或多个中间端口。
26.按照权利要求23的装置,其中,所述数据是至少一个比特阵列。
27.按照权利要求26的装置,其中,所设置的条件是在与所述至少一个比特阵列相关联的多个比特内的至少一个比特置位。
28.按照权利要求26的装置,其中,所述根端口与在所述至少一个比特阵列中的比特位置对应。
29.按照权利要求26的装置,其中,所述至少一个比特阵列是根端口比特阵列。
30.按照权利要求26的装置,其中,所述至少一个比特阵列是中间端口比特阵列。
31.按照权利要求23的装置,其中,所述根端口错误消息包括所述请求方标识符。
32.按照权利要求23的装置,其中,所述数据结构是路由表。
33.按照权利要求32的装置,还包括:
探测装置,用于探测所述输入/输出构件;
存储装置,用于存储在多个路由表和多个请求方标识符之间的关系;
分配装置,用于向与所述多个请求方标识符相关联的多个根节点分配多个末端;以及
建立装置,用于根据将影响在所述多个请求方标识符中的每个请求方标识符的多个错误的每个,来建立错误路由表,以形成所述路由表。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012164418A1 (en) * 2011-06-01 2012-12-06 International Business Machines Corporation Facilitating processing in a communications environment using stop signaling
US8644136B2 (en) 2011-06-01 2014-02-04 International Business Machines Corporation Sideband error signaling

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7492723B2 (en) * 2005-07-07 2009-02-17 International Business Machines Corporation Mechanism to virtualize all address spaces in shared I/O fabrics
US7496045B2 (en) * 2005-07-28 2009-02-24 International Business Machines Corporation Broadcast of shared I/O fabric error messages in a multi-host environment to all affected root nodes
US7363404B2 (en) * 2005-10-27 2008-04-22 International Business Machines Corporation Creation and management of destination ID routing structures in multi-host PCI topologies
US7430630B2 (en) * 2005-10-27 2008-09-30 International Business Machines Corporation Routing mechanism in PCI multi-host topologies using destination ID field
US7474623B2 (en) * 2005-10-27 2009-01-06 International Business Machines Corporation Method of routing I/O adapter error messages in a multi-host environment
US7395367B2 (en) * 2005-10-27 2008-07-01 International Business Machines Corporation Method using a master node to control I/O fabric configuration in a multi-host environment
US7631050B2 (en) * 2005-10-27 2009-12-08 International Business Machines Corporation Method for confirming identity of a master node selected to control I/O fabric configuration in a multi-host environment
US20070171833A1 (en) * 2005-11-21 2007-07-26 Sukhbinder Singh Socket for use in a networked based computing system having primary and secondary routing layers
US20070136458A1 (en) * 2005-12-12 2007-06-14 Boyd William T Creation and management of ATPT in switches of multi-host PCI topologies
US20070165596A1 (en) * 2006-01-18 2007-07-19 Boyd William T Creation and management of routing table for PCI bus address based routing with integrated DID
US7707465B2 (en) * 2006-01-26 2010-04-27 International Business Machines Corporation Routing of shared I/O fabric error messages in a multi-host environment to a master control root node
US7380046B2 (en) * 2006-02-07 2008-05-27 International Business Machines Corporation Method, apparatus, and computer program product for routing packets utilizing a unique identifier, included within a standard address, that identifies the destination host computer system
US7484029B2 (en) * 2006-02-09 2009-01-27 International Business Machines Corporation Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters
US20080137676A1 (en) * 2006-12-06 2008-06-12 William T Boyd Bus/device/function translation within and routing of communications packets in a pci switched-fabric in a multi-host environment environment utilizing a root switch
US7571273B2 (en) * 2006-12-06 2009-08-04 International Business Machines Corporation Bus/device/function translation within and routing of communications packets in a PCI switched-fabric in a multi-host environment utilizing multiple root switches
US8042004B2 (en) * 2008-02-25 2011-10-18 International Business Machines Corporation Diagnosing communications between computer systems
US7831710B2 (en) * 2008-02-25 2010-11-09 International Business Machines Corporation Communication of offline status between computer systems
US8423698B2 (en) * 2008-04-02 2013-04-16 Hewlett-Packard Development Company, L.P. Conversion of resets sent to a shared device
JP5281942B2 (ja) 2009-03-26 2013-09-04 株式会社日立製作所 計算機およびその障害処理方法
US8645606B2 (en) 2010-06-23 2014-02-04 International Business Machines Corporation Upbound input/output expansion request and response processing in a PCIe architecture
US8615622B2 (en) 2010-06-23 2013-12-24 International Business Machines Corporation Non-standard I/O adapters in a standardized I/O architecture
US8645767B2 (en) 2010-06-23 2014-02-04 International Business Machines Corporation Scalable I/O adapter function level error detection, isolation, and reporting
US8918573B2 (en) 2010-06-23 2014-12-23 International Business Machines Corporation Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIe) environment
US8745292B2 (en) 2010-06-23 2014-06-03 International Business Machines Corporation System and method for routing I/O expansion requests and responses in a PCIE architecture
US8458510B2 (en) * 2010-08-12 2013-06-04 International Business Machines Corporation LPAR creation and repair for automated error recovery
US9086965B2 (en) * 2011-12-15 2015-07-21 International Business Machines Corporation PCI express error handling and recovery action controls
US9026865B2 (en) * 2012-06-11 2015-05-05 Unisys Corporation Software handling of hardware error handling in hypervisor-based systems
JP5933356B2 (ja) * 2012-06-12 2016-06-08 ルネサスエレクトロニクス株式会社 コンピュータシステム
US8606973B1 (en) 2012-07-05 2013-12-10 International Business Machines Corporation Managing monitored conditions in adaptors in a multi-adaptor system
US8990642B2 (en) * 2013-02-22 2015-03-24 International Business Machines Corporation Managing error logs in a distributed network fabric
US9218310B2 (en) * 2013-03-15 2015-12-22 Google Inc. Shared input/output (I/O) unit
US10972375B2 (en) 2016-01-27 2021-04-06 Oracle International Corporation System and method of reserving a specific queue pair number for proprietary management traffic in a high-performance computing environment
US10469621B2 (en) 2016-01-27 2019-11-05 Oracle International Corporation System and method of host-side configuration of a host channel adapter (HCA) in a high-performance computing environment
US11018947B2 (en) 2016-01-27 2021-05-25 Oracle International Corporation System and method for supporting on-demand setup of local host channel adapter port partition membership in a high-performance computing environment
US11336509B2 (en) * 2018-10-31 2022-05-17 EMC IP Holding Company LLC Detecting single points of failure on a storage system

Family Cites Families (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5257353A (en) * 1986-07-18 1993-10-26 Intel Corporation I/O control system having a plurality of access enabling bits for controlling access to selective parts of an I/O device
US5367695A (en) * 1991-09-27 1994-11-22 Sun Microsystems, Inc. Bus-to-bus interface for preventing data incoherence in a multiple processor computer system
US5392328A (en) * 1993-02-04 1995-02-21 Bell Communications Research, Inc. System and method for automatically detecting root causes of switching connection failures in a telephone network
US5960213A (en) * 1995-12-18 1999-09-28 3D Labs Inc. Ltd Dynamically reconfigurable multi-function PCI adapter device
US6557121B1 (en) * 1997-03-31 2003-04-29 International Business Machines Corporation Method and system for fault isolation for PCI bus errors
US5968189A (en) * 1997-04-08 1999-10-19 International Business Machines Corporation System of reporting errors by a hardware element of a distributed computer system
US6061753A (en) * 1998-01-27 2000-05-09 Emc Corporation Apparatus and method of accessing target devices across a bus utilizing initiator identifiers
US6769021B1 (en) * 1999-09-15 2004-07-27 Adaptec, Inc. Methods for partitioning end nodes in a network fabric
US6611883B1 (en) 2000-11-16 2003-08-26 Sun Microsystems, Inc. Method and apparatus for implementing PCI DMA speculative prefetching in a message passing queue oriented bus system
US6662251B2 (en) * 2001-03-26 2003-12-09 International Business Machines Corporation Selective targeting of transactions to devices on a shared bus
US7363389B2 (en) 2001-03-29 2008-04-22 Intel Corporation Apparatus and method for enhanced channel adapter performance through implementation of a completion queue engine and address translation engine
US6691184B2 (en) 2001-04-30 2004-02-10 Lsi Logic Corporation System and method employing a dynamic logical identifier
US7171458B2 (en) * 2001-06-12 2007-01-30 International Business Machines Corporation Apparatus and method for managing configuration of computer systems on a computer network
US6775750B2 (en) * 2001-06-29 2004-08-10 Texas Instruments Incorporated System protection map
US7209453B1 (en) * 2001-12-14 2007-04-24 Applied Micro Circuits Corporation System and method for tolerating control link faults in a packet communications switch fabric
US20040025166A1 (en) 2002-02-02 2004-02-05 International Business Machines Corporation Server computer and a method for accessing resources from virtual machines of a server computer via a fibre channel
US6907510B2 (en) * 2002-04-01 2005-06-14 Intel Corporation Mapping of interconnect configuration space
US7036122B2 (en) * 2002-04-01 2006-04-25 Intel Corporation Device virtualization and assignment of interconnect devices
US20030221030A1 (en) * 2002-05-24 2003-11-27 Timothy A. Pontius Access control bus system
US7194538B1 (en) * 2002-06-04 2007-03-20 Veritas Operating Corporation Storage area network (SAN) management system for discovering SAN components using a SAN management server
US7251704B2 (en) * 2002-08-23 2007-07-31 Intel Corporation Store and forward switch device, system and method
US7120711B2 (en) * 2002-12-19 2006-10-10 Intel Corporation System and method for communicating over intra-hierarchy and inter-hierarchy links
US7174413B2 (en) * 2003-01-21 2007-02-06 Nextio Inc. Switching apparatus and method for providing shared I/O within a load-store fabric
US7219183B2 (en) * 2003-01-21 2007-05-15 Nextio, Inc. Switching apparatus and method for providing shared I/O within a load-store fabric
US7953074B2 (en) * 2003-01-21 2011-05-31 Emulex Design And Manufacturing Corporation Apparatus and method for port polarity initialization in a shared I/O device
US7457906B2 (en) * 2003-01-21 2008-11-25 Nextio, Inc. Method and apparatus for shared I/O in a load/store fabric
US7103064B2 (en) 2003-01-21 2006-09-05 Nextio Inc. Method and apparatus for shared I/O in a load/store fabric
US7188209B2 (en) * 2003-04-18 2007-03-06 Nextio, Inc. Apparatus and method for sharing I/O endpoints within a load store fabric by encapsulation of domain information in transaction layer packets
US20040210754A1 (en) * 2003-04-16 2004-10-21 Barron Dwight L. Shared security transform device, system and methods
US7134052B2 (en) * 2003-05-15 2006-11-07 International Business Machines Corporation Autonomic recovery from hardware errors in an input/output fabric
US7096305B2 (en) * 2003-05-15 2006-08-22 Broadcom Corporation Peripheral bus switch having virtual peripheral bus and configurable host bridge
US7380018B2 (en) * 2003-05-15 2008-05-27 Broadcom Corporation Peripheral bus transaction routing using primary and node ID routing information
US20050044301A1 (en) * 2003-08-20 2005-02-24 Vasilevsky Alexander David Method and apparatus for providing virtual computing services
US8776050B2 (en) 2003-08-20 2014-07-08 Oracle International Corporation Distributed virtual machine monitor for managing multiple virtual resources across multiple physical nodes
US7437738B2 (en) * 2003-11-12 2008-10-14 Intel Corporation Method, system, and program for interfacing with a network adaptor supporting a plurality of devices
US20050228531A1 (en) * 2004-03-31 2005-10-13 Genovker Victoria V Advanced switching fabric discovery protocol
US20050270988A1 (en) * 2004-06-04 2005-12-08 Dehaemer Eric Mechanism of dynamic upstream port selection in a PCI express switch
US7457871B2 (en) * 2004-10-07 2008-11-25 International Business Machines Corporation System, method and program to identify failed components in storage area network
US8285907B2 (en) * 2004-12-10 2012-10-09 Intel Corporation Packet processing in switched fabric networks
US20060174094A1 (en) * 2005-02-02 2006-08-03 Bryan Lloyd Systems and methods for providing complementary operands to an ALU
US7886086B2 (en) * 2005-02-03 2011-02-08 International Business Machines Corporation Method and apparatus for restricting input/output device peer-to-peer operations in a data processing system to improve reliability, availability, and serviceability
US20060179265A1 (en) * 2005-02-08 2006-08-10 Flood Rachel M Systems and methods for executing x-form instructions
US7360058B2 (en) * 2005-02-09 2008-04-15 International Business Machines Corporation System and method for generating effective address
US7380066B2 (en) * 2005-02-10 2008-05-27 International Business Machines Corporation Store stream prefetching in a microprocessor
US7350029B2 (en) * 2005-02-10 2008-03-25 International Business Machines Corporation Data stream prefetching in a microprocessor
US20060184769A1 (en) * 2005-02-11 2006-08-17 International Business Machines Corporation Localized generation of global flush requests while guaranteeing forward progress of a processor
US7395414B2 (en) * 2005-02-11 2008-07-01 International Business Machines Corporation Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
US7631308B2 (en) * 2005-02-11 2009-12-08 International Business Machines Corporation Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
US7254697B2 (en) * 2005-02-11 2007-08-07 International Business Machines Corporation Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
US20060184770A1 (en) * 2005-02-12 2006-08-17 International Business Machines Corporation Method of implementing precise, localized hardware-error workarounds under centralized control
US20060195663A1 (en) * 2005-02-25 2006-08-31 International Business Machines Corporation Virtualized I/O adapter for a multi-processor data processing system
US7870301B2 (en) * 2005-02-25 2011-01-11 International Business Machines Corporation System and method for modification of virtual adapter resources in a logically partitioned data processing system
US7543084B2 (en) * 2005-02-25 2009-06-02 International Business Machines Corporation Method for destroying virtual resources in a logically partitioned data processing system
US7398337B2 (en) 2005-02-25 2008-07-08 International Business Machines Corporation Association of host translations that are associated to an access control level on a PCI bridge that supports virtualization
US20060195617A1 (en) * 2005-02-25 2006-08-31 International Business Machines Corporation Method and system for native virtualization on a partially trusted adapter using adapter bus, device and function number for identification
US7386637B2 (en) * 2005-02-25 2008-06-10 International Business Machines Corporation System, method, and computer program product for a fully trusted adapter validation of incoming memory mapped I/O operations on a physical adapter that supports virtual adapters or virtual resources
US7493425B2 (en) * 2005-02-25 2009-02-17 International Business Machines Corporation Method, system and program product for differentiating between virtual hosts on bus transactions and associating allowable memory access for an input/output adapter that supports virtualization
US7496790B2 (en) * 2005-02-25 2009-02-24 International Business Machines Corporation Method, apparatus, and computer program product for coordinating error reporting and reset utilizing an I/O adapter that supports virtualization
US20060212870A1 (en) * 2005-02-25 2006-09-21 International Business Machines Corporation Association of memory access through protection attributes that are associated to an access control level on a PCI adapter that supports virtualization
US20060195848A1 (en) * 2005-02-25 2006-08-31 International Business Machines Corporation System and method of virtual resource modification on a physical adapter that supports virtual resources
US7260664B2 (en) * 2005-02-25 2007-08-21 International Business Machines Corporation Interrupt mechanism on an IO adapter that supports virtualization
US7376770B2 (en) * 2005-02-25 2008-05-20 International Business Machines Corporation System and method for virtual adapter resource allocation matrix that defines the amount of resources of a physical I/O adapter
US7480742B2 (en) * 2005-02-25 2009-01-20 International Business Machines Corporation Method for virtual adapter destruction on a physical adapter that supports virtual adapters
US7685335B2 (en) * 2005-02-25 2010-03-23 International Business Machines Corporation Virtualized fibre channel adapter for a multi-processor data processing system
US8176204B2 (en) * 2005-03-11 2012-05-08 Hewlett-Packard Development Company, L.P. System and method for multi-host sharing of a single-host device
US8656488B2 (en) * 2005-03-11 2014-02-18 Trend Micro Incorporated Method and apparatus for securing a computer network by multi-layer protocol scanning
US7656789B2 (en) 2005-03-29 2010-02-02 International Business Machines Corporation Method, system and storage medium for redundant input/output access
US7565463B2 (en) * 2005-04-22 2009-07-21 Sun Microsystems, Inc. Scalable routing and addressing
US8223745B2 (en) 2005-04-22 2012-07-17 Oracle America, Inc. Adding packet routing information without ECRC recalculation
US7613864B2 (en) * 2005-04-22 2009-11-03 Sun Microsystems, Inc. Device sharing
US7293129B2 (en) * 2005-04-22 2007-11-06 Sun Microsystems, Inc. Flexible routing and addressing
US7478178B2 (en) * 2005-04-22 2009-01-13 Sun Microsystems, Inc. Virtualization for device sharing
US20060271718A1 (en) 2005-05-27 2006-11-30 Diplacido Bruno Jr Method of preventing error propagation in a PCI / PCI-X / PCI express link
US7409589B2 (en) * 2005-05-27 2008-08-05 International Business Machines Corporation Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor
US7492723B2 (en) * 2005-07-07 2009-02-17 International Business Machines Corporation Mechanism to virtualize all address spaces in shared I/O fabrics
US7496045B2 (en) 2005-07-28 2009-02-24 International Business Machines Corporation Broadcast of shared I/O fabric error messages in a multi-host environment to all affected root nodes
US7631050B2 (en) * 2005-10-27 2009-12-08 International Business Machines Corporation Method for confirming identity of a master node selected to control I/O fabric configuration in a multi-host environment
US7363404B2 (en) * 2005-10-27 2008-04-22 International Business Machines Corporation Creation and management of destination ID routing structures in multi-host PCI topologies
US7430630B2 (en) * 2005-10-27 2008-09-30 International Business Machines Corporation Routing mechanism in PCI multi-host topologies using destination ID field
US7474623B2 (en) * 2005-10-27 2009-01-06 International Business Machines Corporation Method of routing I/O adapter error messages in a multi-host environment
US7395367B2 (en) * 2005-10-27 2008-07-01 International Business Machines Corporation Method using a master node to control I/O fabric configuration in a multi-host environment
US20070136458A1 (en) * 2005-12-12 2007-06-14 Boyd William T Creation and management of ATPT in switches of multi-host PCI topologies
US20070165596A1 (en) 2006-01-18 2007-07-19 Boyd William T Creation and management of routing table for PCI bus address based routing with integrated DID
US7707465B2 (en) 2006-01-26 2010-04-27 International Business Machines Corporation Routing of shared I/O fabric error messages in a multi-host environment to a master control root node
US7380046B2 (en) 2006-02-07 2008-05-27 International Business Machines Corporation Method, apparatus, and computer program product for routing packets utilizing a unique identifier, included within a standard address, that identifies the destination host computer system
US7484029B2 (en) 2006-02-09 2009-01-27 International Business Machines Corporation Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters
US7571273B2 (en) 2006-12-06 2009-08-04 International Business Machines Corporation Bus/device/function translation within and routing of communications packets in a PCI switched-fabric in a multi-host environment utilizing multiple root switches
US20080137676A1 (en) 2006-12-06 2008-06-12 William T Boyd Bus/device/function translation within and routing of communications packets in a pci switched-fabric in a multi-host environment environment utilizing a root switch

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012164418A1 (en) * 2011-06-01 2012-12-06 International Business Machines Corporation Facilitating processing in a communications environment using stop signaling
GB2503406A (en) * 2011-06-01 2013-12-25 Ibm Facilitating processing in a communications environment using stop signaling
US8644136B2 (en) 2011-06-01 2014-02-04 International Business Machines Corporation Sideband error signaling
GB2503406B (en) * 2011-06-01 2014-05-07 Ibm Facilitating processing in a communications environment using stop signaling
US8787155B2 (en) 2011-06-01 2014-07-22 International Business Machines Corporation Sideband error signaling
US8880957B2 (en) 2011-06-01 2014-11-04 International Business Machines Corporation Facilitating processing in a communications environment using stop signaling
US8880956B2 (en) 2011-06-01 2014-11-04 International Business Machines Corporation Facilitating processing in a communications environment using stop signaling

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