CN1885428A - Ferroelectric memory device - Google Patents

Abstract

The invention discloses a ferroelectric storage device, especially a ferroelectric storage device with high integration in the bit line direction. The ferroelectric storage device includes: a first bit line extending in a first direction; a plurality of first memory cells connected to the first bit line for storing specified data; extending in a direction substantially opposite to the first direction The second bit line; connected with the second bit line, used to store the second storage unit of specified data; connected with one end of the first bit line and one end of the second bit line, used for storing in the first storage unit A sense amplifier for amplifying the data in the second storage unit; a latch circuit connected to the other end of the first bit line to latch the data amplified by the sense amplifier; for making the first storage unit and the second The data stored in the storage unit is transmitted; and the first switch is connected to the other end of the second bit line and switches whether to connect the second bit line to the data bus.

Description

ferroelectric memory device

technical field

The present invention relates to a ferroelectric storage device.

Background technique

A conventional ferroelectric memory device includes a ferroelectric memory device disclosed in Japanese Unexamined Patent Application Publication No. 2004-220739 (Patent Document 1). In the above conventional ferroelectric memory device, the column decoder provided at one end of the main bit line can read data together with the ferroelectric memory device.

Patent Document 1: JP-A-2004-220739

However, in the conventional ferroelectric memory device described above, a sense amplifier and a write circuit are connected to the lower end of the bit line, and a data latch circuit is connected to the upper end. Therefore, in the above-mentioned conventional ferroelectric memory device, it is necessary to arrange memory cells alternately between the paired bit lines, so there is a problem that the degree of integration of the memory cells is lowered.

Contents of the invention

The technical problem to be solved by the present invention is to provide a ferroelectric storage device capable of solving the above problems. This object is achieved by the combination of the technical features recited in the independent claims among the claims. Furthermore, the dependent claims are preferred specific embodiments of the invention.

(1) According to the first aspect of the present invention, there is provided a ferroelectric memory device, comprising: a first bit line extending in a first direction from one end to the other end; a first memory cell connected to the first bit line, For storing specified data; a second bit line extending from one end to the other in a direction substantially opposite to the first direction; a second memory cell connected to the second bit line for specified data; a sense amplifier , connected to one end of the first bit line and one end of the second bit line, amplifying the data stored on the first storage unit and the second storage unit; a latch circuit, used for latching the amplified by the sense amplifier data; a data bus, used to transmit the data stored in the first storage unit and the second storage unit; and a first switch, connected to the other end of the second bit line, used to determine whether to connect the The second bit line and the data bus are switched.

In the above invention, the first bit line and the second bit line connected to the sense amplifier extend in substantially opposite directions to each other. Therefore, according to the above invention, since the arrangement intervals of the plurality of first memory cells and the plurality of second memory cells can be narrowed in the first direction and the second direction, it is possible to provide a highly integrated ferroelectric memory device.

Furthermore, in the above invention, the lengths of the first bit line and the second bit line are approximately half as compared to the case of the folded bit line system in which the first bit line and the second bit line extend in the same direction, Therefore, the capacity of the bit lines can be reduced, and the potential difference between the bit lines can be increased. Furthermore, it is possible to provide a ferroelectric memory device that operates at high speed and consumes little power.

(2) In the above ferroelectric memory device, further comprising: a first dummy cell arranged between the sense amplifier and the first memory cell and connected to the first bit line; and a second dummy cell arranged in the readout Between the amplifier and the second storage unit, it is connected to the second bit line; wherein, the sense amplifier amplifies the data stored in the first storage unit based on the second dummy unit, and amplifies the data stored in the first storage unit based on the first dummy unit. Data stored in the second storage unit is amplified.

In the above invention, the first bit line and the second bit line are respectively connected to the dummy cells, so there is no need to separately provide a reference bit line. Therefore, according to the above-mentioned invention, even when used in a device for fixing the dimension in the word line direction, such as a display driver IC, it is possible to provide sufficient intervals between the bit lines.

(3) In the above ferroelectric memory device, further comprising a second switch provided between the first bit line and the latch circuit, wherein the first switch amplifies the data stored in the first memory cell in the sense amplifier is turned on; the second switch is turned on when the sense amplifier amplifies the data stored in the second memory unit.

According to the above invention, since the capacity added to the first bit line and the second bit line can be controlled, the reference potential can be generated by the dummy cell having the same shape as the memory cell, and the characteristic variation due to the process unevenness of the dummy cell can be suppressed. .

(4) The ferroelectric storage device designed in other embodiments of the present invention includes: a first bit line extending in a first direction from one end to the other end; a plurality of first memory cells connected to the first bit line , for storing specified data; a second bit line extending from one end to the other end in a second direction substantially opposite to the first direction; a plurality of second memory cells connected to the second bit line, Used to store specified data; the first sense amplifier is connected to one end of the first bit line and one end of the second bit line, and is stored in the first storage unit and the second storage unit amplify the data; the third bit line extends from one end to the other end in the first direction; a plurality of third memory cells are connected to the third bit line for storing specified data; the fourth bit line extending from one end to the other in the second direction; a plurality of fourth memory cells connected to the fourth bit line for storing specified data; a second sense amplifier connected to the third One end of the bit line is connected to one end of the fourth bit line to amplify the data stored in the third storage unit and the fourth storage unit; the latch circuit is connected to the first bit line The other end is connected to latch the data amplified by each sense amplifier; and a switch is connected to the other end of the second bit line and the other end of the third bit line to determine whether to connect the first bit line The second bit line and the third bit line are switched.

In the above invention, the first bit line and the second bit line connected to the first sense amplifier and the third bit line and the fourth bit line connected to the second sense amplifier can respectively extend in substantially opposite directions to each other. . Therefore, according to the above-mentioned invention, since the arrangement intervals of the plurality of first to fourth memory cells are narrowed in the first direction and the second direction, it is possible to provide a highly integrated ferroelectric memory device.

In addition, in the above invention, compared with the case of the folded bit line system in which the bit lines connected to the sense amplifiers extend in the same direction, the length of each bit line can be approximately half, so the bit line can be reduced. Capacitance can increase the potential difference between the bit lines. Furthermore, it is possible to provide a ferroelectric memory device that operates at high speed and consumes little power.

(5) In the above-mentioned ferroelectric storage device, it also includes: a data bus, which transmits the data stored from the first storage unit to the fourth storage unit; a first switch, connected to the fourth bit line The other end is connected to switch whether to connect the data bus to the fourth bit line; and the second switch is arranged between the first bit line and the latch circuit.

(6) In the above-mentioned ferroelectric memory device, further comprising: a first dummy cell connected to the first bit line; a second dummy cell connected to the second bit line; a third dummy cell connected to the The third bit line is connected; and the fourth dummy cell is connected to the fourth bit line; wherein, the first sense amplifier uses the second dummy cell as a reference to amplify and store in the first memory cell and amplifies the data stored in the second storage unit based on the first dummy unit; the second sense amplifier amplifies the data stored in the third storage unit based on the fourth dummy unit the data in the unit, and amplify the data stored in the fourth storage unit based on the third dummy unit.

In the above invention, since the dummy cells are connected to the respective bit lines, it is not necessary to separately provide a reference bit line. Therefore, according to the above-mentioned invention, it is possible to provide a sufficient interval between bit lines even when it is used in a device having a fixed dimension in the word line direction, such as a display driver IC.

(7) The ferroelectric storage device designed in other ways of the present invention includes: a first bit line extending in a first direction from one end to the other end; a plurality of first memory cells connected to the first bit line, Used to store specified data; the second bit line extends from one end to the other end in a second direction substantially opposite to the first direction; a plurality of second memory cells are connected to the second bit line and used for storing specified data; the first sense amplifier is connected to one end of the first bit line and one end of the second bit line, amplifying data; a third bit line extending from one end to the other in the first direction; a plurality of third memory cells connected to the third bit line for storing specified data; a fourth bit line , extending from one end to the other end in the second direction; a plurality of fourth memory cells connected to the fourth bit line for storing specified data; a second sense amplifier connected to the third bit line One end of the line is connected to one end of the fourth bit line to amplify the data stored in the third storage unit and the fourth storage unit; extending upward, connected to the first sense amplifier through a switch, and connected to the second sense amplifier through a switch; and a latch circuit, connected to the other end of the data line, for each sense amplifier The amplified data is latched.

In the above invention, the first bit line and the second bit line connected to the first sense amplifier and the third bit line and the fourth bit line connected to the second sense amplifier can respectively extend in substantially opposite directions to each other. . Therefore, according to the above-mentioned invention, since the arrangement intervals of the plurality of first to fourth memory cells are narrowed in the first direction and the second direction, it is possible to provide a highly integrated ferroelectric memory device.

(8) In the above-mentioned ferroelectric storage device, it also includes: a data bus, which transmits the data stored from the first storage unit to the fourth storage unit; a first switch, connected to one end of the data line connection, switching whether to connect the data line to the data bus; and a second switch, disposed between the data line and the latch circuit.

(9) In the above ferroelectric memory device, further comprising: a first dummy cell connected to the first bit line; a second dummy cell connected to the second bit line; a third dummy cell connected to the The third bit line is connected; and the fourth dummy cell is connected to the fourth bit line; wherein, the first sense amplifier uses the second dummy cell as a reference to amplify and store in the first memory cell and amplify the data stored in the second storage unit with the first dummy unit as a reference; the second sense amplifier amplifies the data stored in the third storage unit with the fourth dummy unit as a reference and amplifying the data stored in the fourth storage unit with the third dummy unit as a reference.

In the above invention, since the dummy cells are connected to the respective bit lines, it is not necessary to separately provide a reference bit line. Therefore, according to the above-mentioned invention, it is possible to provide a sufficient interval between bit lines even when it is used in a device having a fixed dimension in the word line direction, such as a display driver IC.

(10) A ferroelectric memory device according to another aspect of the present invention includes: a first bit line extending in a first direction from one end to the other end; a plurality of first sub-bit lines connected to the first bit line a plurality of first memory cells, connected to each of the first sub-bit lines for storing specified data; a second bit line, from one end to the other end in a second direction substantially opposite to the first direction Extend; a plurality of second sub-bit lines, connected to the second bit lines; a plurality of second memory cells, connected to the respective second sub-bit lines, for storing specified data; a sense amplifier, connected to the second sub-bit lines One end of the first bit line is connected to one end of the second bit line to amplify the data stored in the first storage unit and the second storage unit; and a latch circuit, connected to the first The other end of the bit line is connected to latch the data amplified by the sense amplifier.

In the above invention, the first bit line and the second bit line connected to the sense amplifier extend in substantially opposite directions to each other. Therefore, according to the above-mentioned invention, since the arrangement intervals of the plurality of first to fourth memory cells are narrowed in the first direction and the second direction, it is possible to provide a highly integrated ferroelectric memory device.

In addition, in the above invention, the length of each bit line can be roughly half of that of the folded bit line method in which the bit lines connected to the sense amplifiers extend in the same direction, so that the bit line capacity can be reduced. , the potential difference between the bit lines can be increased. Furthermore, it is possible to provide a ferroelectric memory device that operates at high speed and consumes little power.

Furthermore, since a plurality of sub-bit lines SBL are connected to each bit line BL, the capacity added to the bit line BL can be reduced. Therefore, it is possible to further provide a ferroelectric memory device that operates at a high speed and has a large readout margin.

(11) In the above-mentioned ferroelectric storage device, it also includes: a data bus, which transmits the data stored by the first storage unit and the second four storage units; a first switch, connected to the second bit The other end of the line is connected to switch whether to connect the second bit line to the data bus; and a second switch is arranged between the first bit line and the latch circuit.

(12) In the ferroelectric memory device above, further comprising: a first dummy cell connected to the first bit line; and a second dummy cell connected to the second bit line; wherein the readout The amplifier amplifies data stored in the first storage unit with reference to the second dummy cell, and amplifies data stored in the second storage unit with reference to the first dummy cell.

In the above invention, since the dummy cells are connected to the respective bit lines, it is not necessary to separately provide a reference bit line. Therefore, according to the above-mentioned invention, it is possible to provide a sufficient interval between bit lines even when it is used in a device having a fixed dimension in the word line direction, such as a display driver IC.

Description of drawings

FIG. 1 is a schematic diagram showing the configuration of a display driver IC according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing the structure of a display driver IC according to a second embodiment of the present invention.

FIG. 3 is a schematic diagram showing the structure of a display driver IC according to a third embodiment of the present invention.

FIG. 4 is a schematic diagram showing the structure of a display driver IC according to a fourth embodiment of the present invention.

Detailed ways

Below, with reference to accompanying drawing, illustrate the present invention by the embodiment of the present invention, but the following embodiment is not the limitation of the invention described in the scope of claims, and all the combination of features described in the embodiment is not necessarily the present invention necessary for the solution.

(first embodiment)

FIG. 1 is a schematic configuration diagram of a display driver IC according to this embodiment. The display driver IC of this embodiment includes a ferroelectric memory device and a display driver circuit 170 that drives a device having a display such as a liquid crystal display device based on data stored in the ferroelectric memory device.

The ferroelectric memory device includes memory cell arrays 110 and 112, a word line control unit 120, a plate line control unit 130, a sense amplifier 140, a latch circuit 150, an n-type MOS transistor 152 as an example of a second switch, and a data A bus 160, an n-type MOS transistor 162 as an example of a first switch, a plurality of bit lines BL11-1n and BL21-2n (n is an integer greater than or equal to 2, hereinafter referred to as "bit line BL"), a plurality of A word line WL 11-1m and WL 21-2m (m is an integer greater than or equal to 2. Hereinafter referred to as "word line WL".), a plurality of plate lines PL 11-1m and PL21-2m (hereinafter referred to as " plate line PL”.), dummy word lines DWL1 and DWL2, and dummy plate lines DPL1 and DPL2.

The display driver IC of this embodiment stores data supplied from the outside in the memory cells MC provided on the memory cell arrays 110 and 112 via the data bus 160 . Furthermore, the latch circuit 150 latches data read from the memory cell MC, and the display drive circuit 170 drives an external display based on the data latched in the latch circuit 150 .

The memory cell arrays 110 and 112 include a plurality of memory cells MC and a plurality of dummy cells DMC arranged in an array. In the memory cell arrays 110 and 112, the word line WL is arranged relatively parallel to the plate line PL, and is arranged to cross the bit line BL. Furthermore, in memory cell arrays 110 and 112, each memory cell MC is connected to any one of word line WL, plate line PL, and bit line BL.

Each memory cell MC includes an n-type MOS transistor TR and a ferroelectric capacitor C. One of the source and the drain of the n-type MOS transistor TR is connected to the bit line BL, and the other is connected to one end of the ferroelectric capacitor C. Furthermore, the gate of the n-type MOS transistor TR is connected to a word line WL, and based on the potential of the word line WL, whether or not to connect one end of the ferroelectric capacitor C to the corresponding bit line BL is switched.

Also, the other end of the ferroelectric capacitor C is connected to one (any) plate line PL. Furthermore, the ferroelectric capacitor C stores predetermined data based on the potential difference between the corresponding bit line BL and plate line PL, that is, the potential difference between one end and the other end of the ferroelectric capacitor C.

In memory cell arrays 110 and 112, dummy cells DMC1 and DMC2 are connected to bit line BL, dummy word lines DWL1 and DWL2, and dummy plate lines DPL1 and DPL2, respectively. Dummy cell DMC has the same configuration as memory cell MC, and is provided between a region where memory cell MC is provided and sense amplifier 140 in memory cell arrays 110 and 112 . That is, in the memory cell arrays 110 and 112, the dummy cell DMC is located closer to the sense amplifier 140 than the memory cell MC, and is connected to the bit line BL.

The word line control unit 120 controls voltages of the word line WL and the dummy word lines DWL1 and DWL2 , and controls on and off of the n-type MOS transistor TR. Also, the plate line control unit 130 controls the voltage of the plate line PL and the dummy plate lines DPL1 and DPL2 , and controls the voltage of the other end of the ferroelectric capacitor C.

The sense amplifier 140 amplifies data stored in each memory cell MC based on charges discharged from each ferroelectric capacitor C to the bit line BL. The sense amplifier 140 of this embodiment is a latch type sense amplifier having one end and the other end. One end is connected to the bit lines BL11-1n, and the other end is connected to the bit lines BL21-2n. The bit lines BL11 to 1n extend in a first direction from the sense amplifier 140 to the latch circuit 150, and the bit lines BL21 to 2n extend in a second direction substantially opposite to the first direction.

Moreover, in this embodiment, when the sense amplifier 140 reads the data stored in the memory cell MC of the memory cell array 110, it amplifies the charge stored in the dummy cell DMC2 based on the data of the memory cell array 112 released from the data. The data in the memory cell MC; when the sense amplifier 140 reads the data stored in the memory cell MC of the memory cell array 112, it amplifies the data stored in the memory cell according to the charge released from the dummy cell DMC1 of the memory cell array 110. Data in MC. That is, the ferroelectric memory device of this embodiment has an open bit line structure.

The latch circuit 150 latches the data amplified by the sense amplifier 140 . The latch circuit 150 provides the latched data to the display driving circuit 170 . The display drive circuit 170 drives an external display based on the data supplied from the latch circuit 150 .

Furthermore, an n-type MOS transistor 152 is provided between the latch circuit 150 and the bit lines BL11 to 1n. The source and the drain of the n-type MOS transistor 152 are respectively connected to the latch circuit 150 and the bit lines BL11-1n, and whether or not the bit lines BL11-1n are connected to the latch circuit 150 is determined based on the signal LAT supplied to the gate. switch.

The data bus 160 transfers data stored in the memory cells MC supplied from the outside. The source and drain of the n-type MOS transistor 162 are respectively connected to the data bus 160 and the bit lines BL 21-2n, and whether or not to connect the bit lines BL 21-2n to the data bus 160 is switched based on the voltage of the signal YSEL supplied to the gate. .

Next, the operation of the display driver IC of this embodiment will be described. Next, the operation of writing data to a memory cell MC connected to word line WL11, plate line PL11, and bit line BL11 (hereinafter referred to as "the memory cell MC") will be described. The operation of display driving circuit 170 driving the display with the data stored in memory cell MC will be described.

First, when data supplied to the data bus 160 is stored in the memory cell MC, the n-type MOS transistor 162 connects the bit line BL21 to the data bus 160 based on the signal YSEL. Furthermore, when the sense amplifier 140 connected to the bit line BL21 is turned on, the voltage of the bit line BL11 connected to the memory cell MC is substantially equal to the voltage of the data bus 160. In this embodiment, when the data "1" is stored in the ferroelectric capacitor C, the operating voltage VCC of the display driver IC is supplied to the data bus 160; Bus 160 provides 0V. Furthermore, when the word line control unit 120 changes the voltage of the word line WL11 to turn on the n-type MOS transistor TR of the memory cell MC, the voltage of the bit line BL11 is supplied to one end of the ferroelectric capacitor C, based on The voltage of the data bus 160 stores predetermined data in the ferroelectric capacitor C.

Next, when reading data stored in the memory cell MC, first, the word line control unit 120 turns on the word line WL11 and the dummy word line DWL2. Then, when the plate line control unit 130 raises the voltage of the plate line PL11 to VCC, the charge accumulated in the ferroelectric capacitor C is released to the bit line BL11. At this time, the voltage rise of the bit line BL11 is higher when data "1" is stored than when data "0" is stored in the memory cell.

Then, when reading the data stored in the memory cell, the word line control unit 120 changes the voltage of the dummy word line DWL2 to turn on the n-type MOS transistor TR of the dummy cell DMC2. Furthermore, the plate line control unit 130 sets the voltage of the dummy plate line DPL2 to VCC as well, thereby discharging the charge accumulated in the ferroelectric capacitor C of the dummy cell DMC2 to the bit line BL21.

In this embodiment, data "1" is stored in the dummy cell DMC2, and the n-type MOS transistor 162 connected to the bit line BL21 is turned on, and the bit line BL21 and the data bus 160 are connected. Therefore, a charge corresponding to the data "1" is discharged to the bit line BL21, but the n-type MOS transistor 162 is turned on, and the capacity added to the bit line BL21 becomes larger than that of the bit line BL11, so the bit line BL21 The voltage rises to a voltage between the voltage of the bit line BL11 when data "1" is stored in the memory cell MC and the voltage of the bit line BL11 when data "0" is stored. That is, when data "1" is stored in the memory cell MC, the voltage of the stored bit line BL11 is higher than the voltage of the bit line BL21; on the other hand, when data "0" is stored, the voltage of the stored bit line BL11 is The voltage is lower than the voltage of the bit line BL 21.

Furthermore, after discharging charges to the bit lines BL11 and BL21, the sense amplifier 140 amplifies the voltage of the bit line BL11 based on the voltage of the bit line BL21, that is, amplifies the data stored in the memory cell MC. Specifically, when the voltage of the bit line BL11 is higher than the voltage of the bit line BL21, that is, when data "1" is stored in the memory cell MC, the sense amplifier 140 raises the voltage of the bit line BL11 to VCC. On the other hand, when the voltage of the bit line BL11 is lower than the voltage of the bit line BL21, that is, when data "0" is stored in the memory cell MC, the sense amplifier 140 makes the voltage of the bit line BL11 0V.

Next, the n-type MOS transistor 152 is turned on, and the latch circuit 150 latches the data read from the memory cell MC to the bit line BL11. Also, based on the data latched in the latch circuit 150, the display drive circuit 170 drives an external display. Through the above operations, an external display can be driven based on data supplied from the outside.

In the above example, the operation of the display driver IC was described by taking the memory cell MC of the memory cell array 110 as an example, but the same applies to the case of storing data in the memory cell MC of the memory cell array 112 and reading data. action. Also, when reading data from memory cell MC of memory cell array 112 , sense amplifier 140 amplifies the data read from memory cell MC with reference to dummy memory cell DMC1 of memory cell array 110 . At this time, it is preferable to turn on the n-type MOS transistor 152 to add a predetermined capacity to the bit lines BL11 to 1n.

Furthermore, in the above-mentioned example, the n-type MOS transistors 152 and 162 are turned on, and a predetermined capacitance is added to the bit line BL to generate a standard voltage. different areas, a reference voltage can be generated.

In this embodiment, the bit lines BL11-1n and BL21-2n connected to the sense amplifier 140 extend in opposite directions to each other. Therefore, according to this embodiment, the arrangement interval of memory cells MC in memory cell arrays 110 and 112 can be narrowed in the extending direction of bit line BL, so that a highly integrated ferroelectric memory device can be provided. In particular, as shown in this embodiment, when the ferroelectric memory device is used in a display driver IC, the interval of the bit lines BL corresponds to the interval of an external display, and at the same time, the bit line BL can be extended in the extending direction. Reduce the size of display driver ICs. That is, a ferroelectric memory device and a display driver IC with very high area efficiency can be provided.

In this embodiment, compared with the folded bit line method, the length of the bit line BL can be approximately half, so the capacitance of the bit line BL can be reduced, and the potential between the bit lines connected to the sense amplifier 140 can be increased. Difference. Furthermore, it is possible to provide a ferroelectric memory device with high-speed operation and low power consumption and a display driver IC.

In this embodiment, the dummy cells DMC are respectively connected to the bit lines BL11-1n and the bit lines BL21-2n, so it is not necessary to separately connect reference (standard) bit lines. Further, according to this embodiment, even when the ferroelectric memory device is used in a device having a fixed dimension in the word line direction, such as a display driver IC, a sufficient interval between the bit lines BL can be obtained.

According to this embodiment, the on and off of the n-type MOS transistors 152 and 162 can be appropriately controlled, and the capacitance added to the bit line BL can be controlled, so that a ferroelectric memory device with a large readout margin can be provided.

(second embodiment)

2 is a schematic configuration diagram of a display driver IC according to a second embodiment of the present invention. Since the configuration and operation of the present embodiment are identical to those of the above-mentioned first embodiment, differences will be described below.

The ferroelectric memory device includes: memory cell arrays 110, 112, 114, 116, word line control unit 120, plate line control unit 130, sense amplifiers 140A, 140B, latch circuit 150, n type MOS transistor 152, data bus 160, n-type MOS transistor 162 as an example of a first switch, a plurality of bit lines BL 11˜1n, BL 21˜2n, BL 31˜3n, BL 41˜4n (n is greater than Integer equal to 2. Hereinafter referred to as "bit line BL".), a plurality of word lines WL 11~1m, WL 21~2m, WL 31~3m, WL 41~4m (m is an integer greater than or equal to 2. Hereinafter referred to as is "word line WL".), multiple plate lines PL 11~1m, PL 21~2m, PL 31~3m, PL 41~4m (hereinafter referred to as "plate line PL"), dummy word line DWL 1~ 4 and dummy plate lines DPL 1 to 4, and switches for whether to connect bit lines BL 21 to 2n and bit lines BL 31 to 3n (n-type MOS transistor 180 is an example).

A plurality of memory cells MC are formed on each of the memory cell arrays 110 to 116, and the plurality of memory cells MC are connected to bit lines BL. Moreover, dummy cells DMC 1-4 are provided on each memory cell array 110-116. Specifically, dummy cells DMC 1-4 are connected to bit lines BL, dummy word lines DWL 1-4, and dummy plate lines DPL 1-4 respectively. 4 connections. The dummy cell DMC may have the same structure as the memory cell MC, or may have a different structure from the memory cell MC. Furthermore, in each of the memory cell arrays 110 to 116, for example, a dummy cell DMC is provided between a region where the memory cell MC is provided and the sense amplifiers 140A and 140B. That is, in memory cell arrays 110 to 116, dummy cells DMC are located closer to sense amplifiers 140A and 140B than memory cells MC, and dummy cells DMC 1 to 4 are connected to bit lines BL.

Sense amplifiers 140A and 140B have the same circuit configuration as each other, specifically, they are latch-type sense amplifiers having one end and the other end. One end of the sense amplifier 140A is connected to the bit lines BL11-1n, and the other end is connected to the bit lines BL21-2n. Further, one end of the sense amplifier 140B is connected to the bit lines BL31 to 3n, and the other end is connected to the bit lines BL41 to 4n. The bit lines BL11-1n, BL31-3n extend in a first direction from the sense amplifiers 140A, 140B to the latch circuit 150, and the bit lines BL21-2n, BL 41-4n extend in a direction substantially opposite to the first direction. That is, extending in the second direction.

Moreover, when the sense amplifier 140A reads the data stored in the memory cell MC of the memory cell array 110, the data stored in the memory cell MC is amplified according to the charge released based on the data of the dummy cell DMC2 of the memory cell array 112; When the sense amplifier 140A reads the data stored in the memory cell MC of the memory cell array 112 , the data stored in the memory cell MC is amplified based on the charge discharged from the dummy cell DMC1 of the memory cell array 110 . On the other hand, when the sense amplifier 140B reads the data stored in the memory cell MC of the memory cell array 114, it amplifies the charge stored in the memory cell MC according to the charge released based on the data of the dummy cell DMC4 of the memory cell array 116. When the sense amplifier 140B reads the data stored in the memory cell MC of the memory cell array 116, the data stored in the memory cell MC is amplified based on the charge released from the dummy cell DMC3 of the memory cell array 114. . That is, the ferroelectric memory device of the present embodiment has an open bit line structure, and sense amplifiers have at least two (two in the example shown in FIG. ) stacked structure.

The latch circuit 150 latches the data amplified by the sense amplifiers 140A and 140B. Furthermore, an n-type MOS transistor 152 is provided between the latch circuit 150 and the bit lines BL11 to 1n. The source and drain of the n-type MOS transistor 152 are respectively connected to the latch circuit 150 and the bit lines BL11-1n, and the n-type MOS transistor 152 responds to each of the bit lines BL11-1n based on the signal LAT supplied to the gate. Whether or not the bit line is connected to the latch circuit 150 is switched.

The data bus 160 transmits data stored in each memory cell MC. Furthermore, an n-type MOS transistor 162 is provided between the data bus line 160 and the bit lines BL41 to 4n. The source and the drain of the n-type MOS transistor 162 are respectively connected to the data bus 160 and the bit lines BL 41-4n, and the n-type MOS transistor 162 determines whether to connect the data bus 160 and the bit line BL 41 based on the signal YSEL supplied to the gate. ~4n to switch.

An n-type MOS transistor 180 is provided between the bit lines BL21-2n and the bit lines BL31-3n. The source and the drain of the n-type MOS transistor 180 are respectively connected to the bit lines BL 21-2n and the bit lines BL 31-3n, and the n-type MOS transistor 180 determines whether to connect the bit lines BL 21-3n based on the signal SEL supplied to the gate. 2n and the bit lines BL 31 to 3n are switched.

Next, the operation of the display driver IC of this embodiment will be described. In the following description, first, an operation of writing data to a memory cell MC (hereinafter referred to as "the memory cell MC") connected to the word line WL11, the plate line PL11, and the bit line will be described. On the line BL11, next, the operation of reading the data stored in the memory cell MC and driving the display by the display driving circuit 170 will be described.

First, when storing data supplied to the data bus 160 in the memory cell MC, the n-type MOS transistor 162 connects the bit line BL41 to the data bus 160 based on the signal YSEL. Then, the sense amplifier 140B, the n-type MOS transistor 180, and the sense amplifier 140A are all turned on, and the voltage of the bit line BL11 connected to the memory cell MC is substantially equal to the voltage of the data bus line 160. Then, the word line control unit 120 changes the voltage of the word line WL11 to store predetermined data in the memory cell MC based on the voltage of the data bus 160 (for example, VCC or 0V).

In addition, the sense amplifiers 140A, 140B and the n-type MOS transistor 180 can be appropriately turned on or off according to which memory cell array the accessed memory cell MC is located in.

Next, when reading data stored in the memory cell MC, first, the word line control unit 120 turns on the word line WL11 and the dummy word line DWL2. Then, when the plate line control unit 130 raises the voltage of the plate line PL11 to VCC, the charge accumulated in the ferroelectric capacitor of the memory cell MC is discharged to the bit line BL11. At this time, the voltage rise of the bit line BL11 when data "1" is stored is higher than when data "0" is stored in the memory cell MC.

Then, when reading data stored in memory cell MC, word line control unit 120 changes the voltage of dummy word line DWL2 , and plate line control unit 130 sets the voltage of dummy plate line DPL2 to VCC. Accordingly, the charge accumulated in the ferroelectric capacitor of the dummy cell DMC2 is discharged to the bit line BL21.

As an example, when the dummy cell DMC2 has a structure different from that of the memory cell MC, for example, when the capacitor area of the dummy cell DMC2 is greater than the capacitor area of the memory cell MC, data "0" is stored on the dummy cell DMC2, on the other hand , when the capacitor area of the dummy cell DMC2 is smaller than the capacitor area of the memory cell MC, data "1" is stored in the dummy cell DMC2. Thus, the voltage on the bit line BL21 appears as the voltage of the bit line BL11 when data "1" is stored in the memory cell MC and the voltage of the bit line BL11 when data "0" is stored voltage between. That is, when data "1" is stored in the memory cell MC, the voltage of the bit line BL11 is higher than the voltage of the bit line BL21. On the other hand, when data "0" is stored, the voltage of the bit line BL11 is higher. The voltage of is lower than the voltage of bit line BL 21. In this way, the reference voltage can be generated based on the data stored in the dummy cell DMC2, and the data of the memory cell MC can be read.

Then, after discharging charges to the bit lines BL11 and BL21, based on the voltage of the bit line BL21, the sense amplifier 140A amplifies the voltage of the bit line BL11, that is, amplifies the data stored in the memory cell MC. Specifically, when the voltage of the bit line BL11 is higher than the voltage of the bit line BL21, that is, when data "1" is stored in the memory cell MC, the sense amplifier 140A raises the voltage of the bit line BL11 to VCC . On the other hand, when the voltage of the bit line BL11 is lower than the voltage of the bit line BL21, that is, when data "0" is stored in the memory cell MC, the sense amplifier 140A makes the voltage of the bit line BL11 0V. .

Next, the n-type MOS transistor 152 is turned on, and the latch circuit 150 latches the data read from the memory cell MC to the bit line BL11. Furthermore, based on the data latched by the latch circuit 150, the display drive circuit 170 drives an external display. Through the above operations, an external display can be driven based on data supplied from the outside.

In the above description, the case where the dummy cell DMC2 has a different structure from the memory cell MC has been described, but when the dummy cell DMC2 has the same structure as the memory cell MC, that is, when both capacitors have the same area, reading can be performed. action. That is, the capacity attached to the bit line BL21 is changed, whereby the reference voltage can be generated based on the data stored in the dummy cell DMC2. For example, when data "1" is stored in the dummy cell DMC2, the n-type MOS transistor 180 is turned on based on the signal SEL, and the bit line BL21 and the bit line BL31 are connected. At this time, the charge corresponding to the data "1" is discharged to the bit line BL 21, but since the capacity added to the bit line BL 21 is larger than that of the bit line BL 11, the voltage on the bit line BL 21 appears as when at A voltage between the voltage of the bit line BL11 when data "1" is stored in the memory cell MC and the voltage of the bit line BL11 when data "0" is stored. And, at this moment, sense amplifier 140B and n-type MOS transistor 180 conduction simultaneously, can also make bit line BL 21 and bit line BL 41 be connected, n-type MOS transistor 162 and n-type MOS transistor 180 and sense amplifier 140B simultaneously When turned on, the bit line BL21 can also be connected to the data bus 160 .

Or, as another example, when the dummy cell DMC2 has the same structure as the memory cell MC, that is, when the capacitor areas of the two are the same, the capacitance on the bit line BL11 attached to the memory cell MC side can be changed. . For example, when data "0" is stored in the dummy cell DMC2, the n-type MOS transistor 152 is turned on based on the signal LAT, and the bit line BL11 and the latch circuit 150 are connected. At this time, an amount of charge corresponding to either the data "0" or "1" stored in the memory cell MC is released to the bit line BL11, but since the capacitance added to the bit line BL11 is larger than that of the bit line BL 21 capacitance, so the voltage of the bit line BL 21 is relatively set to the voltage of the bit line BL 11 when data "1" is stored in the memory cell MC and the voltage of the bit line BL 11 when data "0" is stored The voltage between the voltages.

Furthermore, the data read from any one of the memory cells MC connected to the bit line BL31 can also be amplified by the sense amplifier 140B with reference to the dummy cell DMC4 connected to the bit line BL41. In this case, the dummy cell DMC4 may have the same structure as the memory cell MC, or may have a different structure from the memory cell MC. In the latter case, it is possible to cause data "0" to be stored in the dummy cell DMC4, changing the capacitance attached to the bit line BL31. Specifically, based on the signal SEL, the n-type MOS transistor 180 is turned on, so that the bit line BL 21 is connected to the bit line BL 31, or the sense amplifier 140A and the n-type MOS transistor 180 are turned on at the same time, and further transmission can be made on the bit line BL 31. Connect the bit line BL11, or turn on the n-type MOS transistor 180 and the sense amplifier 140A simultaneously with the n-type MOS transistor 152, and further connect the latch circuit 150 to the bit line BL31.

In addition, the sense amplifier 140A can amplify the data stored in the memory cell array 112 based on the dummy cell DMC1 , and the sense amplifier 140B can also amplify the data stored in the memory cell array 116 based on the dummy cell DMC3 .

As described above, in this embodiment, the bit lines BL 11 to 1n and BL 21 to 2n connected to the sense amplifier 140A, and the bit lines BL 31 to 3n and BL 41 to 4n connected to the sense amplifier 140B are respectively extending in substantially opposite directions from each other. Therefore, according to this embodiment, the arrangement interval of the memory cells MC in the memory cell arrays 110 to 116 can be narrowed in the extending direction of the bit line BL, so that a highly integrated ferroelectric memory device can be provided. In particular, as shown in this embodiment, when this ferroelectric memory device is used in a display driver IC, the interval between the bit lines BL and the interval of the external display can be matched, and in the extending direction of the bit line BL, Reduce the size of display driver ICs. That is, a ferroelectric memory device and a display driver IC with very high area efficiency can be provided.

In addition, other detailed configurations and effects of this embodiment are the same as those described in the first embodiment.

(third embodiment)

FIG. 3 is a diagram showing the configuration of a display driver IC according to a third embodiment of the present invention. The configuration and operation of this embodiment overlap with the above-mentioned second embodiment, so the following points of difference will be described.

The ferroelectric memory device includes: memory cell arrays 110, 112, 114, 116, word line control unit 120, plate line control unit 130, sense amplifiers 140A, 140B, latch circuit 150, n type MOS transistor 152, data bus 160, n-type MOS transistor 162 as an example of a first switch, a plurality of bit lines BL 11˜1n, BL 21˜2n, BL 31˜3n, BL 41˜4n (n is greater than Integer equal to 2. Hereinafter, referred to as "bit line BL"), a plurality of word lines WL 11~1m, WL 21~2m, WL 31~3m, WL 41~4m (m is an integer greater than or equal to 2. Hereinafter referred to as is "word line WL".), multiple plate lines PL 11~1m, PL 21~2m, PL 31~3m, PL 41~4m (hereinafter referred to as "word line PL".), dummy word lines DWL1~ 4 and dummy plate lines DPL 1 to 4, data lines DL 1 to n (hereinafter referred to as "data lines DL"), and switching whether to connect the data lines DL 1 to n and each sense amplifier 140A, 140B Switches (n-type MOS transistors 182, 184 as an example).

In the above-mentioned second embodiment, the bit line BL is also used to transmit the write data from the data bus 160 and transmit the read data to the latch circuit 150, but in this embodiment, a data line for transmitting each data is additionally provided. Line DL.

The data line DL extends from one end to the other end along the first direction, one end of which is connected to the data bus 160 through the n-type MOS transistor 162 , and the other end is connected to the latch circuit 150 through the n-type MOS transistor 152 . Furthermore, between the n-type MOS transistors 152 and 162, each data line DL 1 to n is connected to the sense amplifier 140A via the n-type MOS transistor 182 operating based on the signal SEL 1, and the n-type MOS transistor 182 operating based on the signal SEL 2 is connected to the sense amplifier 140A. The MOS transistor 184 is connected to the sense amplifier 140B. In detail, the source and the drain of the n-type MOS transistor 182 are respectively connected to the data line DL and the sense amplifier 140A, and based on the signal SEL1 supplied to the gate, the n-type MOS transistor 182 determines whether the data line DL is connected to the read amplifier 140A. output amplifier 140A for switching. On the other hand, the source and drain of the n-type MOS transistor 184 are respectively connected to the data line DL and the sense amplifier 140B. Based on the signal SEL2 supplied to the gate, the n-type MOS transistor 184 determines whether to connect the data line DL and the sense amplifier 140B. output amplifier 140B for switching.

Next, the operation of the display driver IC of this embodiment will be described. In the following description, first, an operation of writing data to a memory cell MC (hereinafter, referred to as "the memory cell MC"), which is connected to the word line WL11, the plate line PL11, and the bit line BL11, will be described. Next, the operation of reading out the data stored in the memory cell MC and driving the display by the display drive circuit 170 will be described.

First, when data supplied to the data bus 160 is stored in the memory cell MC, the n-type MOS transistor 162 connects the data line DL1 to the data bus 160 based on the signal YSEL. Furthermore, when both the n-type MOS transistor 182 and the sense amplifier 140A are turned on, the voltage of the bit line BL11 connected to the memory cell MC is substantially equal to the voltage of the data bus 160. Then, the word line control unit 120 changes the voltage of the word line WL11, and stores predetermined data in the memory cell MC based on the voltage of the data bus 160 (for example, VCC or 0V).

In addition, the sense amplifiers 140A and 140B and the n-type MOS transistors 182 and 184 can be appropriately turned on or off according to which memory cell array the accessed memory cell MC is located on.

Next, when reading data stored in the memory cell MC, first, the word line control unit 120 turns on the word line WL11 and the dummy word line DWL2. Then, when the plate line control unit 130 raises the voltage of the plate line PL11 to VCC, the charge accumulated in the ferroelectric capacitor of the memory cell MC is discharged to the bit line BL11. At this time, the voltage rise of the bit line BL11 when data "1" is stored is higher than when data "0" is stored in the memory cell MC.

Then, when reading the data stored in the memory cell MC, the word line control unit 120 changes the voltage of the dummy word line DWL2, and the plate line control unit 130 sets the voltage of the dummy plate line DPL2 to VCC. In this way, the charge accumulated in the ferroelectric capacitor of the dummy cell DMC2 is released to the bit line BL21.

Then, after discharging charges to the bit lines BL11 and BL21, based on the voltage of the bit line BL21, the sense amplifier 140A amplifies the voltage of the bit line BL11, that is, amplifies the data stored in the memory cell MC. Specifically, when the voltage of the bit line BL11 is higher than the voltage of the bit line BL21, that is, when data "1" is stored in the memory cell MC, the sense amplifier 140A raises the voltage of the bit line BL11 to VCC. On the other hand, when the voltage of the bit line BL11 is lower than the voltage of the bit line BL21, that is, when data "0" is stored in the memory cell MC, the sense amplifier 140A makes the voltage of the bit line BL11 0V .

In addition, as explained in the second embodiment, the reference voltage is generated based on the data stored in the dummy cell DMC2, specifically, when the capacitor area of the dummy cell DMC2 is larger than the capacitor area of the memory cell MC, the dummy cell DMC2 Data "0" is stored. On the other hand, when the capacitor area of the dummy cell DMC2 is smaller than that of the memory cell MC, data "1" may also be stored in the dummy cell DMC2.

Thereafter, the n-type MOS transistors 182 and 152 are turned on, and the latch circuit 150 latches the data read from the memory cell MC to the bit line BL11. Also, the display driving circuit 170 drives an external display based on the data latched to the latch circuit 150 . Through the above operations, an external display can be driven based on data supplied from the outside.

In the above example, the operation of the display driver IC has been described by taking the memory cell MC of the memory cell array 110 as an example, but the same can be done for storing and reading data in the memory cell MC of other memory cell arrays. action. For example, the sense amplifier 140A can amplify the data stored in the memory cell array 112 with the dummy cell DMC1 as the reference, and the sense amplifier 140B can amplify the data stored in the memory cell array 116 with the dummy cell DMC3 as the reference, and , the sense amplifier 140B amplifies the data stored in the memory cell array 114 with reference to the dummy cell DMC4.

As described above, in this embodiment, the bit lines BL connected to the respective sense amplifiers 140A and 140B extend in substantially opposite directions to each other. Therefore, according to the present embodiment, the arrangement interval of the memory cells of the memory cell arrays 110 to 116 can be narrowed in the extending direction of the bit line BL, so that a highly integrated ferroelectric memory device can be provided. In particular, as in this embodiment, when this ferroelectric memory device is used in a display driver IC, the distance between the bit lines BL can be made to correspond to the distance between the external displays, and it can be reduced in the direction in which the bit lines BL extend. Display driver IC size. That is, a ferroelectric memory device and a display driver IC with very high area efficiency can be provided.

In addition, other detailed configurations and effects of this embodiment are as described in the first and second embodiments.

(fourth embodiment)

4 is a schematic diagram showing the configuration of a display driver IC according to a fourth embodiment of the present invention. The configuration and operation of the present embodiment are identical to those of the above-mentioned first embodiment, and the differences will be described below.

The ferroelectric memory device includes memory cell arrays 110, 112, word line control unit 120, plate line control unit 130, sense amplifier 140, latch circuit 150, n-type MOS transistor 152 as an example of a second switch, data Bus 160, n-type MOS transistor 162 as an example of a first switch, a plurality of bit lines BL11-1n, BL21-2n (n is an integer greater than or equal to 2. Hereinafter, referred to as "bit line BL"), A plurality of sub-bit lines SBL 11-1n, SBL 21-2n, ... (hereinafter referred to as "sub-bit lines SBL"), a plurality of word lines WL 11-1m, WL 21-2m, ... (m is 2 or more hereinafter referred to as "word line WL".), multiple plate lines PL 11~1m, PL 21~2m, ... (hereinafter referred to as "word line PL".), dummy word lines DWL 1, DWL 2 , and pseudo-plate lines DPL 1, DPL 2.

In this embodiment, a plurality of sub-bit lines SBL are connected to the bit line BL, which is applicable to all bit line structures with layers. A plurality of memory cells MC in each memory cell array 110, 112 are connected to sub-bit lines SBL, respectively. Specifically, one of the source and the drain of the n-type MOS transistor of the memory cell MC is connected to the sub-bit line SBL, and the other is connected to one end of the ferroelectric capacitor. Furthermore, the gate of the n-type MOS transistor of the memory cell MC is connected to the word line WL, and based on the potential of the word line WL, whether or not to connect one end of the ferroelectric capacitor to the corresponding sub-bit line SBL is switched.

The other end of the ferroelectric capacitor is connected to plate line PL, and predetermined data is stored based on the potential difference between the corresponding subbit line SBL and plate line PL, that is, based on the potential difference between one end and the other end of the ferroelectric capacitor.

The voltage of each sub-bit line SBL is controlled based on signals SEL11, SEL11b, . . . For example, one end of sub-bit line SBL11 is connected to bit line BL11 through a switch (for example, n-type MOS transistor 190), and the other end thereof is grounded through another switch (for example, n-type MOS transistor 192). Specifically, one of the source and the drain of the n-type MOS transistor 190 is connected to the bit line BL11, the other is connected to the sub-bit line SBL11, and the gate is connected to the signal SEL11. On the other hand, one of the source and the drain of the n-type MOS transistor 192 is grounded, the other is connected to the sub bit line SBL11, and the gate is connected to the signal SEL11b.

On each memory cell array 110, 112, dummy cells DMC1, DMC2 are provided. Specifically, dummy cell DMC1 is connected to bit lines BL 11-1n, and dummy cell DMC2 is connected to bit lines BL 21-2n. The dummy cell DMC may have the same configuration as the memory cell MC, or may have a different configuration from the memory cell MC.

In addition, in this embodiment, a sub-bit line SBL is provided, and the other configurations are as described in the first embodiment except that a plurality of memory cells MC are connected to the sub-bit line SBL.

Next, the operation of the display driver IC of this embodiment will be described. As described below, first, writing of data to a memory cell MC (hereinafter referred to as "the memory cell MC") that is connected to the word line WL11, the plate line PL11, and the sub-bit line SBL11 will be described. Next, the operation of reading out the data stored in the memory cell MC and driving the display by the display drive circuit 170 will be described.

First, when data supplied to the data bus 160 is stored in the memory cell MC, the n-type MOS transistor 162 connects the bit line BL21 to the data bus 160 based on the signal YSEL. Furthermore, when both the sense amplifier 140 and the n-type MOS transistor 190 are turned on, the voltage of the sub-bit line SBL11 connected to the memory cell MC is substantially equal to the voltage of the data bus 160. Then, the word line control unit 120 changes the voltage of the word line WL11, and stores predetermined data in the memory cell MC based on the voltage of the data bus 160 (for example, VCC or 0V).

Next, when reading data stored in the memory cell MC, first, the word line control unit 120 turns on the word line WL11 and the dummy word line DWL2. Then, when the plate line control unit 130 raises the voltage of the plate line PL11 to VCC, the charge accumulated in the ferroelectric capacitor of the memory cell MC is discharged to the sub bit line SBL11, and when the n-type MOS transistor 190 is turned on , releasing the charge to the bit line BL 22. At this time, the voltages of the sub-bit line SBLL11 and the bit line BL11 rise higher when data "1" is stored than when data "0" is stored in the memory cell MC.

Then, in the memory cell MC not being accessed, the n-type MOS transistor whose source or drain is grounded is turned on, thereby grounding the sub-bit line SBL connected to the memory cell MC not being accessed, and using the other One side supplies 0V to the plate line PL. Thus, both one end and the other end of the ferroelectric capacitor of the memory cell MC not being accessed are at ground potential, and since no electric field is applied, the data stored in the ferroelectric capacitor is retained without being destroyed.

Then, when reading data stored in the memory cell MC, the word line control unit 120 changes the voltage of the dummy word line DWL2 , and further, the plate line control unit 130 sets the voltage of the dummy plate line DPL2 to VCC. In this way, the charge accumulated in the ferroelectric capacitor of the dummy cell DMC2 is released to the bit line BL21.

Here, the implementation of setting the dummy cell DMC as the reference voltage is as described in the first and second embodiments.

Then, after the charges are discharged to the bit lines BL11 and BL21, based on the voltage of the bit line BL21, the sense amplifier 140 amplifies the voltage of the bit line BL11, that is, amplifies the data stored in the memory cell MC. Specifically, when the voltage of the bit line BL11 is higher than the voltage of the bit line BL21, that is, when data "1" is stored in the memory cell MC, the sense amplifier 140 raises the voltage of the bit line BL11 to VCC . On the other hand, when the voltage of the bit line BL11 is lower than the voltage of the bit line BL21, that is, when data "0" is stored in the memory cell MC, the sense amplifier 140 makes the voltage of the bit line BL11 0V. .

Next, the n-type MOS transistor 152 is turned on, and the latch circuit 150 latches the data read from the memory cell MC to the bit line BL11. Also, based on the data latched in the latch circuit 150, the display drive circuit 170 drives an external display. According to the above operation, an external display can be driven based on data supplied from the outside.

In the above example, the operation of the display driver IC is described by taking the memory cell MC of the memory cell array 110 as an example, but the same operation can be performed when storing data in the memory cell MC of the memory cell array 112 and reading data. . When reading data from the memory cell MC of the memory cell array 112 , the sense amplifier 140 amplifies the data read from the memory cell MC with reference to the dummy memory cell DMC1 of the memory cell array 110 .

In this embodiment, the bit lines BL11-1n and BL21-2n connected to the sense amplifier 140 extend in substantially opposite directions to each other. Therefore, according to this embodiment, the arrangement interval of the memory cells MC in the memory cell arrays 110 and 112 can be narrowed in the extending direction of the bit line BL, so that a highly integrated ferroelectric memory device can be provided. In particular, as in the present embodiment, when the ferroelectric memory device is used in a display driver IC, the interval between the bit lines BL and the external display can be made to correspond to each other, and the display can be reduced in the direction in which the bit lines BL extend. with the size of the driver IC. That is, a ferroelectric memory device and a display driver IC with very high area efficiency can be provided. Furthermore, since a plurality of sub-bit lines SBL are connected to the bit line BL, the capacitance added to the bit line BL can be further reduced. Therefore, it is further possible to provide a ferroelectric memory device that operates at a high speed and has a large read margin.

In addition, the details of other configurations and effects in this embodiment are the same as those described in the first to third embodiments.

The embodiments or application examples described in the embodiments of the invention above can be appropriately combined, modified or improved according to the application, and the present invention is not limited to the description of the above embodiments. Such combinations or modified or improved embodiments can also be included in the protection scope of the present invention, which can be clearly understood from the description of the scope of claims.

Explanation of reference signs

110, 112, 114, 116 memory cell array

120 word line control unit

130 board line control department

140, 140A, 140B sense amplifier

150 Latch circuit

152 n-type MOS transistors

160 data bus

162 n-type MOS transistors

170 display drive circuit

180, 182, 184 n-type MOS transistors

190, 192 n-type MOS transistors.

Claims (12)

1. A ferroelectric storage device, characterized in that it comprises: a first bit line extending in a first direction from one end to the other; a first storage unit, connected to the first bit line, for storing specified data; a second bit line extending from one end to the other in a direction substantially opposite to the first direction; A plurality of second memory cells connected to the second bit line for storing specified data; a sense amplifier connected to one end of the first bit line and one end of the second bit line to amplify data stored in the first memory cell and the second memory cell; a latch circuit, connected to the other end of the first bit line, for latching the data amplified by the sense amplifier; a data bus for transferring data stored by the first storage unit and the second storage unit; and A first switch, connected to the other end of the second bit line, for switching whether to connect the second bit line to the data bus. 2. The ferroelectric memory device according to claim 1, further comprising: a first dummy cell, configured between the sense amplifier and the first memory cell, and connected to the first bit line; and a second dummy cell, configured between the sense amplifier and the second memory cell, and connected to the second bit line; Wherein, the sense amplifier amplifies the data stored in the first storage unit based on the second dummy unit, and amplifies the data stored in the second storage unit based on the first dummy unit. The data in is enlarged. 3. The ferroelectric storage device according to claim 1 or 2, further comprising: a second switch disposed between the first bit line and the latch circuit, Wherein, the first switch is turned on when the sense amplifier amplifies the data stored in the first storage unit; The second switch is turned on when the sense amplifier amplifies data stored in the second memory cell. 4. A ferroelectric storage device, characterized in that it comprises: a first bit line extending in a first direction from one end to the other; A plurality of first memory cells connected to the first bit line for storing specified data; a second bit line extending from one end to the other in a second direction substantially opposite to the first direction; A plurality of second memory cells connected to the second bit line for storing specified data; a first sense amplifier connected to one end of the first bit line and one end of the second bit line to amplify data stored in the first memory cell and the second memory cell; a third bit line extending in the first direction from one end to the other; A plurality of third memory cells connected to the third bit line for storing specified data; a fourth bit line extending in the second direction from one end to the other; A plurality of fourth memory cells connected to the fourth bit line for storing specified data; a second sense amplifier connected to one end of the third bit line and one end of the fourth bit line to amplify data stored in the third memory unit and the fourth memory unit; a latch circuit, connected to the other end of the first bit line, for latching the data amplified by the respective sense amplifiers; and The switch is connected to the other end of the second bit line and the other end of the third bit line, and switches whether to connect the second bit line to the third bit line. 5. The ferroelectric memory device according to claim 4, further comprising: a data bus for transmitting the data stored from the first storage unit to the fourth storage unit; a first switch, connected to the other end of the fourth bit line, for switching whether to connect the data bus to the fourth bit line; and The second switch is arranged between the first bit line and the latch circuit. 6. The ferroelectric storage device according to claim 4 or 5, further comprising: a first dummy cell connected to the first bit line; a second dummy cell connected to the second bit line; a third dummy cell connected to the third bit line; and a fourth dummy cell connected to the fourth bit line; Wherein, the first sense amplifier amplifies the data stored in the first storage unit based on the second dummy unit, and amplifies the data stored in the second storage unit based on the first dummy unit. data in The second sense amplifier amplifies the data stored in the third storage unit with the fourth dummy cell as a reference, and amplifies the data stored in the fourth storage unit with the third dummy cell as a reference. data. 7. A ferroelectric storage device, characterized in that it comprises: a first bit line extending in a first direction from one end to the other; A plurality of first memory cells connected to the first bit line for storing specified data; a second bit line extending from one end to the other in a second direction substantially opposite to the first direction; A plurality of second memory cells connected to the second bit line for storing specified data; a first sense amplifier connected to one end of the first bit line and one end of the second bit line to amplify data stored in the first memory cell and the second memory cell; a third bit line extending in the first direction from one end to the other; A plurality of third memory cells connected to the third bit line for storing specified data; a fourth bit line extending in the second direction from one end to the other; A plurality of fourth memory cells connected to the fourth bit line for storing specified data; a second sense amplifier connected to one end of the third bit line and one end of the fourth bit line to amplify data stored in the third memory unit and the fourth memory unit; a data line extending from one end to the other in the first direction, connected to the first sense amplifier through a switch, and connected to the second sense amplifier through a switch; and The latch circuit is connected to the other end of the data line, and latches the data amplified by the respective sense amplifiers. 8. The ferroelectric memory device according to claim 7, further comprising: a data bus for transmitting the data stored from the first storage unit to the fourth storage unit; A first switch, connected to one end of the data line, switches whether to connect the data line to the data bus; and The second switch is arranged between the data line and the latch circuit. 9. The ferroelectric storage device according to claim 7 or 8, further comprising: a first dummy cell connected to the first bit line; a second dummy cell connected to the second bit line; a third dummy cell connected to the third bit line; and a fourth dummy cell connected to the fourth bit line; Wherein, the first sense amplifier amplifies the data stored in the first storage unit based on the second dummy unit, and amplifies the data stored in the second storage unit based on the first dummy unit. The data; The second sense amplifier amplifies the data stored in the third memory cell with the fourth dummy cell as a reference, and amplifies the data stored in the fourth memory cell with the third dummy cell as a reference . 10. A ferroelectric storage device, characterized in that it comprises: a first bit line extending in a first direction from one end to the other; a plurality of first sub-bit lines connected to the first bit lines; A plurality of first memory cells connected to each of the first sub-bit lines for storing specified data; a second bit line extending from one end to the other in a second direction substantially opposite to the first direction; a plurality of second sub-bit lines connected to the second bit lines; A plurality of second memory cells connected to the respective second sub-bit lines for storing specified data; a sense amplifier connected to one end of the first bit line and one end of the second bit line to amplify data stored in the first memory cell and the second memory cell; and The latch circuit is connected to the other end of the first bit line, and latches the data amplified by the sense amplifier. 11. The ferroelectric memory device according to claim 10, further comprising: a data bus for transmitting data stored by the first storage unit and the second storage unit; a first switch, connected to the other end of the second bit line, for switching whether to connect the second bit line to the data bus; and The second switch is arranged between the first bit line and the latch circuit. 12. The ferroelectric storage device according to claim 10 or 11, further comprising: a first dummy cell connected to the first bit line; and a second dummy cell connected to the second bit line; Wherein, the sense amplifier amplifies the data stored in the first storage unit based on the second dummy cell, and amplifies the data stored in the second storage unit based on the first dummy cell. data.