CN1862800A - Electronic component plane button ultra-thin packed substrate and making method thereof - Google Patents
Electronic component plane button ultra-thin packed substrate and making method thereof Download PDFInfo
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- CN1862800A CN1862800A CN 200610039919 CN200610039919A CN1862800A CN 1862800 A CN1862800 A CN 1862800A CN 200610039919 CN200610039919 CN 200610039919 CN 200610039919 A CN200610039919 A CN 200610039919A CN 1862800 A CN1862800 A CN 1862800A
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- substrate
- metal
- layer
- base island
- pin
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- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 239000002184 metal Substances 0.000 claims abstract description 85
- 238000004806 packaging method and process Methods 0.000 claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims description 4
- 239000011149 active material Substances 0.000 claims 6
- 239000013543 active substance Substances 0.000 claims 1
- 230000003213 activating effect Effects 0.000 description 23
- 239000000126 substance Substances 0.000 description 23
- 238000005253 cladding Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 2
- 230000002459 sustained effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Images
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- Led Device Packages (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本发明涉及一种电子元器件平面凸点式超薄封装基板及其制作方法，包括基岛(1)和引脚(2)，其特征在于引脚(2)呈凸点状分布于基板正面，凸点与凸点之间有金属薄层(3)连结，基岛(1)低于凸点状的引脚平面分布于基板正面；在后续封装时形成的单个电子元器件封装体内，基岛(1)的数量有一个或多个，引脚(2)排列在基岛的一侧或两侧或三侧，或围在基岛(1)的周围形成一圈或多圈引脚的结构。本发明一方面为芯片厚度争取了更大的空间，另一方面，在芯片厚度一定的前提下，使用此超薄封装基板可以使封装体做到更薄，更加符合封装体轻薄、便携的要求。
The invention relates to a plane bump type ultra-thin packaging substrate for electronic components and a manufacturing method thereof, comprising a base island (1) and pins (2), characterized in that the pins (2) are distributed on the front of the substrate in the form of bumps , there is a metal thin layer (3) connection between the bumps, and the base island (1) is lower than the bump-shaped pin plane and distributed on the front of the substrate; in the single electronic component package formed during subsequent packaging, the base There are one or more islands (1), and the pins (2) are arranged on one or both sides or three sides of the base island, or form one or more circles of pins around the base island (1). structure. On the one hand, the present invention strives for more space for the thickness of the chip; on the other hand, under the premise of a certain thickness of the chip, the use of the ultra-thin packaging substrate can make the package body thinner, which is more in line with the requirements of light, thin and portable packages .
Description
Technical field:
The present invention relates to a kind of electronic component plane button ultra-thin packed substrate and preparation method thereof.Belong to technical field of electronic components.
Background technology:
Before the present invention made, present existing flat-face saliant-point type packing base-board for electronic device mainly had the following disadvantages:
1, the Ji Dao of substrate and pin are in sustained height, equal on Ji Dao and the original thickness of pin basis again 100% thickness that has increased chip after on the Ji Dao chip being housed.This structure can cause two kinds of results: the gross thickness that the first, increases packaging body; If the second packaging body thickness is fixing, then must do further attenuate work to chip, this has proposed higher specification requirement to abrasive disc technology, otherwise this chip can't be presented in this packaging body, and then dwindled the scope of application of this packaging body.
2, Ji Dao and pin are column and are in sustained height on original planar salient point type base plate for packaging, because Ji Dao is thicker, so slowed down radiating rate.
Summary of the invention:
The objective of the invention is to overcome above-mentioned deficiency, provide that Ji Dao is lower than electronic component plane button ultra-thin packed substrate of pin height and preparation method thereof on a kind of substrate.
The object of the present invention is achieved like this: a kind of electronic component plane button ultra-thin packed substrate, comprise Ji Dao and pin, it is characterized in that pin is convex dot shape and is distributed in substrate front side, have thin metal layer to link between salient point and the salient point, Ji Dao is lower than the pin plane distribution of convex dot shape in substrate front side; In the single electronic devices and components packaging body that forms in follow-up when encapsulation, the quantity of Ji Dao has one or more, and pin arrangements is in the side of Ji Dao, or is arranged in both sides or three sides of Ji Dao, or be trapped among Ji Dao around form the structure of a circle or multi-turn pin.
Electronic component plane button ultra-thin packed substrate of the present invention, the front of described pin is provided with metal level.
Electronic component plane button ultra-thin packed substrate of the present invention, the two front of described pin and Ji Dao is or/and the back side is provided with metal level.Metal level on the Ji Dao is arranged on the part salient point or all salient points of unit Ji Dao.
Electronic component plane button ultra-thin packed substrate of the present invention, described pin just, the back side of the back of the body two sides and Ji Dao is provided with metal level.
Electronic component plane button ultra-thin packed substrate of the present invention, the front of described pin is provided with the activating substance layer, is provided with metal level on the activating substance layer.
Electronic component plane button ultra-thin packed substrate of the present invention, the two front of described pin and Ji Dao is provided with metal level or/and the back side is provided with activating substance on activating substance.
Electronic component plane button ultra-thin packed substrate of the present invention, described pin just, the back side of the back of the body two sides and Ji Dao is provided with the activating substance layer, is provided with metal level on the activating substance layer.
Manufacture method of the present invention comprises following steps:
Step 1, get a slice metal substrate,
Step 3, the part mask in metal substrate front is got rid of, is exposed the zone that preparation etches partially on metal substrate,
Remaining mask layer on step 5, the removal metal substrate is made plane button type ultra-thin packed substrate.
Manufacture method of the present invention can also comprise following steps:
Step 6, once more make metal substrate just, the surface of the back side and salient point all is covered with mask layer,
Step 7, remove the metal substrate front or/and the part mask layer at the back side, carry out the zone of metal cladding in order to expose follow-up need,
Step 8, the zone of removing mask layer in the last process is plated metal level,
Remaining mask layer on step 9, the removal metal substrate.
Manufacture method of the present invention plated the activating substance layer earlier before plating metal level.
Technology such as that the present invention has is ultra-thin, rapid heat dissipation a bit.Be specially:
1, Ji Dao is lower than the pin height on the substrate, so the bottom surface of chip can be lower than the pin end face after load on the Ji Dao: striven for bigger space for chip thickness on the one hand, make this encapsulation can break through original area requirement to chip thickness, the thicker chip of encapsulation has also reduced the pressure to chip thinning technology on original basis; On the other hand, under the certain prerequisite of chip thickness, it is thinner to use this ultra-thin packed substrate that packaging body is accomplished, meets frivolous, the portable requirement of packaging body more.
2, Ji Dao is lower than pin, compares with prior art, be equivalent to basis that original basic island floor space equates on reduced the height of Ji Dao, thereby reduced dead resistance, electric capacity and inductance, the electrical property of product is better, it is faster to dispel the heat.
Description of drawings:
Fig. 1-8 is each process sequence diagram of the present invention.
Embodiment:
Embodiment 1:
Embodiment 1 structure is shown in Fig. 8 (a), electronic component plane button ultra-thin packed substrate of the present invention, comprise basic island 1 and pin 2, pin 2 is convex dot shape and is distributed in substrate front side, have thin metal layer 3 to link between salient point and the salient point, basic island 1 is lower than pin 2 plane distribution of convex dot shape in substrate front side; In the single electronic devices and components packaging body that when follow-up encapsulation, forms, the quantity of Ji Dao can have one or more, pin can be arranged in the side of Ji Dao, also can be arranged in both sides or three sides of Ji Dao, or is trapped among the structure that forms a circle or multi-turn pin on every side of Ji Dao.
Its manufacture method comprises following steps:
Step 1, get a slice metal substrate 6, as Fig. 1,
Step 3, the part mask in metal substrate 6 fronts is got rid of, exposed the zone that preparation etches partially on metal substrate 6, as Fig. 3,
Remaining mask layer on step 5, the removal metal substrate 6 is made plane button type ultra-thin packed substrate, as Fig. 8 (a).Can do further modification processing to the plane button type ultra-thin packed substrate of making as required.
Embodiment 2:
Its manufacture method also comprises following steps on the basis of embodiment 1 method:
Step 6, once more make metal substrate 6 just, the surface of the back side and salient point all is covered with mask layer 7, as Fig. 5,
Step 7, remove the mask layer in pin 2 fronts, carry out the zone of metal cladding in order to expose follow-up need, as Fig. 6 (a),
Step 8, the zone of removing mask layer in the last process is plated metal level 4, as Fig. 7 (a),
Remaining mask layer on step 9, the removal metal substrate 6 is made plane button type ultra-thin packed substrate, as Fig. 8 (b).
Embodiment 3:
Embodiment 3 structures are shown in Fig. 8 (c), and it is on the basis of embodiment 1, and 1 the two front is provided with metal level 4 on pin 2 and basic island.
Its manufacture method also comprises following steps on the basis of embodiment 1 method:
Step 6, once more make metal substrate 6 just, the surface of the back side and salient point all is covered with mask layer 7, as Fig. 5,
Step 7, remove pin 2 and basic island 1 the two positive mask layer, carry out the zone of metal cladding in order to expose follow-up need, as Fig. 6 (b),
Step 8, the zone of removing mask layer in the last process is plated metal level 4,, step 9, remove mask layer remaining on the metal substrate 6, make plane button type ultra-thin packed substrate, as Fig. 8 (c) as Fig. 7 (b).
Embodiment 4:
Its manufacture method also comprises following steps on the basis of embodiment 1 method:
Step 6, once more make metal substrate 6 just, the surface of the back side and salient point all is covered with mask layer 7, as Fig. 5,
Step 7, remove the mask layer at the pin 2 and 1 the two back side, basic island, carry out the zone of metal cladding in order to expose follow-up need, as Fig. 6 (c),
Step 8, the zone of removing mask layer in the last process is plated metal level 4, as Fig. 7 (c),
Remaining mask layer on step 9, the removal metal substrate 6 is made plane button type ultra-thin packed substrate, as Fig. 8 (d).
Embodiment 5:
Its manufacture method also comprises following steps on the basis of embodiment 1 method:
Step 6, once more make metal substrate 6 just, the surface of the back side and salient point all is covered with mask layer 7, as Fig. 5,
Step 7, remove pin 2 just, the backside mask layer on back of the body two sides and basic island 1, carry out the zone of metal cladding in order to expose follow-up need, as Fig. 6 (d),
Step 8, the zone of removing mask layer in the last process is plated metal level 4, as Fig. 7 (d),
Remaining mask layer on step 9, the removal metal substrate 6 is made plane button type ultra-thin packed substrate, as Fig. 8 (e).
Embodiment 6:
Embodiment 6 structures are shown in Fig. 8 (f), and it is on the basis of embodiment 1, and 1 the two front and back is provided with metal level 4 on pin 2 and basic island.
Its manufacture method also comprises following steps on the basis of embodiment 1 method:
Step 6, once more make metal substrate 6 just, the surface of the back side and salient point all is covered with mask layer 7, as Fig. 5,
Step 7, remove the two front and back mask layer of pin 2 and basic island 1, carry out the zone of metal cladding in order to expose follow-up need, as Fig. 6 (e),
Step 8, the zone of removing mask layer in the last process is plated metal level 4, as Fig. 7 (e),
Remaining mask layer on step 9, the removal metal substrate 6 is made plane button type ultra-thin packed substrate, as Fig. 8 (f).
Embodiment 7:
Embodiment 7 structures are shown in Fig. 8 (g), and it is on the basis of embodiment 2, is provided with activating substance layer 5 in the front of pin 2, is provided with metal level 4 on activating substance layer 5.
Its manufacture method before the zone of removal mask layer plates metal level 4 in to last process, plates activating substance layer 5 earlier, as Fig. 7 (f), Fig. 7 (k) in the step 8 of embodiment 2 methods.
Embodiment 8:
Embodiment 8 structures are shown in Fig. 8 (h), and it is on the basis of embodiment 3, and 1 the two front is provided with activating substance layer 5 on pin 2 and basic island, is provided with metal level 4 on activating substance layer 5.
Its manufacture method before the zone of removal mask layer plates metal level 4 in to last process, plates activating substance layer 5 earlier, as Fig. 7 (g), Fig. 7 (1) in the step 8 of embodiment 3 methods.
Embodiment 9:
Embodiment 9 structures are shown in Fig. 8 (i), and it is on the basis of embodiment 4, and 1 the two the back side is provided with activating substance layer 5 on pin 2 and basic island, is provided with metal level 4 on activating substance layer 5.
Its manufacture method before the zone of removal mask layer plates metal level 4 in to last process, plates activating substance layer 5 earlier, as Fig. 7 (h), Fig. 7 (m) in the step 8 of embodiment 4 methods.
Embodiment 10:
Embodiment 10 structures are shown in Fig. 8 (j), and it is on the basis of embodiment 5, pin 2 just, the back side on the back of the body two sides and basic island 1 is provided with activating substance layer 5, is provided with metal level 4 on activating substance layer 5.
Its manufacture method before the zone of removal mask layer plates metal level 4 in to last process, plates activating substance layer 5 earlier, as Fig. 7 (i), Fig. 7 (n) in the step 8 of embodiment 5 methods.
Embodiment 11:
Embodiment 11 structures are shown in Fig. 8 (k), and it is on the basis of embodiment 6, in that 1 the two front and back is provided with activating substance layer 5 on pin 2 and basic island, are provided with metal level 4 on activating substance layer 5.
Its manufacture method before the zone of removal mask layer plates metal level 4 in to last process, plates activating substance layer 5 earlier, as Fig. 7 (j), Fig. 7 (o) in the step 8 of embodiment 6 methods.
The above-mentioned metal level 4 that covers on the basic island 1 can be part and covers or all cover.Metal level 4 is gold or silver or copper or tin or nickel or nickel palladium, and metal level can be single or multiple lift, or regional area distributes.
Above-mentioned activating substance layer 3 is nickel or palladium or nickel palladium layer.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100399197A CN100392852C (en) | 2006-04-12 | 2006-04-12 | Flat bump type ultra-thin packaging substrate for electronic components and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100399197A CN100392852C (en) | 2006-04-12 | 2006-04-12 | Flat bump type ultra-thin packaging substrate for electronic components and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN1862800A true CN1862800A (en) | 2006-11-15 |
| CN100392852C CN100392852C (en) | 2008-06-04 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100392851C (en) * | 2006-04-12 | 2008-06-04 | 江苏长电科技股份有限公司 | Planar bump type ultra-thin packaging substrate for semiconductor components and manufacturing method thereof |
| CN103646939A (en) * | 2013-12-05 | 2014-03-19 | 江苏长电科技股份有限公司 | Secondary plating-prior-to-etching metal frame subtraction imbedded chip normal-installation bump structure and process method |
| CN103646929A (en) * | 2013-12-05 | 2014-03-19 | 江苏长电科技股份有限公司 | Primary plating-prior-to-etching metal frame subtraction imbedded chip normal-installation flat pin structure and process method |
| CN103646935A (en) * | 2013-12-05 | 2014-03-19 | 江苏长电科技股份有限公司 | Secondary plating-prior-to-etching metal frame subtraction imbedded chip flip bump structure and process method |
| CN103646936A (en) * | 2013-12-05 | 2014-03-19 | 江苏长电科技股份有限公司 | Secondary plating-prior-to-etching metal frame subtraction imbedded chip flip flat pin structure and process method |
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| US4257061A (en) * | 1977-10-17 | 1981-03-17 | John Fluke Mfg. Co., Inc. | Thermally isolated monolithic semiconductor die |
| CN1059982C (en) * | 1997-08-28 | 2000-12-27 | 华通电脑股份有限公司 | Method for manufacturing integrated circuit package circuit board |
| CN1146976C (en) * | 1997-10-30 | 2004-04-21 | 株式会社日产制作所 | Semiconductor device and method for manufacturing the same |
| CN1172367C (en) * | 2000-11-02 | 2004-10-20 | 讯利电业股份有限公司 | metal base composite element |
| DE10059176C2 (en) * | 2000-11-29 | 2002-10-24 | Siemens Ag | Intermediate carrier for a semiconductor module, semiconductor module produced using such an intermediate carrier, and method for producing such a semiconductor module |
| TW544882B (en) * | 2001-12-31 | 2003-08-01 | Megic Corp | Chip package structure and process thereof |
| CN100392851C (en) * | 2006-04-12 | 2008-06-04 | 江苏长电科技股份有限公司 | Planar bump type ultra-thin packaging substrate for semiconductor components and manufacturing method thereof |
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2006
- 2006-04-12 CN CNB2006100399197A patent/CN100392852C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100392851C (en) * | 2006-04-12 | 2008-06-04 | 江苏长电科技股份有限公司 | Planar bump type ultra-thin packaging substrate for semiconductor components and manufacturing method thereof |
| CN103646939A (en) * | 2013-12-05 | 2014-03-19 | 江苏长电科技股份有限公司 | Secondary plating-prior-to-etching metal frame subtraction imbedded chip normal-installation bump structure and process method |
| CN103646929A (en) * | 2013-12-05 | 2014-03-19 | 江苏长电科技股份有限公司 | Primary plating-prior-to-etching metal frame subtraction imbedded chip normal-installation flat pin structure and process method |
| CN103646935A (en) * | 2013-12-05 | 2014-03-19 | 江苏长电科技股份有限公司 | Secondary plating-prior-to-etching metal frame subtraction imbedded chip flip bump structure and process method |
| CN103646936A (en) * | 2013-12-05 | 2014-03-19 | 江苏长电科技股份有限公司 | Secondary plating-prior-to-etching metal frame subtraction imbedded chip flip flat pin structure and process method |
| CN103646939B (en) * | 2013-12-05 | 2016-02-24 | 江苏长电科技股份有限公司 | Secondary first plates rear erosion metal frame subtraction and buries chip formal dress bump structure and process |
| CN103646936B (en) * | 2013-12-05 | 2016-06-01 | 江苏长电科技股份有限公司 | First plate for two times and lose metal frame subtraction afterwards and bury the flat leg structure of flip-chip and processing method |
| CN103646935B (en) * | 2013-12-05 | 2016-06-01 | 江苏长电科技股份有限公司 | First plate for two times and lose metal frame subtraction afterwards and bury flip-chip bump structure and processing method |
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| CN100392852C (en) | 2008-06-04 |
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Owner name: CHANGJIANG ELECTRONICS TECHNOLOGY (CHUZHOU) CO., L Free format text: FORMER OWNER: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD. Effective date: 20140219 |
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Effective date of registration: 20140219 Address after: 239000 Century Avenue, Anhui, Chuzhou, No. 999 Patentee after: Changjiang Electronics Technology (Chuzhou) Co., Ltd. Address before: 214431 Binjiang Middle Road, Jiangsu, China, No. 275, No. Patentee before: Jiangsu Changjiang Electronics Technology Co., Ltd. |