CN1862273B - A system-on-chip for testing clock signal jitter - Google Patents

Abstract

The invention relates to an on-chip system and method for testing clock signal jitter, in particular to the test of phase-locked loop jitter. High time resolution, low amplitude, differential signals are immune to component variability. A sub-threshold current control unilateral delay line, a reference delay line and a test clock delay line comprising N delay units, the sub-threshold current controls the rise of the clock signal output by each delay unit of the unilateral delay line The edge delay is equal to T/2N plus an intrinsic delay, and the falling edge delay is an intrinsic delay; it also includes an arbiter that monitors which phase of the reference clock signal and the test clock changes first, and adjusts the voltage by controlling the voltage. A delayed delay calibrator; the reference delay line provides a reference clock for the delay calibrator to calculate the intrinsic delay; when the Mth arbiter judges the test clock and the clock of the delay unit When the phases of the clocks are reversed successively, the output signal of the flipper is input in advance, and the jitter value of the clock signal is judged to be M*d.

Description

A system-on-chip for testing clock signal jitter

technical field

The invention relates to an integrated circuit on-chip test system and test method, in particular to an on-chip system and method for testing clock signal jitter, especially to a phase-locked loop jitter test system and method.

Background technique

The current main development trend of integrated circuits is high speed, low power consumption, and small area. With the continuous improvement of the speed of digital circuits, the design of high-frequency clocks has become the main contradiction. In large-scale digital integrated circuits, even more than half of the The area is used for the clock tree circuit. In order to realize high-frequency clock frequency and other designs related to high-frequency applications, a phase-locked loop circuit (PLL) is required to realize the synchronization of the clock circuit in most occasions. The meaning of phase locking is the automatic control of phase synchronization. The automatic control closed-loop system that can complete the phase synchronization of two electrical signals is a phase-locked loop, or PLL for short.

PLLs are typically used to implement the following four functions:

-Synthesize board-level clock to on-chip high-frequency clock.

-Improve noisy clocks to produce more stable low jitter clocks.

- Extract the data synchronous clock in the serial communication data.

- Generates an on-chip clock whose phase is ahead of the receive clock.

The phase-locked loop is mainly composed of a phase comparator (PC), a voltage-controlled oscillator (VCO), and a low-pass filter. The block diagram of the phase-locked loop is shown in Figure 1.

The output Uo of the voltage-controlled oscillator in Figure 1 is connected to an input terminal of the phase comparator, and the level of its output frequency is determined by the average voltage Ud established on the low-pass filter. The external input signal Ui applied to the other input terminal of the phase comparator is compared with the output signal Uo from the voltage-controlled oscillator, and the error output voltage UΨ generated by the comparison result is proportional to the phase difference between the two signals Ui and Uo, and is low-pass filtered After the high frequency component is filtered out by the filter, an average voltage Ud is obtained. This average voltage Ud changes in the direction of reducing the difference between the output frequency and the input frequency until the output frequency and the input signal frequency are identical. At this time, the frequencies of the two signals are the same, and the two phase differences remain constant (that is, synchronized), which is called phase locking.

The phase-locked loop also has the ability to "capture" the signal, which can automatically track the change of the input signal within a certain range. If the frequency of the input signal changes within the capture range of the phase-locked loop, the phase-locked loop can capture the frequency of the input signal. And locked on this frequency. If it is required that the input signal frequency f1 is not equal to the output signal frequency f2, but the two maintain a certain relationship, such as a proportional relationship or a difference relationship, you can add an arithmetic unit outside the phase-locked loop to meet the needs of different jobs. Realize the effect of increasing the frequency.

Jitter is defined as the time displacement of the position of the signal edge from its ideal position. Jitter is a key consideration that cannot be ignored in the design of digital circuits. For example, when using a buffer composed of a phase-locked loop (PLL), if the degree of time base jitter is too serious, the circuit will lose precious clock cycles in the timing design, and it will also cause data locking errors. For data transmission systems, jitter will cause errors in data transmission and reduce the overall reliability of the system.

In order to design a reasonable phase-locked loop circuit, testing is particularly important. To test a signal, a higher signal frequency than the test signal frequency is usually required. Because the PLL integrated in the circuit can achieve almost the highest frequency, it is difficult to test the PLL.

Moreover, for the on-chip integrated PLL system, it is also a very difficult process to extract the signal itself, because such a high-frequency signal will cause great distortion at the pins of the integrated circuit, because the parasitics at the pins have a large capacitive inductive effect. Using an external test instrument to test the phase-locked loop will inevitably introduce a long delay path, and the resulting delay and noise are quite large for the period of the high-frequency clock of the phase-locked loop. This is the current ATE (automatic The reason why the test instrument) cannot test the phase-locked loop well.

The solution to the problem is the built-in self-test (BIST built-in self-test) system. Place the jitter test system and the phase-locked loop under test on the same chip, that is, the test components are placed inside the integrated circuit under test, and the path is greatly shortened so that the access delay is only at the sub-nanosecond level, which will be easier Open the loop of the PLL. At the same time, the phase-locked loop can be combined in hardware, and there is no need to add a buffer driver for transmitting signals to off-chip. Adding test-specific circuits inside the chip conforms to the concept of Design for Testability (DFT), which can greatly reduce the cost and time required for production testing.

Therefore, in order to measure the jitter of the PLL circuit, it is more reasonable to implement the measurement of the PLL circuit inside the integrated circuit chip, that is, to use the on-chip test chip circuit (On-Chip Jitter Measurement Circuit for the PLL) for the jitter of the phase-locked loop. .

For integrated circuit chip designers, how to integrate the jitter measurement circuit of the phase-locked loop in the circuit is a great difficulty. Because there is no good circuit structure, the cost of phase-locked loop circuit design (especially the test cost) Very high, so designing a well-designed jitter measurement circuit will reduce the design cost very effectively.

At present, the trend of increasing system integration in the integrated circuit industry also means that the high-speed serial unit will become the standard interface module (I/O interface macro) of the chip. Therefore, techniques to efficiently test these high-speed serial transceivers are also an urgent problem to be solved.

From the perspective of measurement methodology, traditional jitter measurements can be divided into two categories: digital methods and analog methods.

The analog method is to convert each pulse width of the serial digital signal into a voltage signal, and then use a filter to filter the voltage signal. The filtered voltage change is the amount of jitter. The disadvantage of this method is the switching speed of the switch used. Greatly affect the measurement results, and high-speed switching is not easy to achieve.

The digital method is to shape the input serial digital signal first, then calculate the pulse number of the reference clock that appears in each pulse width of the shaped waveform, and then find the difference between the calculated pulse numbers as the jitter amount. The disadvantage is that when counting high frequency serial digital signals, a higher frequency reference clock must be provided.

A feasible new idea is to use delay line technology. The use of delay line technology to measure jitter is a very promising progress. The method is to use a variable delay line to obtain a normally distributed jitter, and the two points of 15.9% and 84.1% on its cumulative density function curve (CDFcurve) Delay variance, from which the standard deviation of jitter is derived. In order to solve the problem of the linearity limitation of the variable delay line, a delay line architecture that is not affected by component variability can be used, but the disadvantage is that it requires a long test time.

"Vernier Delay line" is a very novel and effective delay line measurement method. The meaning of the so-called Vernier Delay line is to use a delay line similar to the "vernier caliper" principle to measure jitter. In physics, vernier calipers are often used to measure precise lengths. The principle of vernier calipers is to use the "length difference" of the unit scale of the main scale and the vernier scale to distinguish a small length. The measurement method of the Vernier Delay line is also to construct two delay lines, and use the delay of each delay unit of the two delay lines to distinguish a small jitter. The basic principle is shown in Figure 2. We assume that "DCDC" in the figure is a delay line with a large delay, and "FDC" is a delay line with a small delay. Each delay line has N delay units. We assume that each delay unit on the DCDC delay line The delay time of is t1, and the delay time of each delay unit of the FDC delay line is t2, we set dt=t1-t2. Then, if the jitter between the two signals entering FDC and DCDC is jt, since the delays of our FDC and DCDC are different, the jitter between the two signals will gradually decrease after passing through the delay unit. The jitter is reduced by dt each time a delay cell is passed. If the jitter is reduced to 0 after n delay units, then we can know the magnitude of the jitter jt=n*dt.

Contents of the invention

The purpose of the present invention is to disclose an on-chip system and method for testing clock signal jitter, which has the advantages of high time resolution, low amplitude, differential signal not affected by component variability and long test time.

An on-chip system for testing clock signal jitter disclosed by the present invention includes a sub-threshold current-controlled unilateral delay line with N delay units, a reference delay line and a test clock delay line; it also includes an arbiter and a delay calibrator; The rising edge delay of the clock signal output by each delay unit of the sub-threshold current control unilateral delay line is d equal to T/2N plus an intrinsic delay, and the falling edge delay is an intrinsic delay , where T is the period of the input clock; the reference delay line provides a calibration reference for the delay calibrator, and at the same time allows the integrating circuit charge pump charging control circuit to have sufficient pulse width, so that the delay calibrator can give the sub-threshold single An accurate control voltage of the edge delay line; the test clock delay line drives the arbiter and makes each delay unit produce an intrinsic delay; the delay calibrator is controlled by changing the sub-threshold current The control voltage on each of the delay units of the unilateral delay line adjusts its delay; the arbiter is used to monitor the clock signal of the delay unit and the phase of the test clock of the test clock delay line, which one is first change; the reference delay line provides a reference clock for the delay calibrator to calculate the intrinsic delay; when the Mth arbiter judges that the phases of the test clock and the clock of the delay unit have occurred successively When inverting, the output signal of the flipper for advanced judgment is input, and it is judged that the jitter value of the clock signal is M*d.

The on-chip system for testing clock signal jitter disclosed by the present invention also includes the following additional technical features:

Each of the delay units of the sub-threshold current control unilateral delay line includes two connected transistors, namely an NMOS transistor and a PMOS transistor, and two pairs of a PMOS transistor and a PMOS transistor connected in series between VCC and ground. NMOS transistor; the clock VIN, the reference voltage (Vth+vdd/2) and the control voltage Vcontrol that need to be delayed for the test clock input are respectively input into two connected transistors, and the output thereof is connected to two pairs of PMOS transistors and NMOS transistors in turn, the described The control voltage Vcontrol makes the transistor work in the sub-threshold region, where Vth is the threshold voltage of the MOS transistor, and vdd is the power supply voltage.

The system-on-chip of the test clock signal jitter also includes an arbitration signal completion judge and an input lead judgment flipper, two microprocessor CPUs and an OUT CPU; after the microprocessor OUT CPU sends an instruction, the arbitrator judges Whether the phase of the test clock lags behind the reference clock, the microprocessor CPU receives the judgment completion result signal, controls the arbiter to be reset, and after the arbitration completion signal generator sends the arbitration completion signal, the microprocessor CPU Send a signal to the OUT CPU, and the microprocessor OUT CPU samples data and sends it to an external computer; so repeat.

The arbiter is realized by using a high-precision differential signal amplifier with reset control.

The generation of the control voltage Vcontrol for controlling the delay size uses an AND gate to detect the signal phase relationship output by the reference delay line and the sub-threshold current control unilateral delay line, and connects the integral formed by the NMOS transistor MJ and the capacitor C Circuit, the voltage on the capacitor C is Vcontrol.

An on-chip method for testing clock signal jitter disclosed by the present invention includes constructing a sub-threshold current-controlled unilateral delay line with N delay units, a test clock delay line and a reference delay line for driving an arbiter at the same time; constructing a delay Calibrator; test clock signal jitter includes the following steps: the first step, the circuit is powered on, and the delay calibrator judges the size of the delay according to the input test clock to change the control voltage added to each delay unit, so that the voltage The size is just enough to make the delay difference between the delay of each delay unit of the sub-threshold current control delay line and the delay unit of the test clock delay line be dt=T/2N, and the delay here refers to the delay of the rising edge; In the second step, the charging of the charge pump on the delay calibrator is completed, and the delay calibrator starts to work normally; in the third step, firstly, the OUT CPU sends an instruction to collect data, and the phase flipper determines whether the phase of the test clock lags behind the reference clock , if not, push it back half a cycle (180-degree phase); the fourth step, the CPU receives the signal, sends a signal to the arbiter, the arbiter is reset, and starts to judge; if the judgment is completed, the arbitration completion signal generator sends out Signal; the fifth step, after receiving the arbitration completion signal, the CPU sends a signal to the OUT CPU, and the OUT CPU samples the data and sends it to the external computer. After the computer receives it, it repeats from the third step.

An on-chip method for testing clock signal jitter of the present invention also includes the following technical features:

Each of the delay units of the sub-threshold current control unilateral delay line is constructed by using the principle of the logic threshold loss of the transmission gate circuit, including two connected NMOS transistors, and two pairs of NMOS transistors connected in series between VCC and ground. A PMOS transistor and an NMOS transistor; use the NMOS transistor to transmit low level, normally transmit the falling edge of the clock signal, only a small intrinsic delay; use the PMOS transistor to transmit high voltage, and make the PMOS transistor work in the subthreshold region by controlling the voltage Vcontrol , use the sub-threshold current to transmit the high level, thereby controlling the transmission time of the rising edge of the clock signal, and realizing the unilateral delay.

The test is controlled by two microprocessors CPU and OUT CPU; after the microprocessor OUT CPU sends an instruction, the arbiter determines whether the phase of the test clock lags behind the reference clock, and the microprocessor CPU receives and completes The judgment completion result signal sent by the arbitration signal generator controls the arbiter to be reset. After the arbitration completion signal generator sends the arbitration completion signal, the microprocessor CPU sends a signal to OUT CPU, and the microprocessor OUT The CPU samples the data and sends it to an external computer; repeat.

The aforementioned N is equal to ten.

The on-chip system and method for testing clock signal jitter disclosed by the present invention can meet extremely high requirements for test specifications (such as time resolution, low amplitude, differential signal); the delay unit circuit of the present invention utilizes the principle of the logic threshold value loss of the transmission gate circuit, utilizes the NMOS to transmit the low level without voltage loss, utilizes the PMOS to continue to transmit the high voltage, and controls the PMOS to work in the sub-threshold region , to achieve unilateral delay.

Description of drawings

The present invention includes following drawings:

Fig. 1 is a structural block diagram of a phase-locked loop;

Figure 2 is a schematic diagram of the Vernier Delay line for testing clock signal jitter;

Fig. 3A, 3B, 3C and 3D are the time-delay result of unilateral delay line of the present invention under different control conditions;

Fig. 4 is the circuit schematic diagram of two delay units;

Fig. 5 is a schematic diagram of the structure of the sub-threshold controlled single-sided delay line of the present invention.

FIG. 6 is a delay calibration circuit of the present invention.

Specific implementation method

The present invention will be described in further detail below in conjunction with the accompanying drawings.

The present invention adopts the Vernier Delay line measuring method to measure the jitter of the clock signal, and the present invention realizes the Vernier Delay line measuring method by adopting an analog controllable unilateral delay line. The so-called unilateral delay refers to controlling the delay line so that the rising edge of the clock passing through the delay line is retreated, while the falling edge only moves a little.

3A, 3B, 3C, and 3D are the delay results of the single-sided delay line of the present invention under different control conditions of Vcontrol. The line with hollow dots in the figure is the reference clock, while the line with solid dots is the delay result with different Vcontrol delays. Fig. 3 is the result of a schematic test about unilateral delay control. The test adopts the SPICE parameter of 0.5um LEVEL = 2. The control condition of Fig. 3A is: the control voltage Vcontrol of the PMOS transmission gate = 0, and the obtained clock rising delay The delay is Ins; the control condition of Fig. 3B is the control voltage Vcontrol=1.5v of the PMOS transmission gate, and the delay time of the clock rising delay obtained is 5ns; the control condition of Fig. 3C is the control voltage Vcontrol=1.9v of the PMOS transmission gate ; and the control condition of FIG. 3D is that the control voltage Vcontrol of the PMOS transmission gate is 2.0v, and the obtained clock rise delays are 12ns and 24ns.

As shown in Figure 4 is the circuit schematic diagram of two delay units, in which M1 (MbreakerPD) represents a PMOS transistor, M2 (MbreakerND) represents an NMOS transistor; the signal (Vth+vdd/2) is a reference voltage, where, Vdd is the power supply voltage, Vth is the threshold voltage of the MOS transistor; Vcontrol is the delay control voltage, which makes the working state of the transistor in the sub-threshold voltage region, and controls the unilateral delay by modulating this voltage; VIN is the input The clock that needs to be delayed. Each delay unit includes two connected transistors, respectively NMOS transistor and PMOS transistor, and two pairs of a PMOS transistor and an NMOS transistor connected in series between VCC and ground; clock VIN, reference voltage (Vth+vdd/ 2) Two transistors connected to the input of Vcontrol, and their outputs are sequentially connected to the above two pairs of PMOS transistors and NMOS transistors.

The delay unit circuit shown in Figure 4 utilizes the principle of the logic threshold loss of the transmission gate circuit. There is no voltage loss in NMOS transmission low level, so when the falling edge of the clock is transmitted, it can be transmitted normally, and the delay is only A small intrinsic delay. However, when NMOS transmits a high level, there is a threshold loss. After we use the control voltage of Vth+vdd/2 on the gate of the transmission gate, the voltage after passing through the NMOS transmission gate is only about vdd/2. Such a voltage can make The inverter cannot complete the inversion when it transmits a high level. To invert the state of the inverter, it is necessary to rely on the lower PMOS to continue to transmit high voltage and control the PMOS so that the PMOS works in the sub-threshold region. Only subthreshold currents can be used to transmit high levels. The sub-threshold current of a MOS is very sensitively controlled by the gate voltage, so at this time, the magnitude of the sub-threshold current can be controlled by adjusting the gate voltage, and then the PMOS can be controlled to use the sub-threshold current to transmit high levels. The time, that is, the time size of the unilateral delay we want to achieve.

It is this delay element that constitutes the delay line of the present invention.

We build a sub-threshold current delay line with N delay cells (Delay cell), for example, N=10, and use a delay calibration circuit to make the delay cells of each sub-threshold current delay line and the testing clock delay line (Testing clock delay line) The delay difference of the delay unit is dt=T/2N, where the delay refers to the delay of the rising edge, and T represents the period of the test clock. A delay unit of the sub-threshold current control unilateral delay line of the present invention is that the delay difference of the relative testing clock delay line (Testing clock delay line) delay unit of the rising edge of the signal is dt=T/2N, and drops The delay of the edge is a "natural intrinsic delay".

FIG. 5 is a schematic diagram of a system-on-chip for testing clock signal jitter of the present invention. The figure shows the structural relationship between the sub-threshold current control unilateral delay line and the testing clock delay line (Testing clock delay line). The arbiter in the figure is a monitoring unit used to monitor which delay line signal changes first. Generally, it can be realized by using a high-precision differential signal amplifier with reset control.

If it is detected in the M arbiter that the phases of the test clock and the reference clock have reversed successively, it can be known that the delay is about M*d, indicating that the measured jitter value is M*d, because d has already After calibration (d=T/2N), the jitter value d=T/2N*M.

Here, the jitter value d=T/2N*M is relative to the clock cycle "T", that is, the measurement result is relative to the accuracy of the reference clock. This relative size is more meaningful for the test of the phase-locked loop circuit, because it can test the relative size of the jitter under different clock conditions.

The present invention adopts a sub-threshold current control unilateral delay line structure, and its core key lies in three delay lines, a delay calibrator, and an arbiter circuit. Fig. 5 is a schematic structural diagram of the sub-threshold control unilateral delay line of the present invention, including a reference delay line, a sub-threshold current control unilateral delay line and a test clock delay line with n units; it also includes an input lead judgment flipper, two The CNC CPU also has an arbitration signal completion generator; when the phases of the test clock and the reference clock are reversed successively, the output signal of the flipper for advanced judgment is input.

Another key problem of the present invention is how to control the delay difference between the delay unit of the sub-threshold current control unilateral delay line and the delay unit of the testing clock delay line (Testing clock delay line) to be dt=T/2N. We use the circuit shown in Figure 6 to realize it. In the figure, the two inputs are respectively from the reference clock delay line and the subthreshold current control unilateral delay line, and the output is the control voltage Vcontrol of the subthreshold delay line. The main working principle is to use an AND gate to detect the signal phase relationship between the reference clock delay line and the sub-threshold current control single-sided delay line output. It can be known from the basic knowledge of digital logic that the output of node X is a square wave whose duty cycle is not necessarily equal to 1, and the smaller the signal phase difference output by the reference clock delay line and the sub-threshold current control unilateral delay line, the The larger the duty cycle. If the phase difference reaches 180 degrees, the duty cycle of node X is 0, that is to say, X remains low.

When the duty cycle of the X node signal is not 0, the NMOS transistor MJ can be turned on, the integrating circuit starts to work, and the voltage on the capacitor C starts to gradually increase. Since the voltage on C is the Vcontrol that controls the delay, the delay of the sub-threshold current-controlled unilateral delay line will increase due to the increase of the voltage, which will lead to the output of the reference clock delay line and the sub-threshold current-controlled unilateral delay line. The signal phase difference increases, as long as the phase difference has not increased to 180 degrees, the charging of the capacitor will continue until the voltage on the capacitor C reaches a certain value, so that the reference clock delay line and the sub-threshold current control the unilateral delay The signal phase difference of the line output is 180 degrees, the charging of the capacitor by MJ is also completed, and the voltage on the capacitor remains constant.

If we design the reference clock delay line and the test clock delay line to have the same structure, their delays are also the same. If our three delay lines all have N delay units, then the delay difference between each sub-threshold current control single-sided delay line and the test clock delay line delay unit should be dt=(D1-D2)/N, where D1 and D2 are the total delays of the subthreshold current-controlled unilateral delay line and the test clock delay line, respectively. The reference clock delay line and the test clock delay line have the same delay, so D1-D2 should be equal to the total delay difference between the subthreshold current control single-sided delay line and the reference clock delay line. Due to our calibration mechanism, the phase difference between the sub-threshold current control unilateral delay line and the reference clock delay line is 180 degrees, that is, the delay is T/2. So: dt=(D1-D2)/N=T/2N.

The working process of the whole system includes the following steps:

1. Power up the circuit, test the clock input, and the delay calibration circuit starts to work, and change the control voltage applied to each delay unit according to the size of the delay it judges, and finally make the voltage just enough to make each sub-threshold The delay difference between the delay unit of the current control delay line and the delay unit of the testing clock delay line (Testing clock delay line) is dt=T/2N, and the delay here refers to the delay of the rising edge.

2. After the circuit is powered on for a period of time, the charge pump on the delay calibrator has been charged, and the delay calibrator starts to work normally.

3. First, the OUT CPU issues an instruction to collect data, and the phase flipper determines whether the phase of the test clock lags behind the reference clock, and if not, pushes it back by half a cycle (180-degree phase).

4. The CPU receives the signal, sends a signal to the arbiter, the arbiter is reset, and begins to judge. If the judgment is completed, the arbitration completion signal generator sends out a signal.

5. After receiving the arbitration completion signal, the CPU sends a signal to the OUT CPU, and the OUT CPU samples the data and sends it to the external computer. After the computer receives the signal, repeat the step 3.

The effects of three delay lines among the present invention are respectively:

In the unilateral delay line, each unit generates a size: T/2N plus a "test clock delay line" unit's intrinsic delay, that is, the delay of the delay unit of the unilateral delay line and the test clock delay line (Testing clock delay line) The delay difference of the delay unit is dt=T/2N, and the delay here refers to the delay of the rising edge.

The function of the test clock delay line is to firstly drive the arbitrator, and secondly to cause each unit to generate an intrinsic delay.

Because the minimum delay that can be generated by the units on each single-sided delay line is the "intrinsic delay", and if this test clock delay line is not made, T/2N is likely to be less than the intrinsic delay, and the reference clock is also With the addition of delay, the delay of the delay unit of each unilateral delay line does not have to be as small as it should be. Since the delay of each test clock delay line unit is also an intrinsic delay, it is guaranteed that our single The delay of the delay unit of the side delay line can definitely be realized.

Reference clock delay line: In order for the delay calibrator to calculate the size of this intrinsic delay, it is necessary to construct such a delay line to give the delay calibrator a calibration reference, and at the same time allow the integral circuit charge pump charging control circuit to have sufficient pulse width . Allows the delay calibrator to give an accurate control voltage to the subthreshold single-sided delay line.

The core innovation idea of the present invention comprises:

1. The sub-threshold voltage is used to control the delay unit for unilateral delay, thereby controlling the delay of the "Vernier Delay line" delay unit.

2. The delay distribution of each delay unit is realized by using 3 delay lines.

3. Use a delay calibration method to generate a reasonable control voltage to control the delay.

In the system design of the present invention, each specific part also has a set of feasible ways, but way is not unique. Mainly there are two CNC CPUs, an arbitration signal completion judge, an input lead reversal judge, and several data buses.

In the sub-threshold control unilateral delay line structure of the present invention, the structure of the arbitrator can be changed, and the basic structure of the delay line can also be slightly changed. This is a content well known to those skilled in the art and belongs to the protection content of the present invention. .

Claims (5)

1. A system-on-chip for testing clock signal jitter, characterized in that it includes a sub-threshold current control unilateral delay line, a reference delay line and a test clock delay line with N delay units; it also includes an arbiter and a delay calibrator ; The rising edge of the clock signal output by each delay unit of the sub-threshold current control unilateral delay line delays the input signal as d, and its size is equal to T/2N plus an intrinsic delay, and the falling edge delay It is an intrinsic time delay, wherein T is the period of the input clock; the reference delay line provides a calibration reference for the delay calibrator, and simultaneously allows the integrating circuit charge pump charging control circuit to have enough pulse width to allow the delay calibration The device can give an accurate control voltage to the sub-threshold unilateral delay line; the test clock delay line drives the arbiter, and makes each delay unit of the test clock delay line generate an intrinsic delay; the delay calibration The arbitrator adjusts its delay by changing the control voltage added to each of the delay units of the sub-threshold current control unilateral delay line; the arbiter is used to monitor the clock signal of the delay unit and the test Which one of the phase of the test clock of the clock delay line changes first; the reference delay line provides a reference clock for the delay calibrator to calculate the intrinsic delay; when the Mth arbiter judges the test clock and the When the phases of the clocks of the delay unit are reversed successively, the output signal of the flipper for advance judgment is input, and the jitter value of the clock signal is judged to be M*d. 2. The system-on-chip of the test clock signal jitter according to claim 1, wherein each of the delay units of the sub-threshold current control unilateral delay line comprises two butted transistors, which are respectively NMOS transistors and PMOS transistors, and two pairs of a PMOS transistor and an NMOS transistor connected in series between VCC and ground; the clock VIN, the reference voltage (Vth+vdd/2) and the control voltage Vcontrol that need to be delayed for the test clock input are respectively Input two connected transistors, and its output is connected to two pairs of PMOS transistors and NMOS transistors in turn, the control voltage Vcontrol makes the working state of the transistors in the sub-threshold region, where Vth is the threshold voltage of the MOS transistor, and vdd is the power supply voltage. 3. the system-on-chip of test clock signal jitter according to claim 2, is characterized in that, also comprises arbitration signal and completes judging device and input leading judgment flipper, two microprocessor CPUs and OUT CPU; Described microprocessor OUT After the CPU issues an instruction, the arbiter determines whether the phase of the test clock lags behind the reference clock, the microprocessor CPU receives the judgment completion signal, controls the arbiter to be reset, and the arbitration completion signal generator sends an arbitration completion signal. After the signal, the microprocessor CPU sends a signal to the OUT CPU, and the microprocessor OUT CPU samples data and sends it to an external computer; so repeat. 4 . The system-on-chip for testing clock signal jitter according to claim 3 , wherein the arbiter is implemented using a high-precision differential signal amplifier with reset control. 5. the system on chip of test clock signal jitter according to claim 2, is characterized in that, the generation of the control voltage Vcontrol of described control delay size adopts an AND gate to detect described reference delay line and subthreshold current control unit The phase relationship of the signal output by the side delay line is connected to an integrating circuit composed of an NMOS transistor MJ and a capacitor C, and the voltage on the capacitor C is Vcontrol.

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