CN1860519A - Method of driving a shift register, a shift register, a liquid crystal display device having the shift register - Google Patents

Abstract

In a shift register usable in a liquid crystal display device having a large screen size and high resolution and an LCD device having the shift register, the shift register includes stages cascaded to each other, and each stage has a The carry buffer used to generate the carry signal. The pull-down transistors of each stage of the shift register are divided into first pull-down transistors and second pull-down transistors. A power voltage Vona higher than a power voltage Von applied to the clock generator is applied to the shift register. A signal delay due to an RC delay of a gate line can be minimized, a shift register is independent of a threshold voltage variation of a TFT, and image display quality can not be deteriorated.

Description

Method for driving shift register, shift register, liquid crystal display device with shift register

technical field

The present invention relates to a method of driving a shift register, a shift register, and a liquid crystal display (LCD) device having the same. More specifically, the present invention relates to a driving method, a shift register and a shift register usable in an amorphous silicon (a-Si) thin film transistor liquid crystal display device (a-Si TFT LCD) having a large display A liquid crystal display (LCD) device having the shift register.

Background technique

TFT LCD devices are divided into two types: amorphous silicon TFT LCD (or a-Si TFT LCD) devices and polysilicon TFT LCD devices. Compared with amorphous silicon TFT LCD devices, polysilicon TFT LCD (or poly-Si TFT LCD) devices have lower power consumption and low price, but are manufactured through complicated processes. Thus, polysilicon TFT LCDs are used in display devices with small display screens such as mobile phones.

Amorphous silicon TFT LCD devices can provide large display screens and high yield (or high productivity), and are used in display devices with large display screens such as laptop computers, LCD monitors, or high-definition televisions (HDTVs).

FIG. 1 is a schematic diagram illustrating a conventional polysilicon thin film transistor LCD, and FIG. 2 is a schematic diagram illustrating a conventional amorphous silicon thin film transistor LCD.

As shown in FIG. 1 , a polysilicon TFT LCD device includes a polysilicon TFT pixel array formed on a glass substrate 10 . A data driver circuit 12 and a gate driver circuit 14 are formed on a glass substrate 10 . The integrated printed circuit board 20 is connected to the terminal portion 16 through the thin film cable 18, so that the manufacturing cost of the polysilicon TFT LCD device can be reduced since the data driver circuit 12 and the gate driver circuit 14 are integrated on the glass substrate 10, and the polysilicon TFT LCD can be reduced in size. device thickness and minimize power consumption.

However, as shown in FIG. 2, in an amorphous silicon TFT LCD device, a data driver chip 34 is mounted on a flexible printed circuit board 32 through a chip on film (COF), and a data printed circuit board 36 is mounted on a flexible printed circuit board 32 through a flexible printed circuit board 32. Connect to the data line terminal on the amorphous silicon TFT pixel array. The gate driver chip 404 is mounted on the flexible printed circuit board 32 through a chip on film (COF), and the gate printed circuit board 42 is connected to gate line terminals on the amorphous silicon TFT pixel array through the flexible printed circuit board 40 .

Amorphous silicon TFT LCD devices have advantages in terms of yield (or productivity), but have disadvantages in terms of manufacturing cost and thickness.

In addition, in an amorphous silicon TFT LCD device used to display images on a large display screen with high resolution, a gate driver circuit needs to perform fast discharge. The gate lines have a capacitive load.

However, when conventional gate driver circuits are used in amorphous silicon TFT LCD devices with large display screens, deterioration of display quality may occur.

Contents of the invention

Accordingly, the present invention is provided to substantially obviate one or more problems due to limitations and disadvantages of the related art.

An aspect of the present invention is to provide a shift register that can drive an amorphous silicon TFT LCD device for displaying images on a large display screen with high resolution.

Another aspect of the present invention is to provide a liquid crystal display device having the above shift register.

Another aspect of the present invention is to provide a method of driving the above shift register.

In one aspect of the invention, a shift register comprising a plurality of cascade-connected stages is provided. The stages receive a first clock signal and a second clock signal to sequentially generate a plurality of scan line driving signals for selecting a plurality of scan lines. Each stage includes a carry buffer, a pull-up section, a pull-down section, a pull-up driver section, and a pull-down driver section. The carry buffer supplies a carry signal corresponding to the first clock signal or the second clock signal to the next stage, and the second clock signal has an opposite phase to the first clock signal. The pull-up part supplies the first scan line driving signal corresponding to the first clock signal or the second clock signal to the output terminal. The pull-down part supplies the first power supply voltage to the output terminal. The pull-up driver part turns on the pull-up part in response to a carry signal supplied from a previous stage, and turns off the pull-up part in response to a second scan line driving signal of a next stage. The pull-down driver part turns off the pull-down part in response to a carry signal supplied from a previous stage, and turns on the pull-up part in response to a second scan line driving signal of a next stage.

In another aspect of the present invention, there is provided a liquid crystal display device including a display cell array, a data driver circuit and a gate driver circuit. The display unit array is formed on a transparent substrate and includes a plurality of gate lines, a plurality of data lines and a plurality of switching elements. The switch element is coupled to the gate line and the data line. The data driver circuit supplies an image signal to each data line. The gate driver circuit includes a shift register, and the shift register includes a plurality of cascaded stages. The stages receive the first clock signal and the second clock signal to sequentially generate a plurality of gate line driving signals for selecting the gate lines. Each stage includes a carry buffer, a pull-up section, a pull-down section, a pull-up driver section, and a pull-down driver section. The carry buffer supplies a carry signal corresponding to the first clock signal or the second clock signal to the next stage, and the second clock signal has an opposite phase to the first clock signal. The pull-up part supplies a first gate driving signal corresponding to the first clock signal or the second clock signal to the output terminal. The pull-down part supplies the first power supply voltage to the output terminal. The pull-up driver part turns on the pull-up part in response to a carry signal supplied from a previous stage, and turns off the pull-up part in response to a second gate line driving signal of a next stage. The pull-down driver part turns off the pull-down part in response to a carry signal supplied from a previous stage, and turns on the pull-up part in response to a second gate line driving signal of a next stage.

In another aspect of the present invention, a method of driving a shift register is provided. The shift register includes multiple cascaded stages. The stages receive a first clock signal and a second clock signal to sequentially generate a plurality of scan line driving signals for selecting a plurality of scan lines. A carry signal corresponding to the first clock signal or the second clock signal is supplied to the next stage, and the second clock signal has a phase opposite to that of the first clock signal. Then, a first scan line driving signal corresponding to the first clock signal or the second clock signal is generated in response to the carry signal output from the previous stage. The first voltage level of the first scan line driving signal output from the current stage is lowered in response to the second scan line driving signal output from the next stage.

In another aspect of the present invention, a shift register comprising a plurality of cascaded stages is provided. The first stage receives a scan start signal, and the stages receive a first clock signal and a second clock signal to sequentially generate a plurality of scan line driving signals for selecting a plurality of scan lines. Each stage includes a first carry buffer, a pull-up section, a pull-down section, a pull-up driver section and a pull-down driver section, and a second carry buffer. The first carry buffer supplies a first carry signal corresponding to a first clock signal or a second clock signal to a next stage, and the second clock signal has a phase opposite to that of the first clock signal. The pull-up part supplies the first scan line driving signal corresponding to the first clock signal or the second clock signal to the first output terminal. The pull-down part supplies the first power supply voltage to the first output terminal. The pull-up driver part turns on the pull-up part in response to the second carry signal output from the first carry buffer of the previous stage, and turns off the pull-up part in response to the second scan line driving signal of the next stage. The pull-down driver part turns off the pull-down part in response to the first carry signal supplied from the first carry buffer of the preceding stage, and turns on the pull-up part in response to the second scan line driving signal of the next stage. The second carry buffer lowers the first voltage level of the second carry signal, and outputs the first carry signal from the first carry buffer of the previous stage to be applied to the pull-up part.

In another aspect of the present invention, there is provided a liquid crystal display device including a display cell array, a data driver circuit and a gate driver circuit. The display unit array is formed on a transparent substrate and includes a plurality of gate lines, a plurality of data lines and a plurality of switching elements. The switch element is coupled to the gate line and the data line. The data driver circuit supplies an image signal to each data line. The gate driver circuit includes a shift register, and the shift register includes a plurality of cascaded stages. The stages receive the first clock signal and the second clock signal to sequentially generate a plurality of gate line driving signals for selecting the gate lines. Each stage includes a first carry buffer, a pull-up section, a pull-down section, a pull-up driver section and a pull-down driver section, and a second carry buffer. The first carry buffer supplies a first carry signal corresponding to a first clock signal or a second clock signal to a next stage, and the second clock signal has a phase opposite to that of the first clock signal. The pull-up part supplies the first scan line driving signal corresponding to the first clock signal or the second clock signal to the first output terminal. The pull-down part supplies the first power supply voltage to the first output terminal. The pull-up driver part turns on the pull-up part in response to the second carry signal output from the first carry buffer of the previous stage, and turns off the pull-up part in response to the second scan line driving signal of the next stage. The pull-down driver part turns off the pull-down part in response to the first carry signal supplied from the first carry buffer of the preceding stage, and turns on the pull-up part in response to the second scan line driving signal of the next stage. The second carry buffer lowers the first voltage level of the second carry signal, and outputs the first carry signal from the first carry buffer of the previous stage to be applied to the pull-up part.

In another aspect of the present invention, a shift register comprising a plurality of cascaded stages is provided. The stages receive a first clock signal and a second clock signal to sequentially generate a plurality of scan line driving signals for selecting a plurality of scan lines. Each stage includes a pull-up switching device, a first pull-up driver switching device, a second pull-up driver switching device, a first pull-down switching device, a pull-down driver switching device, and a second pull-down switching device. The pull-up switching device supplies the first scan line driving signal corresponding to the first clock signal or the second clock signal to the output terminal of each stage. The first pull-up driver switching device turns on the pull-up switching device in response to a scan start signal output from a previous stage or a second scan line driving signal. The second pull-up driver switching device turns off the pull-up switching device in response to the third scan line driving signal output from the next stage. The first pull-down switching device provides a first power supply voltage to the output terminal. The pull-down driver switching device turns off the pull-down switching device in response to a scan start signal output from a previous stage or a second scan line driving signal. The second pull-down switching device is turned on in response to the third scan line driving signal to supply the first power supply voltage to the output terminal.

In another aspect of the present invention, there is provided a liquid crystal display device including a display cell array, a data driver circuit and a gate driver circuit. The display unit array is formed on a transparent substrate and includes a plurality of gate lines, a plurality of data lines and a plurality of switching elements. The switch element is coupled to the gate line and the data line. The data driver circuit supplies an image signal to each data line. The gate driver circuit includes a shift register, and the shift register includes a plurality of cascaded stages. The stages receive the first clock signal and the second clock signal to sequentially generate a plurality of gate line driving signals for selecting the gate lines. Each stage includes a pull-up switching device, a first pull-up driver switching device, a second pull-up driver switching device, a first pull-down switching device, a pull-down driver switching device, and a second pull-down switching device. The pull-up switching device supplies the first gate line driving signal corresponding to the first clock signal or the second clock signal to the output terminal of each stage. The first pull-up driver switching device turns on the pull-up switching device in response to a scan enable signal output from a previous stage or a second gate line driving signal. The second pull-up driver switching device turns off the pull-up switching device in response to a third gate line driving signal output from a next stage. The first pull-down switching device provides a first power supply voltage to the output terminal. The pull-down driver switching device turns off the pull-down switching device in response to a scan start signal output from a previous stage or a second gate line driving signal. The second pull-down switching device is turned on in response to the third gate line driving signal to supply the first power supply voltage to the output terminal.

In another aspect of the present invention, a shift register comprising a plurality of cascaded stages is provided. The stages receive a first clock signal and a second clock signal to sequentially generate a plurality of scan line driving signals for selecting a plurality of scan lines. Each stage includes a first pull-up driver switching device, a pull-up switching device, a first pull-down switching device, a second pull-down switching device, a capacitor, a second pull-up driver switching device, a third pull-up driver switching device, a first A pull-up driver switching device and a second pull-down driver switching device. The first electrode of the first pull-up driver switching device receives the second power supply voltage, the second electrode of the first pull-up driver switching device receives the scan start signal or the first scan line drive signal output from the previous stage, and the first pull-up A third electrode of the driver switching device is coupled to the first node. The fourth electrode of the pull-up switching device receives the first clock signal or the second clock signal, the fifth electrode of the pull-up switching device is coupled to the first node, and the sixth electrode of the pull-up switching device is coupled to the output terminal. A seventh electrode of the first pull-down switching device is coupled to the output terminal, an eighth electrode of the first pull-down switching device is coupled to the second node, and a ninth electrode of the first pull-down switching device receives the first supply voltage. The tenth electrode of the second pull-down switching device is coupled to the output terminal, the eleventh electrode of the second pull-down switching device receives the second gate line drive signal output from the next stage, and the twelfth electrode of the second pull-down switching device A first supply voltage is received. A capacitor is coupled between the first node and the output terminal. The thirteenth electrode of the second pull-up driver switching device is coupled to the first node, the fourteenth electrode of the second pull-up driver switching device receives the second gate line drive signal output from the next stage, and the second pull-up A fifteenth electrode of the driver switching device receives the first supply voltage. The sixteenth electrode of the third pull-up driver switching device is coupled to the first node, the seventeenth electrode of the third pull-up driver switching device is coupled to the second node, and the eighteenth electrode of the third pull-up driver switching device receives first supply voltage. The nineteenth electrode of the first pull-up driver switching device and the twentieth electrode of the first pull-up driver switching device are mutually coupled and receive the second power supply voltage, and the twenty-first electrode of the first pull-up driver switching device is coupled at the second node. The twenty-second electrode of the second pull-down driver switching device is coupled to the second node, the twenty-third electrode of the second pull-down driver switching device is coupled to the first node, and the twenty-fourth electrode of the second pull-down driver switching device receives first supply voltage.

In another aspect of the present invention, a method of driving a shift register is provided. The shift register includes a plurality of cascaded stages, and the stages receive a first clock signal and a second clock signal to sequentially generate a plurality of scan line driving signals for selecting a plurality of scan lines. A first clock signal or a second clock signal is received and provided to each stage. The first clock signal and the second clock signal substantially have a first voltage level corresponding to the first voltage level of the first supply voltage. A second power supply voltage is generated and provided to each stage. The second power supply voltage has a second voltage level higher than the first voltage level by a predetermined voltage level. A first scan line driving signal for selecting the first scan line coupled to the current stage is generated. The third voltage level of the first scan line driving signal is lowered to a fourth voltage level lower than the third voltage level in response to the second scan line driving signal output from the next stage. A first scan line driving signal having a fourth voltage level is supplied to the first scan line. After reducing the third voltage level of the first scan line driving signal, when the voltage level of the output signal of the pull-down switching device changes from the fifth voltage level to a sixth voltage level higher than the fifth voltage level, the first The fourth voltage level of a scan line driving signal is maintained for a predetermined period.

In another aspect of the present invention, a method of driving a shift register is provided. The shift register includes a plurality of cascaded stages, and the stages alternately receive a first clock signal and a second clock signal generated from a clock generator to sequentially generate a plurality of scanning line driving signals for selecting a plurality of scanning lines . The first and second clock signals substantially have a first voltage level corresponding to the first voltage level of the first supply voltage. Each stage includes a pull-up switching device, a first pull-up driver switching device, a second pull-up driver switching device, a pull-down switching device, and a pull-down driver switching device. The pull-up switching device supplies the first scan line driving signal corresponding to the first clock signal or the second clock signal to the output terminal of each stage. The first pull-up driver switching device turns on the pull-up switching device in response to a scan start signal output from a previous stage or a second scan line driving signal. The second pull-up driver switching device turns off the pull-up switching device in response to the third scan line driving signal output from the next stage. The pull-down switching device provides the third supply voltage to the output terminal. The pull-down driver switching device turns off the pull-down switching device in response to a scan start signal output from a previous stage or a second scan line driving signal. A first clock signal or a second clock signal is received and provided to each stage. A second power supply voltage is generated and provided to each stage. The second power supply voltage has a second voltage level higher than the first voltage level by a predetermined voltage level. During the period of the high level of the first clock signal or the second clock signal, a first scan line driving signal for selecting the first scan line coupled to the current stage is generated. The third voltage level of the first scan line driving signal is lowered to a fourth voltage level lower than the third voltage level in response to the third scan line driving signal output from the next stage. A first scan line driving signal having a fourth voltage level is supplied to the first scan line. After reducing the third voltage level of the first scan line driving signal, when the voltage level of the output signal of the pull-down switching device changes from the fifth voltage level to a sixth voltage level higher than the fifth voltage level, the first The fourth voltage level of a scan line driving signal is maintained for a predetermined period.

As described above, according to the shift register of the present invention, the shift register includes a plurality of stages and a carry buffer transistor for generating a carry signal. Signal delay due to RC delay of gate lines can be minimized in a liquid crystal display device having a large screen size and high resolution.

The carry signal is independent of the output signal output from the output terminal of the current stage, and is transmitted to the gate line by the carry buffer transistor located in the current stage. Therefore, the effect of the RC load due to the gate line can be prevented.

In addition, since the next stage is reset not by a gate line driving signal but by a clock signal, image display quality does not deteriorate.

In addition, in a liquid crystal display device having a large screen size and high resolution, the shift register is independent of changes in the threshold voltage of thin film transistors, so even when the threshold voltage of the thin film transistor changes due to changes in ambient temperature, the shift register Normal gate line driving signals can also be output, and abnormal operation of the shift register due to variations in the threshold voltage of the thin film transistor can be prevented.

In addition, since the shift register is independent of threshold voltage variation of the thin film transistor in a liquid crystal display device having a large screen size and high resolution, it can be enhanced.

In addition, the reliability of the shift register can be improved over a wide range of ambient temperatures.

In addition, since the tolerance of threshold voltage variation can be improved, the yield of manufacturing the shift register can be improved.

In addition, the pull-down transistor of each stage of the shift register is divided into a first pull-down transistor and a second pull-down transistor. Therefore, the transistor size of the pull-down transistor which affects the capacitive load of the inverter of the shift register can be reduced, the operation speed of the inverter can be increased, and thus the image display quality is not deteriorated.

In addition, a power supply voltage Vona higher than a power supply voltage Von applied to the clock generator is applied to the shift register, so image display quality does not deteriorate even in a liquid crystal display device having a large screen size and high resolution.

Description of drawings

The above and other advantages of the present invention will become more apparent by describing in detail preferred embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a conventional polysilicon thin film transistor LCD;

2 is a schematic diagram showing a conventional amorphous silicon thin film transistor LCD;

3 is an exploded perspective view illustrating an amorphous silicon thin film transistor LCD according to an exemplary embodiment of the present invention;

4 is a schematic diagram illustrating the amorphous silicon thin film transistor substrate of FIG. 3;

FIG. 5 is a block diagram illustrating the data driver circuit of FIG. 4;

6 is a block diagram illustrating a shift register used in the gate driver circuit of FIG. 4;

FIG. 7 is a circuit diagram illustrating stages of the shift register of FIG. 6;

FIG. 8 is a diagram illustrating scan line driving signals output from the stages of FIG. 7;

FIG. 9 is a diagram illustrating scan line driving signals output from the shift register of FIG. 6;

FIG. 10 is a schematic diagram showing the shift register and gate lines of FIG. 6;

11 is a block diagram showing a shift register used in a gate driver circuit according to a first exemplary embodiment of the present invention;

FIG. 12 is a circuit diagram showing an Nth stage in the shift register of FIG. 11;

Fig. 13 is a circuit diagram showing the last stage and a dummy stage (dummy stage) in the shift register of Fig. 11;

FIG. 14 is a schematic diagram showing the shift register and gate lines of FIG. 11;

15A and 15B are layout diagrams illustrating pull-up parts, pull-down parts and carry buffers in stages of the shift register of FIG. 11;

FIG. 15C is an enlarged view showing a carry buffer in the shift register of FIG. 15A;

16A, 16B and 16C are diagrams showing gate line drive signals output from the shift register of FIG. 7;

17 is a block diagram showing a shift register used in a gate driver circuit according to a second exemplary embodiment of the present invention;

18 is a block diagram showing a shift register used in a gate driver circuit according to a third exemplary embodiment of the present invention;

19A and 19B are graphs showing outputs of the shift register of FIG. 18;

20 is a block diagram showing a shift register used in a gate driver circuit according to a fourth exemplary embodiment of the present invention;

21 is a block diagram showing a shift register used in a gate driver circuit according to a fifth exemplary embodiment of the present invention;

Figure 22 is a graph of the voltage measured at the capacitor of Figure 21;

FIG. 23 is a diagram illustrating gate line driving signals output from the shift register of FIG. 7;

24 is a block diagram showing a unit level of a shift register used in a gate driver circuit according to a sixth exemplary embodiment of the present invention;

FIG. 25 is a diagram illustrating gate line driving signals output from the shift register of FIG. 24;

26 is a diagram illustrating a gate line driving signal output from the shift register of FIG. 7 and a gate line driving signal output from the shift register of FIG. 24;

27 is a block diagram of a power supply and a clock generator according to a seventh exemplary embodiment of the present invention;

28 is a diagram showing a gate line drive signal output from a shift register when the same power supply voltage as that applied to the clock generator of FIG. 27 is applied to the shift register;

29 is a block diagram of a power supply and a clock generator according to a seventh exemplary embodiment of the present invention;

30 is an example circuit diagram of the DC-to-DC converter of FIG. 29;

FIG. 31 is a diagram showing gate line drive signals output from the shift register when the power and clock generator of FIG. 29 drives the shift register; and

FIG. 32 is a diagram of gate line driving signals output from a shift register when the power and clock generators of FIGS. 29 and 28 drive the shift register.

Detailed ways

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is an exploded perspective view illustrating an amorphous silicon thin film transistor LCD according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , the liquid crystal display device 100 includes a liquid crystal display panel assembly 110 , a backlight assembly 120 , a chassis 130 and a cover case 140 .

The liquid crystal display panel assembly 110 includes a liquid crystal display panel 112 , a flexible printed circuit board 116 and an integrated control chip 118 . The liquid crystal display panel 112 includes a TFT substrate 112a and a color filter substrate 112b.

A display cell array, a data driver circuit, a gate driver circuit, and external connection terminals are formed on the TFT substrate 112a. A color filter and a transparent common electrode are formed on the color filter substrate 112b. The color filter substrate 112b faces the TFT substrate 112a, and liquid crystal is filled between the color filter substrate 112b and the TFT substrate 112a.

The integrated control chip 118 is electrically connected to the thin film transistors formed on the display unit array of the TFT substrate 112a through the flexible printed circuit 116 . A data signal, a data timing signal, a gate timing signal, and a power supply voltage for driving the gate driver circuit are supplied to the data driver circuit and the gate driver circuit formed on the TFT substrate 112a. The display unit array includes a plurality of gate lines, a plurality of data lines, and a plurality of switching elements, and the switching elements are respectively connected to each of the data lines and each of the gate lines. The gate driver circuit is connected to the gate lines, and drives the switching elements. The data driver circuit is connected to the data lines, and supplies image signals to the data lines.

The backlight assembly 120 includes a lamp assembly 122 , a light guide sheet 124 , a light sheet 126 , a reflection sheet 128 and a mold frame 129 .

FIG. 4 is a schematic diagram illustrating the amorphous silicon thin film transistor substrate of FIG. 3 .

Referring to Fig. 4, adopt the same process of forming TFT on TFT substrate 112a, form display cell array 150, data driver circuit 160, gate driver circuit 170 on TFT substrate 112a, be used to connect data driver circuit 160 to integrated control chip 118 external connection terminals 162 and 163 , and another external connection terminal 169 for connecting the gate driver circuit 170 to the integrated control chip 118 .

The display cell array 150 includes m data lines DL1 , DL2 , . . . , DLm and n gate lines GL1 , GL2 , . . . , GLn. The data lines DL1, DL2, . . . , DLm extend in the column direction, and the gate lines GL1, GL2, . . . , GLn extend in the row direction. For example, a liquid crystal display panel having a screen size of 2 inches is disclosed. The liquid crystal display panel has 176 data lines and 192 gate lines, thereby providing a dot resolution of 525(176×3)×192.

A switching transistor (ST; or a switching element) is formed at an intersection between the data line and the gate line. The drain of the switching transistor STi is connected to the data line DLi, the gate of the switching transistor STi is connected to the gate line GLi, and the source of the switching transistor STi is connected to the pixel electrode PE. The liquid crystal LC is located between the pixel electrode PE and the common electrode CE. The common electrode CE is formed on the color filter substrate 112b.

Accordingly, the voltage applied to the pixel electrode PE and the common electrode CE changes the alignment angle of the liquid crystal molecules, adjusts the amount of light passing through the liquid crystal molecules, and may display an image.

The data driver circuit 160 includes a shift register 164 and 528 switch transistors (SWT). Each of the 8 data line blocks BL1, BL2, . . . , BL8 includes 66 switching transistors (SWT).

The 66 input terminals of each data line block are commonly connected to the external connection terminal 163, and the 66 output terminals are respectively connected to 66 corresponding data lines. The external connection terminal 163 has 66 data input terminals. The block selection terminal is connected to an output terminal of the shift register 164 .

The sources of the 528 switching transistors (SWT) are respectively connected to the corresponding data lines, the drains of the 528 switching transistors (SWT) are respectively connected to the corresponding data input terminals, and the gates of the 528 switching transistors (SWT) are connected to the block selection terminals. Each of the 528 switching transistors (SWT) is an amorphous silicon TFT MOS transistor.

Thus, 66 data lines out of 528 data lines are divided into 8 blocks, and 8 block selection signals can sequentially select each block.

The shift register 164 receives the first clock CKH, the second clock CKHB, and the block selection enable signal STH through the external connection terminal 162 having three terminals. Each output terminal of the shift register 164 is connected to a block selection terminal of a corresponding data line block.

FIG. 5 is a block diagram illustrating a data driver circuit of FIG. 4. Referring to FIG.

Referring to FIG. 5 , the shift register 164 according to the present invention includes, for example, 9 stages SRH ₁ , SRH ₂ , . . . , SRH ₉ cascaded to each other. The output terminal OUT of each stage is connected to the input terminal IN of the next stage. These stages include 8 stages SRH ₁ , SRH ₂ , . . . , SRH ₈ and a dummy stage (SRC ₉ ). The 8 stages SRH ₁ , SRH ₂ , . . . , SRH ₈ correspond to 8 data line blocks. Each stage includes an input terminal IN, an output terminal OUT, a control terminal CT, a clock terminal CK, a first supply voltage terminal VSS, and a second supply voltage terminal VDD. The eight stages SRH ₁ , SRH ₂ , . . . , SRH ₈ provide block selection enable signals DE1, DE2, . . . , DE8 to the block selection terminals of each data line block BL1, BL2, . The block selection enable signals DE1, DE2, . . . , DE8 are enable signals for selecting each data line block.

The first clock CKH is applied to the odd stages SRH ₁ , SRH ₃ , SRH ₅ , SRH ₇ and SRH ₉ , and the second clock CKHB is applied to the even stages SRH ₂ , SRH ₄ , SRH ₆ , SRH ₈ . The first clock CKH has an opposite phase to the second clock CKHB. For example, the duty cycle of the first clock CKH and the second clock CKHB is lower than 1/66ms.

The output signal (or gate line driving signal) of the next stage is applied to the control terminal CT as a control signal.

The output signal of each stage has an active period (or a high level period) sequentially, and the data line block corresponding to the active period is selected.

The dummy stage SRH ₉ supplies a control signal to the control terminal CT of the previous stage (SRH ₈ ).

FIG. 6 is a block diagram illustrating a shift register used in the gate driver circuit of FIG. 4 .

Referring to FIG. 6 , the gate driver circuit 170 includes a shift register, and the shift register includes a plurality of stages SRC ₁ , SRC ₂ , . . . , SRC ₁₉₂ and dummy stages SRC ₁₉₃ cascaded to each other. The output terminal OUT of each stage is connected to the input terminal IN of the next stage. These stages include 192 stages SRC ₁ , SRC ₂ , . . . , SRC ₁₉₂ and pseudo-stage SRC ₁₉₃ .

Each stage includes an input terminal IN, an output terminal OUT, a control terminal CT, a clock signal input terminal CK, a first power supply voltage terminal VSS, and a second power supply voltage terminal VDD.

The first stage SRC ₁ receives a scan start signal STV through an input terminal IN. The scan start signal STV is a pulse synchronized with the vertical synchronization signal Vsync. Each stage SRC _{1 ,} SRC ₂ , . . _{. , SRC 192 generates gate line driving signals GOUT 1 , GOUT 2 ,} . , GOUT ₁₉₂ are respectively connected to the gate lines so as to select the gate lines.

The first clock signal ckv is applied to odd stages (SRC ₁ , SRC ₃ , SRC ₅ , . . . ), and the second clock signal ckvb is applied to even stages (SRH ₂ , SRH ₄ , SRH ₆ , . . . ). The first clock ckb has an opposite phase to the second clock ckvb. For example, the duty cycle of the first clock ckv and the second clock ckvb is about 16.6/192ms.

The duty cycle of the clock in the shift register 164 for the data driver circuit is about 8 times greater than the duty cycle of the clock in the shift register 170 for the gate driver circuit.

_{Output signals GOUT 1 , GOUT 2 , .}

The output signal of each stage sequentially has an active period (or a high level period), and a gate line corresponding to the active period is selected.

Pseudo-stage SRC ₁₉₃ resets (or deactivates) the last stage (SRH ₁₉₂ ). Specifically, the dummy stage SRC ₁₉₃ lowers the voltage level of the output signal of the final stage (SRC ₁₉₂ ) from a high voltage level (HIGH) to a low voltage level (LOW).

FIG. 7 is a circuit diagram illustrating stages of the shift register of FIG. 6, and FIG. 8 is a diagram illustrating scan line driving signals output from the stages of FIG. 7. Referring to FIG.

Referring to FIG. 7 , each stage of the shift register 170 includes a pull-up part 171 , a pull-down part 172 , a pull-up driver part 173 and a pull-down driver part 174 .

The pull-up part 171 includes a first NMOS transistor M1 having a drain connected to the clock signal input terminal CK, a gate connected to the first node N1, and a source connected to the output terminal GOUT[N].

The pull-down part 172 includes a second NMOS transistor M2 having a drain connected to the output terminal OUT, a gate connected to the second node N2, and a source connected to the first power supply voltage terminal VSS.

The pull-up driver section 173 includes a capacitor C and NMOS transistors M3, M4, and M5. The capacitor C is connected between the first node N1 and the output terminal GOUT[N]. The drain of the third NMOS transistor M3 is connected to the second power supply voltage VON, the gate thereof is connected to the output terminal GOUT[N-1] of the previous stage, and the source thereof is connected to the first node N1. The drain of the transistor M4 is connected to the first node N1, the gate thereof is connected to the second node N2, and the source thereof is connected to the first power supply voltage VOFF. The drain of the transistor M5 is connected to the first node N1, the gate thereof is connected to the second node N2, and the source thereof is connected to the first power supply voltage VOFF. The transistor size of the transistor M3 is about 2 times larger than that of the transistor M5.

Pull-down driver section 174 includes two NMOS transistors M6 and M7. The drain and gate of the transistor M6 are commonly connected to each other and to the second power supply voltage VON, and the source thereof is connected to the second node N2. The drain of the transistor M7 is connected to the second node N2, the gate thereof is connected to the first node N1, and the source thereof is connected to the first power supply voltage VOFF. The transistor size of transistor M6 is about 16 times larger than that of transistor M7.

As shown in FIG. 8, when the first and second clock signals ckv and ckvb and the scan start signal STV are supplied to the shift register 170, the first stage SRC1 responds to the front (start) edge of the scan start signal STV and shifts the first A high-level period of the clock signal ckv is delayed by a predetermined time of Tdr1, thereby outputting a delayed output signal GOUT1.

As described above, the shift register formed on the glass substrate receives the scan start signal STV, the first clock ckv, and the second clock ckvb, and drives the gates of the TFTs formed on the TFT substrate.

The operation of each stage of the shift register will be described below.

FIG. 9 is a diagram illustrating scan line driving signals output from the shift register of FIG. 6 .

Referring to FIG. 9 , the shift register receives a first clock signal ckv or a second clock signal ckvb, and supplies a plurality of gate line driving signals (GOUT ₁ , GOUT ₂ , GOUT ₃ , . . . ) to a plurality of gate lines. The second clock ckvb has an opposite phase to the first clock ckv. The first and second clock signals swing in a period of 2H, as shown in FIG. 9 . A signal output from a timing controller (not shown) has a voltage in the range of 0 volts to 3 volts and is amplified to have a voltage in the range of -8 volts to 24 volts, thereby obtaining the first and second clock signals .

Referring again to FIG. 7 , the output signal (or gate line driving signal) GOUT _N-1 of the previous stage charges the capacitor C and sets (or activates) the current stage. The output signal (or gate line driving signal) GOUT _N+1 of the next stage discharges the capacitor C and resets (or deactivates) the current stage.

When the first clock signal ckv, the second clock signal ckvb, and the scan start signal STV are applied to the first stage, the high level period of the first clock signal ckv is delayed by a predetermined period in response to the rising edge of the scan start signal STV to The output terminal is output as an output signal GOUT[1].

The capacitor C starts charging in response to a rising edge of the scan start signal STV input into the gate of the transistor M1 through the input terminal IN. When the voltage Vc1 charged at the capacitor C is greater than the threshold voltage of the transistor M1, the pull-up transistor M1 is turned on, and a high level period of the first clock ckv is output at the output terminal OUT.

When the high-level period of the first clock signal CKV is output at the output terminal OUT, the output voltage or the high-level period of the first clock signal ckv is bootstrap at the capacitor C, so that the gate voltage of the pull-up transistor M1 rises above the conduction voltage Von. Thus, the NMOS pull-up transistor M1 remains fully turned on. Since the transistor M3 has a transistor size about twice larger than the transistor M4, even when the transistor M4 is turned on by the scan enable signal STV, the transistor M2 is turned on.

Meanwhile, before the scan start signal STV is input into the pull-down driver part 174, the voltage of the first node N1 is raised to the second power supply voltage Von through the transistor M6, and the transistor M2 is turned on. Thus, the output signal of the output terminal OUT basically has the first power supply voltage Voff. When the scan start signal STV is input to the pull-down driver part 174, the transistor is turned on, and the voltage of the second node N2 drops to substantially the first power supply voltage Voff. Since the transistor M7 has a transistor size about 16 times larger than the transistor M6, even if the transistor M6 is turned on, the second node N2 substantially maintains the first power supply voltage Voff. Thus, the pull-down transistor M2 is turned off.

When the scan start signal STV is applied to the pull-down driver part 74, the pull-down transistor M2 is turned off, and the first clock signal ckv is delayed by the duty cycle of the first clock signal ckv to be output at the output terminal.

When the voltage of the output signal output from the output terminal OUT falls to the off voltage Voff or Vss), the transistor M7 is turned off.

Since only the second power voltage Von is supplied to the second node N2 through the transistor M6, the voltage of the second node N2 starts to increase from the first power voltage Voff to the second power voltage Von. When the voltage of the fourth node starts to rise, the transistor M4 is turned on, and the charge of the capacitor is discharged through the transistor M4. Therefore, the pull-up transistor M1 starts to turn off.

Then, since the output signal GOUT[N+1] output from the next stage rises to the on-voltage Von, the transistor M5 is turned on. Since the transistor size of the transistor M5 is about twice larger than that of the transistor M4, the voltage of the first node N1 drops to the first power voltage Voff more quickly than when only the transistor M4 is turned on.

In addition, when the voltage of the second node N2 rises to the second power supply voltage Von, the pull-down transistor M2 is turned on, and the output voltage output from the output terminal OUT changes from the on voltage Von to the off voltage Voff.

Since the second node N2 is connected to the transistor M6, even if the output signal GOUT[N+1] of the next stage applied to the control terminal CT falls to a low voltage level and the transistor M5 is turned off, the second node N2 remains at the first Two supply voltage Von. Thus, malfunction due to the turn-off of the pull-down transistor M2 is prevented.

As shown in FIG. 8 , the output signals GOUT[1], GOUT[2], GOUT[3], . . . are sequentially generated.

As described above, the capacitor C is charged in response to the output signal of the previous stage, and the clock signal applied to the pull-up part or the pull-down part is output as the output signal of the current stage. When the output signal of the next stage is generated on the gate line connected to the output terminal of the next stage, the output signal of the next stage turns on the discharge transistor M5, and discharges the capacitor C, thereby terminating the operation cycle of the shift register .

The shift register described above is used as a gate driver circuit in a liquid crystal display device having a small or medium display size, but it cannot be used as a display device with a large display due to RC delay due to resistance and capacitance present in the gate line. A gate driver circuit in a liquid crystal display device.

As shown in FIG. 6, each stage receives the first clock ckv or the second clock ckvb having a period of 2H, and applies the first clock ckv or the second clock ckvb to the gate line.

Specifically, the Nth stage receives the (N-1)th gate turn-on voltage (or (N-1)th gate line drive signal) through the input terminal, and responds to the (N-1)th gate turn-on voltage Thus, an Nth gate turn-on voltage (or an Nth gate line driving signal) is generated. The Nth stage receives the (N+1)th gate line driving signal through the control terminal, and supplies the gate turn-off voltage to the gate line in response to the (N+1)th gate line driving signal.

Since the (N−1)th gate turn-on voltage is electrically coupled to the (N−1)th gate line, the load of the (N−1)th gate line electrically affects the input terminal of the Nth stage. Therefore, a signal delay is generated, and each stage is affected by the load of the gate line.

As shown in FIG. 10 , each gate line has multiple resistive elements and multiple capacitive elements, and the input terminal of the Nth stage receives the (N−1)th output signal of the (N−1)th stage. Since the input terminal of the Nth stage is connected to the (N−1)th gate line, signal delay (eg, RC delay) may occur due to RC load of the gate line.

In addition, since each stage is cascaded with each other, the signal delay is caused by the preceding gate line (first gate line) connected to the preceding stage (first stage, second stage, ..., (N-1)th stage) , the second gate line, . Therefore, display quality may be seriously deteriorated. In a liquid crystal display device with a small or medium screen size, since the RC load of the gate line is small and the period of the display gate conduction voltage is long, the signal delay may not cause the above-mentioned seriously deteriorated display quality. However, in a liquid crystal display device having a large screen size, signal delay can lead to the above-mentioned severely deteriorated display quality.

An external signal may be used instead of the gate line driving signal output from the previous stage to activate (or set) the next stage.

FIG. 11 is a block diagram showing a shift register used in a gate driver circuit according to a first exemplary embodiment of the present invention.

Referring to FIG. 11 , the gate driver circuit according to the first exemplary embodiment of the present invention includes a plurality of stages SRC ₁ , SRC ₂ , SRC ₃ , . . . , SRC _N , SRC _N+1 and a plurality of carry Buffers CB ₁ , CB ₂ , . . . , CB _N . Carry buffers CB ₁ , CB ₂ , . . . , CB _N are interposed between two adjacent stages. The output terminal OUT of each stage is connected to the input terminal IN of the next stage. These stages include N stages SRC ₁ , SRC ₂ , SRC ₃ , . . . , SRC _N and a dummy stage SRC _N+1 .

Each stage includes an input terminal IN, an output terminal OUT, a control terminal CT, a clock signal input terminal CK, a first power supply voltage terminal VSS, a second power supply voltage terminal VDD, and a carry output terminal CRR.

The first stage SRC ₁ receives a scan start signal STV through an input terminal IN. The scan start signal STV is a pulse signal synchronized with a vertical synchronization signal Vsync supplied from an external graphics controller (not shown).

The stages SRC ₂ , . . . , SRC _N receive the carry voltage supplied from the carry output terminal CRR of the previous stage through the carry buffer.

Each stage SRC _{1 ,} SRC ₂ , . . _{. , SRC 192 generates gate line driving signals GOUT 1 , GOUT 2 ,} . , GOUT ₁₉₂ are respectively connected to the gate lines so as to select the gate lines.

The first clock signal ckv is applied to odd stages (SRC ₁ , SRC ₃ , SRC ₅ , . . . ), and the second clock signal ckvb is applied to even stages (SRH ₂ , SRH ₄ , SRH ₆ , . . . ). The first clock ckb has an opposite phase to the second clock ckvb. For example, the duty cycle of the first clock ckv and the second clock ckvb is about 16.6/192ms.

The duty cycle of the clock in the shift register 164 for the data driver circuit is about 8 times greater than the clock in the shift register 170 for the gate driver circuit.

The output signals GOUT ₂ , . . . , GOUT ₁₉₂ of the next stages SRC ₂ , SRC ₃ , SRC ₄ are respectively applied as control signals to the control terminals CT of the stages SRC ₁ , SRC ₂ , SRC ₃ .

The carry buffers CB ₁ , CB ₂ , . . . , CB _N use a clock signal supplied from an external power source instead of a gate line driving signal output from a previous stage as a carry signal in order to activate (or set) the next stage. A carry buffer CB ₁ , CB ₂ , . . . , CB _N may be installed inside each stage.

FIG. 12 is a circuit diagram showing an Nth stage in the shift register of FIG. 11 .

Referring to FIG. 12 , each stage of the shift register includes a pull-up part 171 , a pull-down part 172 , a pull-up driver part 173 , a pull-down driver part 174 and a carry buffer 275 .

The pull-up part 171 includes a first NMOS transistor M1, the drain of which is connected to the clock signal input terminal CK, the gate of which is connected to the first node N1, and the source of which is connected to the output terminal GOUT[N].

The pull-down part 172 includes a second NMOS transistor M2, the drain of which is connected to the output terminal GOUT[N], the gate of which is connected to the second node N2, and the source of which is connected to the first power supply voltage terminal VSS.

The pull-up driver section 173 includes a capacitor C and NMOS transistors M3, M4, and M5. The capacitor C is connected between the first node N1 and the output terminal GOUT[N]. The drain of the third NMOS transistor M3 is connected to the second power supply voltage VON, the gate thereof is connected to the output terminal GOUT[N-1] of the previous stage, and the source thereof is connected to the first node N1. The drain of the transistor M4 is connected to the first node N1, the gate thereof is connected to the second node N2, and the source thereof is connected to the first power supply voltage VOFF. The drain of the transistor M5 is connected to the first node N1, the gate thereof is connected to the second node N2, and the source thereof is connected to the first power supply voltage VOFF. The transistor size of the transistor M3 is about 2 times larger than that of the transistor M5.

Pull-down driver section 174 includes two NMOS transistors M6 and M7. The drain and gate of the transistor M6 are commonly connected to each other and to the second power supply voltage VON, and the source thereof is connected to the second node N2. The drain of the transistor M7 is connected to the second node N2, the gate thereof is connected to the first node N1, and the source thereof is connected to the first power supply voltage VOFF. The transistor size of transistor M6 is about 16 times larger than that of transistor M7.

The carry buffer 275 includes a carry buffer transistor TR1, and outputs the first clock ckv or the second clock ckvb to the next stage. Specifically, the gate of the carry buffer transistor TR1 is connected to the input terminal of the pull-down driver section 174, the drain of the carry buffer transistor TR1 is connected to the clock terminal CKV or CKVB, and the source of the carry buffer transistor TR1 is connected to the lower The gate of the third transistor M3 of the pull-up part 173 of the first stage.

The carry buffer transistor TR1 of the previous stage receives the first clock ckv or the second clock ckvb, and transmits the first clock ckv or the second clock ckvb as a carry signal to the current stage. Since a clock signal having a substantially uniform voltage level is used as a carry signal, an RC delay due to an RC load of a gate line may not occur.

FIG. 13 is a circuit diagram showing a final stage and a dummy stage in the shift register of FIG. 11 .

Referring to FIG. 13 , each stage of the shift register includes a pull-up part 171 , a pull-down part 172 , a pull-up driver part 173 , a pull-down driver part 174 and a carry buffer 275 . In FIG. 13, the same reference numerals denote the same elements in FIG. 12, and thus detailed descriptions of the same elements will be omitted.

As shown in Figure 13, since the output signal of the previous stage is affected by the RC load of the gate line, the output signal of the previous stage is not applied to the input terminal of each stage, and the clock signal is applied to each stage as a carry signal. level input terminals. Therefore, since the clock signal used as the carry signal is independent from the output signal of the previous stage, RC delay due to RC load of the gate line may not occur.

Hereinafter, the upper stage of FIG. 13 is referred to as the previous stage SRC _N , and the lower stage of FIG. 13 is referred to as the current stage SRC _N+1 in order to describe the operation of the shift register of the present invention.

The carry buffer transistor TR1 of the previous stage SRC _N receives the first clock ckv (or the control signal of the pull-up transistor M1) for activating (or setting) the current stage SRC _N+1 , and basically uses the first clock ckv as The carry signal is transmitted to the current stage SRC _N+1 . Since the clock signal ckv having a substantially uniform voltage level is used as a carry signal, RC delay due to RC load of the gate line may not occur.

Before the carry signal CA[N] is applied to the gate of the third transistor M3, the third transistor M3 remains in an off state. When the carry signal CA[N] is applied to the gate of the third transistor M3, the third transistor M3 is turned on after a predetermined period to form a current path through which the capacitor C is charged with the second power supply voltage Von.

When the clock ckv having a low level or the voltage level of the first power voltage Voff is applied to the gate of the third transistor M3, the third transistor M3 is turned off.

FIG. 14 is a schematic diagram illustrating the shift register and gate lines of FIG. 11 .

14, each stage (SRC ₁ , SRC ₂ , SRC ₃ , . . . ) applies a plurality of gate line driving signals (GOUT ₁ , GOUT ₂ , GOUT ₃ , . . . ) to select the gate lines of the liquid crystal display panel 150 .

In addition, each stage (SRC ₁ , SRC ₂ , SRC ₃ , . . . ) applies a carry signal to the input terminal of the next stage through the carry output terminal CA. The carry signal is the first clock ckv or the second clock ckvb. The first clock ckv or the second clock ckvb is supplied from an external power source and is independent of each stage. The second clock ckvb has an opposite phase to the first clock ckv.

Since the carry signal output from the carry output terminal of the previous stage is applied to the input terminal of the current stage instead of the gate line drive signal output from the output terminal OUT of the previous stage to activate the current stage, it is possible to prevent the RC due to the gate line. Display quality deterioration due to load.

15A and 15B are layout diagrams showing the pull-up part, the pull-down part and the carry buffer in the stages of the shift register of FIG. 11, and FIG. 15C is an enlargement showing the carry buffer in the shift register of FIG. 15A picture.

The transistor size of the pull-up NMOS transistor M1 and the pull-down NMOS transistor M2 of FIG. polar line.

As shown in FIGS. 15A, 15B and 15C, a gate wiring (gate wiring) and an active pattern (active pattern) are sequentially formed in a predetermined area on an insulating substrate, and a 'branch' shape (or 'finger' shape) to form multiple drain electrodes and multiple source electrodes to form pull-up transistors (M1[N] and M1[N+1]) and pull-down transistors (M2[N] and M2[N+1] ). The gate wiring includes a gate electrode (or gate electrodes) and a gate line (or gate lines). M1[N] is the pull-up transistor M1 of the Nth stage, and M1[N+1] is the pull-up transistor M1 of the (N+1)th stage. M2[N] is the pull-down transistor M2 of the Nth stage, and M2[N+1] is the pull-down transistor M2 of the (N+1)th stage. In the 'branch' type shape of the present invention, the drain electrodes are branched from the main drain wiring, and each drain electrode is inserted into a branch of each drain electrode. For example, the active pattern is composed of amorphous silicon. Hereinafter, the Nth stage is referred to as the current stage, and the (N+1)th stage is referred to as the next stage.

Specifically, gate wirings of the pull-up transistors (M1[N] and M1[N+1]) are formed in a first predetermined area defining a first predetermined area. For example, the first predetermined area may have a rectangular shape. Active patterns of the pull-up transistors (M1[N] and M1[N+1]) are formed on gate wirings of the pull-up transistors (M1[N] and M1[N+1]). The drain electrodes of the pull-up transistors (M1[N] and M1[N+1]) are branched from the main drain wiring 300 extending in the downward direction, and the drain electrodes of the pull-up transistors (M1[N] and M1[N+1] ) formed on the active pattern. Each source of the pull-up transistors (M1[N] and M1[N+1]) is formed between branches (drain lines) of the drain electrodes. That is, each branch (source line) of the source electrode is formed between branches (or drain lines) of the drain electrode. The source electrodes of the pull-up transistors (M1[N] and M1[N+1]) may also be formed outside the drain electrodes of the pull-up transistors (M1[N] and M1[N+1]). Each source electrode of the pull-up transistors (M1[N] and M1[N+1]) is electrically connected to a gate line through a contact hole (CNT1, CNT2). For example, each drain line may have a width of about 5 μm, and each gate line may have a width of about 5 μm. For example, the width of the main drain line may be greater than about 5 μm. The smaller the distance (L) between the drain line and the source line, the better the characteristics of the thin film transistor (TFT). For example, the smaller the distance (L) between the drain line and the source line, the larger the transistor size (W/L).

Specifically, gate wirings of the pull-down transistors (M2[N] and M2[N+1]) are formed in a second predetermined area defining a second predetermined area. For example, the second predetermined area may have a rectangular shape. Active patterns of pull-down transistors (M2[N] and M2[N+1]) are formed on gate wirings of the pull-down transistors (M2[N] and M2[N+1]). The drain electrodes of the pull-down transistors (M2[N] and M2[N+1]) are branched from the main drain wiring 300 extending in the upward direction, and formed at the pull-down transistors (M2[N] and M2[N+1]) on the active pattern. Each drain electrode of the pull-down transistors (M2[N] and M2[N+1]) is electrically connected to a gate line through a contact hole (CNT1, CNT2). Each source electrode of the pull-down transistors (M2[N] and M2[N+1]) is formed between branches (or drain lines) of the drain electrodes. That is, each branch (or source line) of the source electrode is formed between branches (or drain lines) of the drain electrode. The source electrodes of the pull-up transistors (M2[N] and M2[N+1]) may also be formed outside the drain electrodes of the pull-up transistors (M2[N] and M2[N+1]).

Specifically, the plurality of source electrodes of the pull-up transistors (M1[N] and M1[N+1]) and the plurality of drain electrodes of the pull-down transistors (M2[N] and M2[N+1]) are commonly connected to the first A contact hole CNT1, so that the source electrodes of the pull-up transistors (M1[N] and M1[N+1]) and the drain electrodes of the pull-down transistors (M2[N] and M2[N+1]) can be commonly connected to gate line. Since the height of the source electrode of the pull-up transistor (M1[N] and M1[N+1]) or the height of the source electrode of the pull-down transistor (M2[N] and M2[N+1]) is different from the height of the gate line , so the source electrodes of the pull-up transistors (M1[N] and M1[N+1]) or the pull-down transistors (M2[N] and M2[N+1]) pass between the first indium tin oxide (ITO1) layer and the second A bridge formed between the two contact holes CNT2 is connected to a gate line. The first indium tin oxide (ITO1) layer includes a conductive material. The first indium tin oxide (ITO1) layer is connected to the first contact hole CNT1.

A carry buffer transistor TR1 is formed adjacent to the pull-up transistor M1 so as to supply the first clock ckv or the second clock ckvb applied to the drain electrode of the pull-up transistor M1 of the current stage to the third clock of the next stage. Gate electrode of transistor M3.

Specifically, the gate electrode of the carry buffer transistor TR1 is commonly connected to the gate electrodes of the pull-up transistors (M1[N] and M1[N+1]). The drain electrode of the carry buffer transistor TR1 may branch from the main drain wiring of the pull-up transistors (M1[N] and M1[N+1]). The source electrode of carry buffer transistor TR1 bypasses (bypasses) the pull-up transistors (M1[N] and M1[N+1]) and pull-down transistors (M2[N] and M2[N+1]) to extend to The gate electrode of the third transistor M3 of the next stage.

Since the height of the branch (or source line) of the source electrode of the carry buffer transistor TR1 is different from the height of the gate wiring connected to the gate electrode of the third transistor M3 of the next stage, the source electrode of the carry buffer transistor TR1 The gate wiring connected to the gate electrode of the third transistor M3 is connected through a bridge formed between the second indium tin oxide (ITO2) layer and the fourth contact hole CNT4. The second indium tin oxide (ITO2) layer includes a conductive material. The second indium tin oxide (ITO2) layer is connected to the source line of the carry buffer transistor TR1 through the third contact hole CNT3.

The shift registers of Figures 7 and 8 are used in liquid crystal display panels with small or medium screen sizes such as 525 (176 x 3) x 192, but the shift registers of Figures 7 and 8 cannot be used for large screens due to signal delay issues. screen size of the LCD panel.

The transistor size of the pull-up or pull-down transistor (M1 or M2) needs to be increased so that the shift register of FIGS. 7 and 8 can be used in a liquid crystal display panel with a large screen size. However, there is a limit to increase the transistor size of the pull-up or pull-down transistor (M1 or M2) due to the limit of the chip area of the shift register.

Therefore, the reliability and yield of manufacturing liquid crystal display devices may not be guaranteed because the threshold voltage of the thin film transistor varies due to the limitation of the transistor size of the pull-up or pull-down transistor (M1 or M2) and the characteristics of the amorphous silicon thin film transistor .

16A, 16B and 16C are diagrams illustrating gate line driving signals output from the shift register of FIG. 7 .

Referring to FIG. 16A , when the thin film transistors of the shift register have normal threshold voltages at room temperature, the gate line driving signals (GOUT ₁ , GOUT ₂ , GOUT ₃ , . . . ) are similar to square waves and have an Consistent peak voltage levels.

Referring to FIG. 16B, the threshold voltage of the thin film transistor of the shift register decreases as the temperature increases, and the gate line driving signals (GOUT' ₁ , GOUT' ₂ , GOUT' ₃ , ...) are similar to square waves, but The gate line drive signals (GOUT' ₁ , GOUT' ₂ , GOUT' ₃ , . . . ) have reduced peak voltage levels. That is, the peak voltage level of the first gate line driving signal _GOUT'1 has about 20 volts, and the peak voltage level of the second gate line driving signal _GOUT'2 is lower than 20 volts.

As shown in FIG. 16B, an override signal whose waveform is like a spark is applied to a specific gate line. The gate line driving signals (GOUT' ₁ , GOUT' ₂ , GOUT' ₃ , . . . ) have reduced peak voltage levels due to overlapping signals, so that the gate line driving signals having abnormal waveforms are generated.

Referring to FIG. 16C , the threshold voltage of the thin film transistor of the shift register increases as the temperature decreases, and the gate line driving signals (GOUT" ₁ , GOUT" ₂ , GOUT" ₃ , ...) are not similar to square waves, And the gate line drive signals (GOUT" ₁ , GOUT" ₂ , GOUT" ₃ , . . . ) have reduced peak voltage levels. That is, the peak voltage level of the first gate line driving signal GOUT" ₁ has about 22 volts, and the peak voltage level of the second gate line driving signal GOUT" ₂ is lower than 22 volts.

When the thin film transistor of the shift register has a normal threshold voltage at room temperature, the shift register works normally, and the gate line driving signal output from the shift register is similar to a square wave and has a consistent peak voltage level.

However, when the threshold voltage of the thin film transistor of the shift register changes as the temperature decreases (or increases), the gate line driving signal output from the shift register has an abnormal waveform, or a uniform peak voltage level. Therefore, the gate line drive signal having an abnormal waveform does not normally turn on the switching device (switching element) on the liquid crystal display panel, and the display quality of the liquid crystal display device deteriorates.

As shown in Figure 6, the shift register has a circuit structure in which the gate line drive signal output from the previous stage affects the gate line drive signal output from the current stage, especially in liquid crystal display devices with a large display screen size Among them, when the threshold voltages of the respective thin film transistors of the shift register are switched and each stage is sequentially driven by the shift register, some stages may not output gate line driving signals.

FIG. 17 is a block diagram showing a shift register used in a gate driver circuit according to a second exemplary embodiment of the present invention.

Referring to FIG. 17 , each stage of the shift register includes a pull-up part 171 , a pull-down part 172 , a pull-up driver part 173 , a pull-down driver part 174 , a first carry buffer 275 and a second carry buffer 276 . In FIG. 17, the same reference numerals denote the same elements in FIG. 7, and thus detailed descriptions of the same elements will be omitted.

The first carry buffer 275 includes a first carry buffer transistor TR1, and outputs the first clock ckv or the second clock ckvb to the next stage.

Specifically, the gate of the first carry buffer transistor TR1 is connected to the input terminal of the pull-down driver section 174, the drain of the first carry buffer transistor TR1 is connected to the clock terminal CKV or CKVB, and the first carry buffer transistor TR1 The source of is connected to the second carry buffer 276 of the next stage.

The second carry buffer 276 includes a second carry buffer transistor TR2 controlled by the pull-down driver section 174 or an inverter. Specifically, the buffer transistor M3 is turned on by the first clock ckv or the second clock ckvb supplied from the first carry buffer 275 to be applied to the pull-up part 171, and then the output of the pull-down driver part 174 (or inverter) The voltage has a low voltage level, and the second carry buffer 276 is turned off. Therefore, when the carry signal is transmitted to the second carry buffer transistor TR2, the voltage level of the carry signal may not be lowered.

The drain of the second carry buffer transistor TR2 is connected to the input terminal of the pull-up driver part 173 of the current stage, and is also connected to the source of the first carry buffer transistor TR1. The gate of the second carry buffer transistor TR2 is connected to the gate of the second transistor M2 or the pull-down part 172, and the source of the second carry buffer transistor TR2 receives the first power voltage through the first power voltage terminal VOFF.

In addition, after the 1H period, the second carry buffer transistor TR2 maintains the on state while the pull-down driver part 174 is turned on, and the first power supply voltage Voff is applied to the buffer transistor M3 to turn off the buffer transistor M3. The first supply voltage terminal VOFF is the same as the supply voltage terminal VSS of FIG. 5 .

Since the clock signal is used instead of the gate line driving signal output from the previous stage as the carry signal, the gate line driving signal output from each stage is independent of the gate line driving signal of the previous stage.

Hereinafter, the upper stage of FIG. 17 is referred to as the previous stage SRC _N , and the lower stage of FIG. 17 is referred to as the current stage SRC _N+1 in order to describe the operation of the shift register of the present invention.

The carry buffer transistor TR1 of the previous stage SRC _N receives the first clock ckv or the second clock ckvb, and transmits the first clock ckv or the second clock ckvb as a carry signal to the current stage SRC _N+1 . Since a clock signal having a substantially uniform voltage level is used as a carry signal, an RC delay due to an RC load of a gate line may not occur.

Before the carry signal CA[N] is applied to the gate of the third transistor M3, the third transistor M3 remains in an off state. When the carry signal CA[N] is applied to the gate of the third transistor M3, after a predetermined period, the third transistor M3 is turned on to form a current path through which the capacitor C is charged with the second power supply voltage Von.

When charging the capacitor C of the pull-up driver part 173 of the current stage, the second carry buffer transistor TR2 is turned off. When the current stage has an idle state, the power supply voltage Voff applied to the second carry buffer transistor TR2 is applied to the gate of the buffer transistor M3 and maintains the off state of the buffer transistor M3.

Specifically, the third transistor M3 of the pull-up driver part 173 of the previous stage maintains an off state, and when a carry signal is applied to the third transistor M3 through the first carry buffer transistor TR1 of the previous stage, it becomes idle. state. Accordingly, the gate of the third transistor M3 has a voltage level corresponding to the divided voltage formed by the resistance of the first carry buffer transistor TR1 and the resistance of the second transistor M2.

When the second carry buffer transistor TR2 is turned off and a carry signal such as a clock signal is applied to the gate of the buffer transistor M3, the buffer transistor M3 is turned on, and the voltage Von is applied to the capacitor C.

FIG. 18 is a block diagram showing a shift register used in a gate driver circuit according to a third exemplary embodiment of the present invention.

Referring to FIG. 18 , each stage of the shift register includes a pull-up part 171 , a pull-down part 172 , a pull-up driver part 173 , a pull-down driver part 174 , a first carry buffer 275 and a second carry buffer 376 . In FIG. 18, the same reference numerals denote the same elements in FIG. 7, and thus detailed descriptions of the same elements will be omitted.

The first carry buffer 275 includes a first carry buffer transistor TR1, and outputs the first clock ckv or the second clock ckvb to the next stage.

Specifically, the gate of the first carry buffer transistor TR1 is connected to the input terminal of the pull-down driver section 174, the drain of the first carry buffer transistor TR1 is connected to the clock terminal CKV or CKVB, and the source of the carry buffer transistor TR1 The pole is connected to the second carry buffer 376 of the next stage.

The second carry buffer 376 includes second and third carry buffer transistors TR2 and TR3. Specifically, when the output of the pull-down driver section 174 (or inverter) has a low voltage level, the second carry buffer 376 is turned off. Therefore, when the carry signal is transmitted to the second carry buffer 376, the voltage level of the carry signal may not be lowered. In addition, after the 1H period, the second carry buffer 376 remains on, while the pull-down driver section 174 is turned on, so as to turn off the buffer transistor M3.

The drain of the second carry buffer transistor TR2 is connected to the input terminal of the pull-up driver part 173 of the current stage, and is also connected to the source of the first carry buffer transistor TR1 of the previous stage. The gate of the second carry buffer transistor TR2 is connected to the gate of the second transistor M2 or the pull-down part 172, and the source of the second carry buffer transistor TR2 is connected to the drain of the third carry buffer transistor TR3. The first supply voltage terminal VOFF is the same as the supply voltage terminal VSS of FIG. 5 .

Hereinafter, the upper stage of FIG. 18 is referred to as the previous stage SRC _N , and the lower stage of FIG. 18 is referred to as the current stage SRC _N+1 in order to describe the operation of the shift register of the present invention.

The carry buffer transistor TR1 of the previous stage SRC _N receives the first clock ckv, and transmits the first clock ckv as a carry signal to the current stage SRC _N+1 . Since the clock signal has a substantially uniform voltage level, RC delay due to RC load of the gate line may not occur.

When charging the capacitor C of the pull-up driver part 173 of the current stage, the second carry buffer transistor TR2 is turned off. When the current stage has an idle state, the voltage (Voff+Vth) of the third carry buffer transistor TR3 is applied to the gate of the buffer transistor M3, and the off state of the buffer transistor M3 is maintained.

Specifically, the third transistor M3 of the pull-up driver part 173 of the previous stage maintains an off state, and when a carry signal is applied to the third transistor M3 through the first carry buffer transistor TR1 of the previous stage, it becomes idle. state. Accordingly, the gate of the third transistor M3 has a voltage level corresponding to a divided voltage formed by the resistance of the first carry buffer transistor TR1, the resistance of the second carry buffer transistor TR2, and the threshold voltage of the third carry buffer transistor TR3. flat.

When the second carry buffer transistor TR2 is turned off and a carry signal is applied to the gate of the buffer transistor M3, the buffer transistor M3 is turned on, and the voltage Von is applied to the capacitor C.

When a clock having a low voltage level, such as voltage level Voff, is applied to the gate of buffer transistor M3, the buffer transistor is turned off. The turn-on or turn-off time point of the buffer transistor M3 depends on the voltage level of the voltage applied to the gate of the buffer transistor M3.

The turn-on or turn-off time point of the buffer transistor M3 is inversely proportional to the threshold voltage of the buffer transistor M3. When the threshold voltage of the buffer transistor M3 decreases due to an increase in ambient temperature, the turn-on or turn-off time point of the buffer transistor M3 becomes earlier than in the case where the buffer transistor M3 has a normal threshold voltage. When the threshold voltage of the buffer transistor M3 increases due to a decrease in ambient temperature, the turn-on or turn-off time point of the buffer transistor M3 is delayed. Therefore, the charge charged in the capacitor C varies with the ambient temperature, and the gate line driving signal varies with the voltage due to the charge charged in the capacitor C.

The generation of overlapping signals can be prevented. The overlapping signal is generated when the threshold voltage becomes low and the second carry buffer transistor TR2 is not fully turned off. The overlapping signal may turn on the discharge transistor M5 of the previous stage, and lower the output voltage of the pull-up transistor M1 of the previous stage, so that the gate line driving signal output from the previous stage may be lowered.

According to the third exemplary embodiment of the present invention, the gate of the buffer transistor M3 has the same resistance as the resistance of the second and third carry buffer transistor TR1, the threshold of the buffer transistor M3 and the resistance of the first carry buffer transistor TR1. The voltage level corresponding to the divided voltage formed. Even if the threshold voltage of the buffer transistor M3 changes according to the change of the surrounding temperature, the threshold voltage of the third carry buffer transistor TR3 changes according to the change of the surrounding temperature, the voltage level of the carry signal depends on the surrounding temperature, and the carry signal is applied on the gate of the buffer transistor M3, thereby canceling the effect due to the variation of the threshold voltage. A voltage level change of the gate line driving signal can be prevented.

19A and 19B are graphs showing outputs of the shift register of FIG. 18 .

As shown in FIG. 16A , when the thin film transistors of the shift register have normal threshold voltages at room temperature, the gate line driving signals (GOUT ₁ , GOUT ₂ , GOUT ₃ , . . . ) resemble square waves.

Referring to FIG. 19A, the threshold voltage of the thin film transistor of the shift register decreases as the temperature increases, the gate line driving signals (GOUT' ₁ , GOUT' ₂ , GOUT' ₃ , ...) are similar to square waves, and The gate line drive signals (GOUT' ₁ , GOUT' ₂ , GOUT' ₃ , . . . ) have about 25 volts. The voltage level of the overlapping signal shown in FIG. 19A is much smaller than that of the overlapping signal shown in FIG. 16B. A normal gate line driving signal is output.

Referring to FIG. 19B, the threshold voltage of the thin film transistor of the shift register increases as the temperature decreases, and the gate line driving signals (GOUT" ₁ , GOUT" ₂ , GOUT" ₃ , ...) are similar to square waves, and the gate line The polar line drive signals (GOUT" ₁ , GOUT" ₂ , GOUT" ₃ , . . . ) have a uniform voltage level of about 25 volts. Compared with the gate line driving signals (GOUT" ₁ , GOUT" ₂ , GOUT" ₃ , ...) of FIG. 16C , the gate line driving signals (GOUT" ₁ , GOUT" ₂ , GOUT" ₃ , ...) is more similar to a square wave, and the voltage levels of the gate line drive signals (GOUT" ₁ , GOUT" ₂ , GOUT" ₃ , ...) are more consistent.

As shown in FIGS. 19A and 19B, since the shift register includes a carry buffer in each stage, even when the threshold voltage of the thin film transistor varies due to changes in ambient temperature, the shift register can output normal gate line drive Signal.

According to the third exemplary embodiment of the present invention, since each stage includes the first, second, and third carry buffer transistors TR1, TR2, and TR3, the current stage receives the first clock ckv or the third clock with a consistent voltage level. The second clock ckvb serves as a carry signal, and the gate line driving signal output from the current stage can be independent of the gate line driving signal output from the previous stage. The carry signal compensates for variations in threshold voltage. Therefore, the shift register is independent of threshold voltage variation of the thin film transistor, and can improve reliability, productivity, and yield in manufacturing a liquid crystal display device having a large screen size.

FIG. 20 is a block diagram showing a shift register used in a gate driver circuit according to a fourth exemplary embodiment of the present invention.

Referring to FIG. 20 , each stage of the shift register includes a pull-up part 171 , a pull-down part 172 , a pull-up driver part 173 , a pull-down driver part 174 , a first carry buffer 275 and a second carry buffer 476 . In FIG. 20, the same reference numerals denote the same elements in FIG. 7, and thus detailed descriptions of the same elements will be omitted.

The second carry buffer 476 includes second and fourth carry buffer transistors TR2 and TR4. Specifically, when the output of the pull-down driver section 174 (or inverter) has a low voltage level, the second carry buffer 476 is turned off. Therefore, when the carry signal is transmitted to the second carry buffer 476, the voltage level of the carry signal may not be lowered. In addition, after the 1H period, the second carry buffer 476 remains on, while the pull-down driver section 174 is turned on, so as to turn off the buffer transistor M3.

The drain of the second carry buffer transistor TR2 is connected to the input terminal of the pull-up driver part 173 of the current stage, and is also connected to the source of the first carry buffer transistor TR1 of the previous stage. The gate of the second carry buffer transistor TR2 is connected to the gate of the second transistor M2 or the pull-down part 172, and the source of the second carry buffer transistor TR2 receives the first power voltage Voff through the first power voltage terminal VOFF. The first supply voltage terminal VOFF is the same as the supply voltage terminal VSS of FIG. 5 .

The drain of the fourth carry buffer transistor TR4 is connected to the gate of the second carry buffer transistor TR2, the gate of the fourth carry buffer transistor TR4 is connected to the drain of the second carry buffer transistor TR2, and the fourth carry The source of the buffer transistor TR4 receives the first power voltage Voff through the first power voltage terminal VOFF.

Hereinafter, the upper stage of FIG. 20 is referred to as the previous stage SRC _N , and the lower stage of FIG. 20 is referred to as the current stage SRC _N+1 in order to describe the operation of the shift register according to the fourth exemplary embodiment of the present invention. .

The carry buffer transistor TR1 of the previous stage SRC _N receives the first clock ckv, and transmits the first clock ckv as a carry signal to the current stage SRC _N+1 . Since the clock signal has a substantially uniform voltage level, RC delay due to RC load of the gate line may not occur.

When electrically charging the capacitor C of the pull-up driver part 173 of the current stage, the second carry buffer transistor TR2 is turned off. When the current stage is in an idle state, the voltage (Voff) of the second carry buffer transistor TR2 is applied to the gate of the buffer transistor M3, and the off state of the buffer transistor M3 is maintained.

Specifically, the third transistor M3 of the pull-up driver part 173 of the current stage maintains an off state. When the carry signal is applied to the third transistor M3 through the first carry buffer transistor TR1 of the previous stage, the gate of the third transistor M3 has the same resistance as that generated by the first carry buffer transistor TR1 and the second carry buffer transistor TR2 The voltage level corresponding to the divided voltage formed by the resistors.

When the second carry buffer transistor TR2 is turned off and the carry signal is applied to the gate of buffer transistor M3, buffer transistor M3 is turned on and a current path is formed between buffer transistor M3 and capacitor C such that the voltage Von Applied to capacitor C.

When a clock having a low voltage level, such as voltage level Voff, is applied to the gate of buffer transistor M3, buffer transistor M3 is turned off.

When the carry signal generated from the previous stage is applied to the gate of the fourth carry buffer transistor TR4, the fourth carry buffer transistor TR4 is turned on, thereby rapidly reducing the voltage level of the gate of the second carry buffer transistor TR2. That is, the fourth carry buffer transistor TR4 increases the switching speed of the second carry buffer transistor TR2. Therefore, the operation speed of the carry buffer can be increased.

FIG. 21 is a block diagram showing a shift register used in a gate driver circuit according to a fifth exemplary embodiment of the present invention.

Referring to FIG. 21 , each stage of the shift register includes a pull-up part 171 , a pull-down part 172 , a pull-up driver part 173 , a pull-down driver part 174 , a first carry buffer 275 and a second carry buffer 576 . In FIG. 21, the same reference numerals denote the same elements in FIG. 7, and thus detailed descriptions of the same elements will be omitted.

The first carry buffer 275 includes a first carry buffer transistor TR1, and outputs the first clock ckv or the second clock ckvb to the next stage. Specifically, the gate of the first carry buffer transistor TR1 is connected to the input terminal of the pull-down driver section 174, the drain of the first carry buffer transistor TR1 is connected to the clock terminal CKV or CKVB, and the source of the carry buffer transistor TR1 The pole is connected to the second carry buffer 576 of the next stage.

The second carry buffer 576 includes second, third and fourth carry buffer transistors TR2, TR3 and TR4. Specifically, when the output of the pull-down driver section 174 (or inverter) has a low voltage level, the second carry buffer 576 is turned off. Therefore, when the carry signal is transmitted to the second carry buffer 576, the voltage level of the carry signal may not be lowered. In addition, after the 1H period, the second carry buffer 576 remains on, while the pull-down driver section 174 is turned on to turn off the buffer transistor M3.

The drain of the second carry buffer transistor TR2 is connected to the input terminal of the pull-up driver part 173 of the current stage, and is also connected to the source of the first carry buffer transistor TR1 of the previous stage. The gate of the second carry buffer transistor TR2 is connected to the gate of the second transistor M2 or the pull-down part 172, and the source of the second carry buffer transistor TR2 is connected to the drain of the third carry buffer transistor TR3.

The drain and gate of the third carry buffer transistor TR3 are commonly connected to each other, and are connected to the source of the second carry buffer transistor TR2 and the source of the third carry buffer transistor TR3. The source of the third carry buffer transistor TR3 receives the first power voltage Voff through the first power voltage terminal VOFF. The first power supply voltage terminal VOFF is the same as the power supply voltage terminal VSS of FIG. 5 .

The drain of the fourth carry buffer transistor TR4 is connected to the gate of the second carry buffer transistor TR2, the gate of the fourth carry buffer transistor TR4 is connected to the drain of the second carry buffer transistor TR2, and the fourth carry The source of the buffer transistor TR4 receives the first power voltage Voff through the first power voltage terminal VOFF.

When the carry signal generated from the previous stage is applied to the gate of the fourth carry buffer transistor TR4, the fourth carry buffer transistor TR4 is turned on, thereby rapidly reducing the voltage level of the gate of the second carry buffer transistor TR2. That is, the fourth carry buffer transistor TR4 increases the switching speed of the second carry buffer transistor TR2. Therefore, the operation speed of the carry buffer can be increased.

According to the fifth exemplary embodiment of the present invention, since the carry buffer further includes the fourth carry buffer transistor TR4 for controlling the turn-on or turn-off of the second carry buffer transistor TR2, the second carry buffer can be improved. The switching speed of transistor TR2.

FIG. 22 is a graph showing voltages measured at the capacitor of FIG. 21 . In particular, part 'A' represents the voltage measured at the capacitor when the carry buffer has the fourth carry buffer transistor TR4, and part 'B' represents the voltage measured at the capacitor when the carry buffer does not have the fourth carry buffer transistor TR4 measured voltage.

As shown in FIG. 22, when the fourth carry buffer transistor TR4 is added to the carry buffer, the turn-off time of the second carry buffer transistor TR2 can be reduced, and the turn-on or turn-off time of the third transistor M3 can be reduced, The voltage measured at the capacitor can thus be increased. Therefore, the carry buffer having the fourth carry buffer transistor TR4 can be used in a liquid crystal display device with a large display size and high resolution, the turn-on or turn-off of the third transistor M3 can be controlled by the maximum voltage, and can be Improve the performance of shift registers.

As described in the above embodiments of the present invention, instead of the output signal (or gate line drive signal) output from the output terminal OUT of the previous stage, a carry buffer for generating a carry signal independent of the output signal of the previous stage will be used Installed in each stage, thereby preventing abnormal operation of the shift register due to variation in threshold voltage of the thin film transistor. In addition, the reliability of the shift register can be improved over a wide range of ambient temperatures, and since the variation tolerance of the threshold voltage can be improved, the yield of manufacturing the shift register can be improved.

FIG. 23 is a diagram showing gate line driving signals output from the shift register of FIG. 7 . FIG. 23 shows the waveform of the output voltage (or the voltage of the node N2) output from the pull-down driver section (or inverter) when the clock signal V[CKVB] is applied to each stage. V[GOUT(1)] represents the output voltage of the first stage varying according to the output voltage output from the inverter, and V[GOUT(2)] represents the output voltage of the second stage varying according to the output voltage of the inverter .

Referring to FIG. 23, the output voltage output from the inverter has a gentle slope, or rises slowly from a low voltage level to a high voltage level. That is, the operation speed of the inverter is slow.

The slope of the inverter depends on the resistance of the inverter and the parasitic capacitance C1 of the pull-down transistor M2. The larger the value of R×C1, the gentler the slope of the inverter, and the slower the operating speed of the inverter.

In particular, when a gate driver circuit or a shift register drives a gate line connected to a thin film transistor on a liquid crystal display panel having a large display size, since the transistor sizes of the pull-up and pull-down transistors M1 and M2 increase, Therefore, the parasitic capacitances of the pull-up and pull-down transistors M1 and M2 also increase. The transistor size refers to the ratio (W/L) of the channel width (W) of the transistor to the channel length (L) of the transistor. Consequently, R×C1 increases, and the slope of the inverter becomes gentle.

The size of the inverter needs to be increased in order to increase the operating speed of the inverter. In order to increase the size of the inverter, a larger layout area is required, and the power consumption of the inverter increases. Therefore, the size of the inverter needs to be minimized. However, when the inverter is designed to have a minimum size, the operation speed of the inverter is slow.

As shown in Figure 23, when the operation speed of the inverter is slow, especially when the output voltage of the inverter changes slowly from a low voltage level to a high voltage level, the gate line driving signals such as V[Gout(1)], V The pulse width of [Gout(2)] is greater than 1H. 1H refers to the pulse width of the clock signal. The pulse width of the grayscale voltage output from the data driver circuit 160 is also 1H.

For example, a pixel connected to an output terminal OUT of a first gate line is affected by a grayscale voltage applied to a data line connected to a next gate line connected to a next stage. Therefore, when the pulse width of V[Gout(1)] is larger than 1H, the image display quality is deteriorated. Usually, the minimum value of the gray level voltage is about 0V, and the effective pulse width of the gate line driving signal V[Gout(n)] is preferably less than or equal to 1H. The effective pulse width of the gate line driving signal V[Gout(n)] refers to the pulse width of a portion of the gate line driving signal V[Gout(n)] having a voltage level greater than 0 volts. In particular, in order to reduce the deterioration of image display quality, when the voltage level of the inverter changes from a low level to a high level, the voltage level of the gate line driving signal needs to change from a high level to a low level quickly, and The effective pulse width of the gate line driving signal V[Gout(n)] is preferably less than or equal to H.

Hereinafter, a shift register that has the smallest inverter size under the constraint of the layout area and can prevent image display quality from deteriorating is described.

24 is a block diagram showing a unit stage of a shift register used in a gate driver circuit according to a sixth exemplary embodiment of the present invention.

Referring to FIG. 24 , the cell stage includes a buffer transistor 808 , a hold transistor 806 , a discharge transistor 804 , an inverter 808 , a pull-up transistor 810 , and a pull-down transistor 812 . The cell level of FIG. 24 has some differences from the cell level of FIG. 7 .

First, the size of the inverter 808 of FIG. 24 , the size of the pull-up transistor M1 , and the size of the pull-down transistor M2 are the same as those of FIG. 7 . However, the pull-down transistor M2 is divided into a first pull-down transistor M2a and a second pull-down transistor M2b. For example, when the transistor size of the pull-down transistor M2 of FIG. 7 is 1, the transistor size ratio between the first pull-down transistor M2a and the second pull-down transistor M2b may be 0.1:0.9. Preferably, the transistor size of the second pull-down transistor M2b is larger than that of the first pull-down transistor M2a.

Second, the first pull-down transistor M2a is driven by the output voltage of the inverter 808, and the second pull-down transistor M2b is driven by the pull-up driver transistor M5 and the gate line drive signal V[Gout(n+1) output from the next stage. ]drive. The charge charged in the capacitor C is discharged by the second pull-up driver transistor M5.

Since the second pull-down transistor M2b is driven by the gate line drive signal V[Gout(n+1)] output from the next stage, the effective pulse width of the gate line drive signal V[Gout(n)] can be less than or equal to 1H. In addition, the transistor size of the first pull-down transistor M2a having a capacitive load is reduced, and the operation speed of the inverter is increased.

FIG. 25 is a diagram showing gate line driving signals output from the shift register of FIG. 24 . In particular, FIG. 25 shows gate line driving signals output from the shift register when the transistor size ratio between the first pull-down transistor M2a and the second pull-down transistor M2b is about 0.1:0.9.

Referring to FIG. 25, the effective pulse width of the gate line driving signal V[Gout(n)] output from the shift register of FIG. 25 is less than or equal to 1H, and the output voltage slope of the inverter of FIG. 25 is steeper than that of FIG. 23 The output voltage slope of the inverter. The operation speed of the inverter of FIG. 25 is faster than that of the inverter of FIG. 23 .

FIG. 26 is a diagram illustrating a gate line driving signal output from the shift register of FIG. 7 and a gate line driving signal output from the shift register of FIG. 24 . FIG. 26 shows the output voltages of the inverters of FIGS. 23 and 25 simultaneously. The output voltage of the inverter of Fig. 23 is V[INVERTER'], the output voltage of the shift register of Fig. 23 is V[Gout'], the output voltage of the inverter of Fig. 25 is V[INVERTER], and Fig. 25 The output voltage of the shift register is V[Gout].

Referring to FIG. 26 , the slope of the output voltage V[INVERTER] of the inverter 808 in FIG. 24 is greater than the output voltage V[INVERTER'] of the inverter in FIG. 23 at the rising edge of the output voltage. Referring to 'A' and 'A' of FIG. 26, compared with the voltage level of the output voltage V[Gout'] of the shift register of FIG. 23, the voltage level of the output voltage V[Gout] of the shift register of FIG. The level changes from high level to low level more rapidly, so that the effective pulse width of the gate line driving signal V[Gout(n)] can be less than or equal to 1H.

FIG. 27 is a block diagram of a power supply and clock generator according to a seventh exemplary embodiment of the present invention.

Referring to FIG. 27 , the power supply may be a DC-to-DC converter 710 , and an output power supply voltage Von of the DC-to-DC converter 710 is applied to the clock generator 720 and the shift register 170 . The clock generator 720 receives power voltages Von and Voff, and generates clock signals ckv and ckvb to provide the clock signals ckv and ckvb to the shift register 170 . That is, the clock generator 720 and the shift register 170 are driven by the same power supply voltage Von.

FIG. 28 is a diagram showing gate line drive signals output from the shift register when the same power supply voltage as that applied to the clock generator of FIG. 27 is applied to the shift register.

Referring to FIG. 28, when the same power supply voltage Von is applied to the clock generator 720 and the shift register 170, the gate line driving signal V[Gout(1)'] output from the first stage is shown as being according to the first stage. The output voltage of the inverter 808 (or the pull-down driving transistors M6 and M7) varies, and the gate line driving signal V[Gout(2)'] output from the second stage is shown as The output voltage of inverter 808 (or pull-down drive transistors M6 and M7 ) varies.

When the same power voltage Von is applied to the clock generator 720 and the shift register 170, the maximum voltage level of the clock signal is substantially the same as the high level of the power voltage Von.

When the same power supply voltage Von is applied to the clock generator 720 and the shift register 170 in a liquid crystal display device having a large display size, image display quality may deteriorate as capacitive load due to gate lines increases.

As shown in FIG. 28, the pulse width of the gate line drive signal V[Gout(1)'] is greater than 1H (the pulse width of the clock signal). Usually, the minimum value of the gray level voltage is about 0V, and the effective pulse width of the gate line driving signal V[Gout(n)] is preferably less than or equal to 1H. In particular, in order to reduce the deterioration of image display quality, when the voltage level of the output voltage output from the inverter 808 changes from low level to high level, the voltage level of the gate line driving signal needs to rapidly change from high level to high level. Change to low level, and the effective pulse width of the gate line driving signal V[Gout(n)] is preferably less than or equal to 1H.

Since the operation speed of the inverter 808 (or the pull-down transistors M6 and M7 ) is slow, the pulse width of the gate line driving signal V[Gout(1)'] is greater than 1H. As shown in parts A1' and A2' of FIG. 28, since the output voltage from the inverter 808 has a gentle slope or rises slowly from a low level to a high level, the gate line driving signal V[Gout(1 )'] and the voltage levels of V[Gout(2)'] slowly drop below the low level in the vicinity of portions A1' and A2'. Therefore, the effective pulse width of the gate line driving signals V[Gout(1)'] and V[Gout(2)'] is greater than 1H.

When the effective pulse width of V[Gout(n)'] is greater than 1H, the pixel connected to the output terminal OUT of the n-th gate line is subjected to the voltage applied to the next gate line connected to the next stage (the (nth (n)th gate line) +1) Influence of the gray scale voltage of the data line of the gate line). Therefore, image display quality may be deteriorated. The voltage level of the output voltage of the inverter 808 needs to change from low level to high level quickly, so that the effective pulse width of V[Gout(n)′] may not be greater than 1H. That is, the gradient of the output voltage of the inverter needs to be large. The magnitude of the output voltage of the inverter can be increased so that the output voltage slope of the inverter can be increased.

FIG. 29 is a block diagram of a power supply and clock generator according to a seventh exemplary embodiment of the present invention.

Referring to FIG. 29 , the DC-to-DC converter 910 generates a power supply voltage Von, and applies the power supply voltage Von to the clock generator 720 . The DC-to-DC converter 910 generates another power voltage Vona, and applies the power voltage Vona to the shift register 170 . The power supply voltage Vona has a different voltage level from the power supply voltage Von. That is, a power voltage Vona different from the power voltage Von is applied to the shift register 170 .

Preferably, the magnitude of the supply voltage Vona is greater than the magnitude of the supply voltage Von in order to maintain the maximum output voltage of the inverter 808 greater than that of the inverter of FIG. 28 .

FIG. 30 is an example circuit diagram illustrating the DC-to-DC converter of FIG. 29 . Fig. 30 shows a DC to DC converter for generating a supply voltage Vona greater than the supply voltage Von.

Referring to FIG. 30 , the DC-to-DC converter receives a DC voltage VDD, and generates a power supply voltage Von (VDD+ΔV) and a power supply voltage Vona (VDD+2ΔV) through a charge pump circuit. For example, the charge pump circuit includes a plurality of diodes D1 , D2 , D3 and D4 and a plurality of capacitors C2 , C3 , C4 and C5 connected in series.

A DC voltage VDD is applied to the anode of the diode D1, ΔV is applied to the capacitor C2, and Von (VDD+ΔV) is output from the cathode of the diode D2. Von is applied to the anode of the diode D3, ΔV is applied to the capacitor C4, and Vona (VDD+2ΔV) is output from the cathode of the diode D4. Therefore, Vona (>Von) and Von can be generated by the charge pump circuit. In addition, Vona (>Von) and Von can be generated by a voltage level shifter (shifter) circuit. Von can vary, and Vona can also vary independently of Von.

When Vona (>Von) is applied to the shift register 170, as shown in FIGS. 7 and 29, the inverter 808 is driven by Vona applied to the shift register through the drain of transistor M6. Thus, the output voltage of the inverter 808 driven by Vona increases the output voltage of the inverter driven by Von. In addition, the voltage level of the output voltage of the inverter rapidly changes from a low level to a high level. Therefore, the effective pulse width of V[Gout(n)] is basically 1H or not more than 1H, and image display quality may not be deteriorated.

FIG. 31 is a diagram illustrating a gate line driving signal output from a shift register when the power supply and clock generator of FIG. 29 drives the shift register.

In FIG. 28, a Von of about 25 volts is applied to the inverter 808, and the maximum output voltage of the inverter 808 is about 15 volts. In FIG. 31, a Von of about 45 volts is applied to the inverter 808, and the maximum output voltage of the inverter 808 is about 35 volts. Therefore, the effective pulse widths of V[Gout(1)] and V[Gout(1)] are smaller than those in FIG. 28 with respect to portions B1 and B1' of the rising edge of the output voltage of the inverter.

FIG. 32 is a diagram showing gate line driving signals output from the shift register when the power and clock generators of FIGS. 29 and 28 drive the shift register.

Referring to FIG. 32, V[Gout'] represents a gate line driving signal when the clock generator and the shift register are driven by the same power supply voltage Von. V[Gout] represents a gate line driving signal when Von is applied to the clock generator and Vona greater than Von is applied to the shift register.

Regarding portions A and A' of the falling edge of the output voltage of the inverter, the effective pulse width of V[Gout] is narrower than that of V[Gout'].

Although the above-described embodiments discuss a shift register for driving gate lines of a liquid crystal display device, the present invention can also be used in an organic electroluminescence display device.

Although the exemplary embodiments of the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the scope of the invention as defined by the appended claims.

Claims (31)

1. shift register comprises the level of a plurality of cascades, and these levels receive first clock signal and second clock signals, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, and each level comprises:

The carry impact damper is used for providing carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases;

Last pull portion is used for providing first scan line driving signal corresponding to first clock signal or second clock signal to lead-out terminal;

Drop-down part is used for providing first supply voltage to lead-out terminal;

On draw driver portion, be used to respond the carry signal that provides from previous stage and pull portion in the conducting, and second scan line driving signal of response next stage and turn-off pull portion; And

The pull-down driver part is used to respond the carry signal that provides from previous stage and turn-offs drop-down part, and second scan line driving signal of response next stage and pull portion in the conducting.

2. shift register as claimed in claim 1, wherein the carry impact damper comprises the first transistor, it is used for reception first of first drain electrode or second clock signal by the first transistor, the first source electrode with the output signal of response pull-down driver part by the first transistor outputs to next stage with carry signal, and this output signal puts on the first grid electrode of the first transistor.

3. shift register as claimed in claim 2, wherein adjacent on the position of pull portion form the first transistor so that with first or the second clock signal offer next stage on draw driver portion.

4. shift register as claimed in claim 2 is wherein gone up pull portion and is comprised transistor seconds,

The pull-down section branch comprises the 3rd transistor, and the 3rd transistor comprises:

First grid electrode is from the second grid wiring branch of transistor seconds;

First drain electrode drains from the main wiring branch of its branch from second of transistor seconds; And

The first source electrode gets around pull portion and drop-down part the 3rd grid with the drop-down part that is extended to next stage.

5. shift register as claimed in claim 4, wherein the first source electrode of the first transistor is received the 3rd transistorized the 3rd drain electrode by the bridging that forms between first source electrode line and the 3rd drain line.

6. liquid crystal display comprises:

Array of display cells forms on transparency carrier, and this array of display cells comprises many gate lines, many data lines and a plurality of on-off element, and on-off element is coupled in gate line and data line;

Data driving circuit is used for providing picture signal to every data line; And

Gate driver circuit comprises shift register, and this shift register comprises the level of a plurality of cascades, and these levels receive first clock signal and second clock signal, produce a plurality of gate line drive signals that are used to select gate line with order, and each level comprises:

The carry impact damper is used for providing carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases;

Last pull portion is used for providing first grid polar curve drive signal corresponding to first clock signal or second clock signal to lead-out terminal;

Drop-down part is used for providing first supply voltage to lead-out terminal;

On draw driver portion, be used to respond the carry signal that provides from previous stage and pull portion in the conducting, and the second grid line drive signal of response next stage and turn-off pull portion; And

The pull-down driver part is used to respond the carry signal that provides from previous stage and turn-offs drop-down part, and the second grid line drive signal of response next stage and pull portion in the conducting.

7. method that drives shift register, this shift register comprises the level of a plurality of cascades, and these levels receive first clock signal and second clock signals, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, and this method comprises:

Provide carry signal corresponding to first clock signal or second clock signal to next stage, the second clock signal has and the first clock signal opposite phases;

Response produces first scan line driving signal corresponding to first clock signal or second clock signal from the carry signal of previous stage output; And

Response reduces from second scan line driving signal of next stage output from first voltage level when first scan line driving signal of prime output.

8. method as claimed in claim 7, wherein carry signal has second voltage level corresponding to first clock signal or second clock signal, and is independent of parasitic resistor and the capacitor parasitics that produces from sweep trace.

9. method as claimed in claim 7 also comprises: after predetermined period, respond first voltage level of first scan line driving signal and reduce from second voltage level of the carry signal of previous stage output.

10. shift register comprises the level of a plurality of cascades, and the first order receives scan start signal, and these levels receive first clock signal and second clock signals, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, and each level comprises:

The first carry impact damper is used for providing first carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases;

Last pull portion is used for providing first scan line driving signal corresponding to first clock signal or second clock signal to first lead-out terminal;

Drop-down part is used for providing first supply voltage to first lead-out terminal;

On draw driver portion, be used to respond from second carry signal of the first carry impact damper output of previous stage and pull portion in the conducting, and second scan line driving signal of response next stage and turn-off pull portion;

The pull-down driver part is used to respond first carry signal that provides from the first carry impact damper of previous stage and turn-offs drop-down part, and second scan line driving signal of response next stage and pull portion in the conducting; And

The second carry impact damper is used to reduce by first voltage level of second carry signal, exports first carry signal to put on pull portion from the first carry impact damper of previous stage.

11. shift register as claimed in claim 10, wherein the first carry impact damper comprises the first transistor, it is used for reception first of first drain electrode or second clock signal by the first transistor, the first source electrode with the output signal of response pull-down driver part by the first transistor outputs to next stage with carry signal, and this output signal puts on the first grid electrode of the first transistor.

12. shift register as claimed in claim 10, wherein the second carry impact damper comprises transistor seconds, and transistor seconds comprises:

Second drain electrode, be coupled in previous stage the first carry impact damper second lead-out terminal and on draw the input terminal of driver portion;

Second gate electrode is coupled in drop-down part; And

The second source electrode is used to receive first supply voltage.

13. shift register as claimed in claim 10, wherein the second carry impact damper comprises:

Transistor seconds, its second drain electrode be coupled in previous stage the first carry impact damper second lead-out terminal and on draw the input terminal of driver portion, its second gate electrode is coupled in drop-down part, and its second source electrode is used to receive first supply voltage; And

The 3rd transistor, its 3rd drain electrode and the 3rd gate electrode coupled in common are in the second source electrode, and its 3rd source electrode is used to receive first supply voltage.

14. shift register as claimed in claim 10, wherein the second carry impact damper comprises:

Transistor seconds, its second drain electrode be coupled in previous stage the first carry impact damper second lead-out terminal and on draw the input terminal of driver portion, its second gate electrode is coupled in drop-down part, and its second source electrode is used to receive first supply voltage; And

The 3rd transistor, its 3rd drain electrode is coupled in second gate electrode of transistor seconds, and its 3rd gate electrode is coupled in second drain electrode of transistor seconds, and its 3rd source electrode is used to receive first supply voltage.

15. shift register as claimed in claim 10, wherein the second carry impact damper comprises:

Transistor seconds, its second drain electrode be coupled in previous stage the first carry impact damper second lead-out terminal and on draw the input terminal of driver portion, its second gate electrode is coupled in drop-down part, and its second source electrode is used to receive first supply voltage;

The 3rd transistor, its 3rd drain electrode and the 3rd gate electrode coupled in common are in the second source electrode of transistor seconds, and its 3rd source electrode is used to receive first supply voltage; And

The 4th transistor, its 4th drain electrode is coupled in second gate electrode of transistor seconds, and its 4th gate electrode is coupled in second drain electrode of transistor seconds, and its 4th source electrode is used to receive first supply voltage.

16. a liquid crystal display comprises:

Array of display cells is formed on the transparency carrier, and this array of display cells comprises many gate lines, many data lines and a plurality of on-off element, and on-off element is coupled in gate line and data line;

Data driving circuit is used for providing picture signal to every data line; And

Gate driver circuit, comprise shift register, this shift register comprises the level of a plurality of cascades, the first order receives scan start signal, these levels receive first clock signal and second clock signal, produce a plurality of gate line drive signals that are used to select many gate lines with order, each level comprises:

The first carry impact damper is used for providing first carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases;

Last pull portion is used for providing first grid polar curve drive signal corresponding to first clock signal or second clock signal to first lead-out terminal;

Drop-down part is used for providing first supply voltage to first lead-out terminal;

On draw driver portion, be used to respond from second carry signal of the first carry impact damper output of previous stage and pull portion in the conducting, and the second grid line drive signal of response next stage and turn-off pull portion;

The pull-down driver part is used to respond first carry signal that provides from the first carry impact damper of previous stage and turn-offs drop-down part, and the second grid line drive signal of response next stage and pull portion in the conducting; And

The second carry impact damper is used to reduce by first voltage level of second carry signal, exports first carry signal from the first carry impact damper of previous stage and puts on pull portion.

17. a shift register comprises the level of a plurality of cascades, these levels receive first clock signal and second clock signals, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, and each level comprises:

Last drag switch device, being used for lead-out terminal to each grade provides first scan line driving signal corresponding to first clock signal or second clock signal;

Draw the driver switch device on first, be used to respond from the scan start signal of previous stage output or second scan line driving signal and drag switch device in the conducting;

Draw the driver switch device on second, be used to respond from the three scan line drive signal of next stage output and turn-off the drag switch device;

First device that pulls down switch is used for providing first supply voltage to lead-out terminal;

The pull-down driver switching device is used to respond from the scan start signal of previous stage output or second scan line driving signal and turn-offs the device that pulls down switch; And

Second device that pulls down switch, the device that responds the three scan line drive signal and conducting second pulls down switch is to provide first supply voltage to lead-out terminal.

18. shift register as claimed in claim 17, wherein each level also comprises and draws the driver switch device on the 3rd, and during when last drag switch break-over of device and to last drag switch device discharge, draws the shutoff of driver switch device on the 3rd.

19. shift register as claimed in claim 17, wherein first and second devices that pull down switch comprise the amorphous silicon nmos tft respectively.

20. shift register as claimed in claim 19 wherein second pulls down switch the first transistor size of device greater than the first transistor seconds size that pulls down switch device.

21. shift register as claimed in claim 20, wherein the transistor seconds size is greater than nine times basically of the first transistor sizes.

22. a liquid crystal display comprises:

Array of display cells is formed on the transparency carrier, and this array of display cells comprises many gate lines, many data lines and a plurality of on-off element, and on-off element is coupled in gate line and data line;

Data driving circuit is used for providing picture signal to every data line; And

Gate driver circuit comprises shift register, and this shift register comprises the level of a plurality of cascades, and these levels receive first clock signal and second clock signal, produce a plurality of gate line drive signals that are used to select many gate lines with order, and each level comprises:

Last drag switch device, being used for lead-out terminal to each grade provides first grid polar curve drive signal corresponding to first clock signal or second clock signal;

Draw the driver switch device on first, be used to respond from the scan start signal of previous stage output or second grid line drive signal and drag switch device in the conducting;

Draw the driver switch device on second, be used to respond from the 3rd gate line drive signal of next stage output and turn-off the drag switch device;

First device that pulls down switch is used for providing first supply voltage to lead-out terminal;

The pull-down driver switching device is used to respond from the scan start signal of previous stage output or second grid line drive signal and turn-offs the device that pulls down switch; And

Second device that pulls down switch, the device that responds the 3rd gate line drive signal and conducting second pulls down switch is to provide first supply voltage to lead-out terminal.

23. a shift register comprises the level of a plurality of cascades, these levels receive first clock signal and second clock signals, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, and each level comprises:

Draw the driver switch device on first, its first electrode is used to receive second source voltage, and its second electrode is used to receive the scan start signal or first scan line driving signal from previous stage output, and its 3rd electricity is grade coupled in first node;

Last drag switch device, its 4th electrode is used to receive first clock signal or second clock signal, and its 5th electrode is coupled in first node, and its 6th electrode is coupled in lead-out terminal;

First device that pulls down switch, its 7th electrode is coupled in lead-out terminal, and its 8th electrode is coupled in Section Point, and its 9th electrode is used to receive first supply voltage;

Second device that pulls down switch, its tenth electrode is coupled in lead-out terminal, and its 11 electrode is used to receive the second grid line drive signal from next stage output, and its 12 electrode is used to receive first supply voltage;

Capacitor is coupled between first node and the lead-out terminal;

Draw the driver switch device on second, its 13 electrode is coupled in first node, and its 14 electrode is used to receive the second grid line drive signal from next stage output, and its 15 electrode is used to receive first supply voltage;

Draw the driver switch device on the 3rd, its 16 electrode is coupled in first node, and its 17 electrode is coupled in Section Point, and its 18 electrode is used to receive first supply voltage;

Draw the driver switch device on first, its 19 electrode and the mutual coupled in common of the 20 electrode also receive second source voltage, and its 21 electrode is coupled in Section Point; And

The second pull-down driver switching device, its 22 electrode is coupled in Section Point, and its 23 electrode is coupled in first node, and its 24 electrode is used to receive first supply voltage.

24. shift register as claimed in claim 23, wherein first and second devices that pull down switch comprise the amorphous silicon nmos tft respectively.

25. shift register as claimed in claim 24, wherein first and second devices that pull down switch are respectively nmos pass transistors, and second pulls down switch the first transistor size of device greater than the first transistor seconds size that pulls down switch device.

26. shift register as claimed in claim 25, wherein the transistor seconds size is greater than nine times basically of the first transistor sizes.

27. a method that drives shift register, this shift register comprises the level of a plurality of cascades, and these levels receive first clock signal and second clock signal, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, and this method comprises:

Receive first clock signal or second clock signal, to provide first clock signal or second clock signal, first clock signal and second clock signal to have first voltage level corresponding basically with first voltage level of first supply voltage to each level;

Produce second source voltage, have second voltage level than the high predetermined voltage level of first voltage level so that second source voltage, second source voltage to be provided to each level;

Generation is used to select to be coupled in first scan line driving signal when first sweep trace of prime;

Response is brought down below the tertiary voltage level of first scan line driving signal the 4th voltage level of tertiary voltage level from second scan line driving signal of next stage output;

First scan line driving signal with the 4th voltage level is provided to first sweep trace; And

After the tertiary voltage level that reduces by first scan line driving signal, when the voltage level of the output signal of the device that pulls down switch when the 5th voltage level fades to the 6th voltage level that is higher than the 5th voltage level, the 4th voltage level of first scan line driving signal is kept predetermined period.

28. method as claimed in claim 27, the first voltage level rising predetermined voltage level of first supply voltage wherein is so that produce the second source voltage with second voltage level.

29. method as claimed in claim 27, wherein first voltage level of first supply voltage is conditioned so that it changes, and second voltage level of first supply voltage is independent of first supply voltage and regulates.

30. method as claimed in claim 27, the maximal voltage level of the output signal of the device that wherein pulls down switch is between first voltage level and second voltage level.

31. method that drives shift register, this shift register comprises the level of a plurality of cascades, and these grades alternately receive first clock signal and the second clock signal that produces from clock generator, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, first and second clock signals have first voltage level corresponding with first voltage level of first supply voltage basically, and each level comprises:

Last drag switch device, being used for lead-out terminal to each grade provides first scan line driving signal corresponding to first clock signal or second clock signal;

Draw the driver switch device on first, be used to respond from the scan start signal of previous stage output or second scan line driving signal and drag switch device in the conducting;

Draw the driver switch device on second, be used to respond from the three scan line drive signal of next stage output and turn-off the drag switch device;

The device that pulls down switch is used for providing the 3rd supply voltage to lead-out terminal; And

The pull-down driver switching device is used to respond from the scan start signal of previous stage output or second scan line driving signal and turn-offs the device that pulls down switch, and wherein this method comprises:

Receive first clock signal or second clock signal, to provide first clock signal or second clock signal to each level;

Produce second source voltage, have second voltage level than the high predetermined voltage level of first voltage level so that second source voltage, second source voltage to be provided to each level;

During the high level period of first clock signal or second clock signal, produce first scan line driving signal be used to select to be coupled in when first sweep trace of prime;

Response is brought down below the tertiary voltage level of first scan line driving signal the 4th voltage level of tertiary voltage level from the three scan line drive signal of next stage output;

First scan line driving signal with the 4th voltage level is provided to first sweep trace; And

After the tertiary voltage level that reduces by first scan line driving signal, when the voltage level of the output signal of the device that pulls down switch when the 5th voltage level fades to the 6th voltage level that is higher than the 5th voltage level, the 4th voltage level of first scan line driving signal is kept predetermined period.

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