CN1851825B - High performance memory and related method - Google Patents
High performance memory and related method Download PDFInfo
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- CN1851825B CN1851825B CN200610081730A CN200610081730A CN1851825B CN 1851825 B CN1851825 B CN 1851825B CN 200610081730 A CN200610081730 A CN 200610081730A CN 200610081730 A CN200610081730 A CN 200610081730A CN 1851825 B CN1851825 B CN 1851825B
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Abstract
The invention provides a memory and a related method. The memory includes: memory cells arranged in a matrix form, wherein each memory cell can correspond to a row of connecting lines and a column of connecting lines; at least one discharge module, which is correspondingly connected to the respective column connection line respectively, for discharging the column connection line where the memory cell is to be accessed; at least one auxiliary module respectively and correspondingly connected to the discharge modules; and a sense amplifier, coupled to the auxiliary module, for accessing the memory cell according to a power level of the column line; the memory circuit can be used for selecting and discharging the column connection line corresponding to the memory cell to be accessed according to a discharge signal and a column selection signal; when the memory unit to be accessed is enabled, the power supply level of the row connecting line where the memory unit is located is changed, wherein when the power supply level of the row connecting line exceeds a threshold level, the auxiliary module enables the power supply level of the row connecting line to be increased.
Description
Technical field
The present invention relates to a kind of efficient storage and correlation technique thereof, particularly relate to and a kind ofly have independent discharge module is minimized power consumption, enhancement access usefulness with supplementary module ROM (read-only memory) and correlation technique thereof on line at each row.
Background technology
In advanced information society, various files, data, data can both be transmitted, manage and store in the mode of electric signal, and various storer/memory circuit that carries out data access also just becomes the indispensable hardware circuit of various electronic installation/massaging devices.Wherein, the ROM (read-only memory) of read-only property can be come storage data in non-volatile mode, and its range of application is more extensive.For example, in circuit/chip that digital signal is handled, or in mobile phone, be used for carrying out in the communication chip of signal coding/modulation, ROM (read-only memory) all can be set store program code (code) or other essential parameter and the vector (vector) that signal is handled.Because read-only memory circuit is of many uses, its development also just becomes one of research and development emphasis of present information manufacturer.
As known to persons skilled in the art, can be provided with a plurality of storage unit that are used for storing the one digit number certificate respectively in the storer, these storage unit can be arranged as the storage array of matrix form via the ranks connection of row line-row line (character line-bit line just).In each storage unit, then can utilize the difference of circuit structure to make each storage unit can write down the data of digital " 0 " or " 1 " respectively.For example, in the storage unit of record numeral " 1 " transistor is not set, in the storage unit of record digital " 0 " a metal oxide semiconductor transistor can be set then; In the storer of prior art, there is an end to be connected in capable line in this one transistor drain/source electrode, the other end then is biased in low level ground terminal voltage; Grid then is connected in the row line.
In order to cooperate the ground end bias arrangement in the storage unit, the storer of prior art can be provided with pre-charge circuit and be used for keeping the holding circuit of level, so that when access memory cell, the row line is carried out precharge, and suitably keeps the voltage level on the capable line.Will be in the storer of prior art during given storage unit on the access one given capable line, prior art can be earlier carried out precharge with pre-charge circuit to each row line of storage array, is the voltage (for example being positive bias voltage Vdd) of high level with the voltage charging on each row line; When row line voltage raise to high level, holding circuit also can start and keep high level voltage on the capable line.Next, will stop this given capable line is carried out precharge, this given storage unit of activation then makes this given storage unit can begin to influence according to recorded data in it voltage on given capable line.If what write down in the given storage unit is numeral " 1 " and be not provided with transistor, this given storage unit just can not change to the high-voltage level on the position line, but will be maintained at high level to the voltage on the position line by holding circuit.If what write down in the given storage unit is digital " 0 " and be provided with a transistor, this transistor will conducting and the voltage discharge that will go on the line is the low level of ground terminal voltage.According to the voltage on the given capable line is high level or low level, and sensing amplifier just can interpretation go out the digital data content that writes down in this given storage unit.Begin to proceed to the voltage sensing/data interpretation of sensing amplifier from precharge, just can finish a store access cycle (accessingcycle also can be described as reading cycle).
But, by above-mentioned description to existing storer as can be known, existing storer still has some technical disadvantages to have much room for improvement. one of them, be a large amount of power consumptions that precharge causes. when beginning a store access cycle reading a storage unit, existing storer all will carry out comprehensive precharge to all row lines, will expend many power like this. another shortcoming is, transistor meeting and holding circuit in the storage unit resist (fighting) mutually, make the required time of access data to increase. just as described in the preceding paragraph, concerning the storage unit that records digital " 0 ", these storage unit will make capable line be discharged to low level with the transistor of conducting, just can make can the judge rightly numerical value of its record of sensing amplifier. but, because the row line has been precharged to high level earlier when store access cycle begins, yet the transistor in the storage unit will could be pulled low to low level by high level with row line voltage via the conducting of a period of time., when storage unit began the discharge of row line, holding circuit can be resisted the discharge of storage unit because keeping the high level of capable line; So, storage unit will spend the more time could with the row line voltage be pulled low to low level. in other words, existing storer needs the long period just can finish a store access cycle, and this has also reduced the access usefulness of existing storer.
Summary of the invention
Therefore, the invention provides a kind of power consumption is low, access usefulness is high efficient storage and correlation technique, to overcome the shortcoming of prior art.
According to an aspect of the present invention, provide a kind of memory circuitry, include: the storage unit of arranging with the form of matrix, wherein each storage unit can a corresponding delegation line and a row line; At least one discharge module, it is linked to respectively on separately this row line accordingly, desires this row line at this storage unit place of access in order to discharge; At least one supplementary module, it is connected to this discharge module separately respectively accordingly; And a sensing amplifier, be linked to this supplementary module, in order to the power supply electrical level according to this row line, access goes out this storage unit.Wherein this memory circuitry can select signal to desire this row line of this storage unit place correspondence of access in order to select discharge according to a discharge signal and delegation.Wherein when this storage unit of desiring access was enabled, the power supply electrical level of this row line at this storage unit place changed, and wherein when the power supply electrical level of this row line surpassed a threshold level, this supplementary module made the power supply electrical level of this row line more increase.
According to another aspect of the present invention, provide a kind of selectivity discharge memory circuitry, include: a plurality of storage unit are arranged in the form of matrix, and wherein each this storage unit can a corresponding delegation line and a row line; And a plurality of discharge modules, it is connected to respectively on separately this row line accordingly, receives a discharge signal and delegation and selects signal in order to this row line is discharged.Wherein utilize this discharge signal and this row to select signal to desire this row line at this storage unit place of access in order to select discharge.
As discussed earlier, in storer, available transistorized having or not plans that a storage unit recorded data is digital " 0 " or " 1 ".In existing storer, the transistor biasing in the storage unit is in low level ground terminal voltage; In order to differentiate transistorized having or not when the access memory cell, must be earlier to be precharged to high level, and holding circuit is set suitably keeps this high level going line.In comparison, storer of the present invention is in high level (similarly being positive bias voltage Vdd) with the transistor biasing in the storage unit; When storage unit on access delegation line, the present invention is discharged to this row line ground terminal voltage (other row line then need not discharge) earlier, the storage unit of access is desired in activation then, makes this storage unit influence power supply electrical level (similarly being voltage) on the capable line according to its recorded data (just transistorized having or not).If in the storage unit transistor is not set, the voltage on the row line can not change; If be provided with transistor in the storage unit, this turn-on transistor that is biased in high level will be drawn high the voltage of row line.According to the height of power supply electrical level on the row line, sensing amplifier just can sensing/interpretation go out to desire recorded data in the access memory cell, finishes a store access cycle.
By foregoing description as can be known, the present invention discharges and overcomes the highly energy-consuming precharge program of existing storer optionally to go line. when each store access cycle begins, the present invention only needs the capable line of desiring access is discharged earlier, other row line then need not discharge, so the present invention can reduce the power that discharges and recharges required consumption in advance. in the present invention, can be the discharge module that each row line is provided with a correspondence, the discharge module of different rows line can independently operate, only remaining the capable line at access memory cell place just need discharge. when reality realizes, this discharge module can determine whether and will discharge according to the result of row line address decoder. be in storer during a certain storage unit of access, can decode the capable line and the row line at this storage unit place earlier. and the present invention just can utilize the decoded result of capable line to control the discharge module of each row on line, only the capable line of desiring the access memory cell place is discharged in advance, all row lines are advanced precharge high power consumption comprehensively to overcome in the prior art.
On the other hand, because storer of the present invention is will desire the accessed row line earlier to be discharged to the ground terminal voltage when carrying out store access cycle, so in storer of the present invention, do not need the power supply electrical level of capable line to be maintained at high level with holding circuit.In general, storer is formed at at semiconductor-based the end, and the low-voltage that this substrate meeting is held with being biased in, so the original ground terminal voltage of just relatively tending to of the power supply electrical level on the row line.Therefore, the present invention just need not also will be with voltage the voltage when being maintained at precharge of holding circuit with the row line after precharge as prior art.In addition, in existing storer, if desire to be provided with transistor in the access memory cell, this transistor can drag down row line voltage when access and be the ground terminal voltage, and the function of its function meeting and holding circuit is resisted mutually, and the access time is increased.In comparison, the present invention just can be converted into this holding circuit a supplementary module that can increase access usefulness; Be provided with transistor if desire in the access memory cell, this transistor can charge to high level with the capable line that is discharged to the ground terminal voltage in advance, and this supplementary module will charge to the row line together with transistor, make the voltage on the capable line can quicken to be increased to high level, reduce the access time, strengthen access usefulness.
Description of drawings
Fig. 1 is the tradition circuit diagram of storer only.
Fig. 2 is the waveform sequential synoptic diagram of related signal when storer operates among Fig. 1.
Fig. 3 is the circuit diagram of another legacy memory.
Fig. 4 is the circuit diagram of storer of the present invention.
Fig. 5 is the waveform sequential synoptic diagram of related signal when storer operates among Fig. 4.
Fig. 6 is the circuit diagram of another embodiment of the present invention.
The reference numeral explanation
10,20,30,40 storeies
12,22,32,42 governor circuits
14A, 24A, 34A, 46A column decoder
14B, 24B, 34B, 46B row decoder
16A-16B, 26A-26B, 36A-36B terminating circuit
18,28,38,48 sensing amplifiers
The Ld discharge module
The Le supplementary module
Ka-Kb, Ks transistor
The D storage unit
The Kc phase inverter
Pre, C (1)-C (N), Dis, CH (1)-CH (p) signal
W (1)-W (M), WL (1)-WL (M) character line
B (1)-B (K), BL (1)-BL (K) bit line
The V bias voltage
G ground terminal voltage
Tp0-tp4, t0-t4 time point
The Vt threshold level
The Qa judging unit
Qn drawing unit
The Qp driver element
The Qi control module
Qs, QsH switch element
Embodiment
Please refer to Fig. 1; Fig. 1 is the structural representation of a legacy memory 10.Storer 10 is a read-only memory circuit, and it has a plurality of storage unit D, and each storage unit is used for storing one data; By the connection of each row line (character line just) W (1) to W (M), each row line (being bit line) B (1) to B (K), each storage unit D just can connect/be arranged as a matrix.For the access of supporting this memory cell matrix is controlled, also be provided with a governor circuit 12, a row decoder 14B, a column decoder 14A, terminating circuit 16A-16B and a sensing amplifier 18 in the memory circuit 10; In addition, each row line B (1) also is respectively equipped with two p type metal oxide semiconductor transistor Ka, Kb, a phase inverter Kc and the n-type metal oxide semiconductor transistor as switch element to B (N).Storer 10 is biased between the bias voltage V (for example being positive bias voltage Vdd) and low level ground terminal voltage G of high level; Wherein, main control module 12 is used for the running of master control memory circuit 10, similarly is the running of coordinating between other circuit, and provides a precharge signal Pre to control the opportunity that precharge is carried out; Terminating circuit 16A, 16B then can include the interlock circuit that redundant storage unit (dummy cell), impedance matching circuit or bias circuit etc. are used for supporting memory cell matrix.
As shown in Figure 1, each the storage unit D in the storer 10 plans (program) each storage unit recorded data with having or not of n-type metal oxide semiconductor transistor; For example, do not have transistorized storage unit and be used for record numeral " 1 ", have transistorized storage unit and then be used for writing down digital " 0 ".It should be noted that, in the storage unit of legacy memory 10, the drain/source of each metal oxide semiconductor transistor is connected between the corresponding capable line and low level ground terminal voltage G, and grid then is connected in the respective column line and controls with the selection that is subjected to column decoder.To B (N), the transistor Ks on each row line is as a switch element at each row line B (1), and its grid then is controlled by the signal C (1) of row decoder 14B respectively to C (K).The conducting of controlling each switch element to C (K) via signal C (1) whether, just can control each row line B (1) to B (K) whether can be with its voltage transmission to sensing amplifier 18.
On the other hand, on each row line, transistor Ka promptly is used for being used as a pre-charge circuit, transistor Kb on each row line then forms the pairing voltage holding circuit of the capable line of each bar with phase inverter Kc. cooperate the transistor that is biased in low level ground terminal voltage G in each storage unit, be used for carrying out precharge transistor Ka and then be biased in high level bias voltage V at Qi Yuan, the grid of each transistor Ka then all unifies to be controlled by signal Pre; When signal Pre makes each transistor Ka activation conducting, each transistor Ka just can be via its drain electrode to each self-corresponding capable line charging. cooperate the drain voltage of transistor Ka, the running that phase inverter Kc on each row line then can come oxide-semiconductor control transistors Kb according to the reverse voltage of this drain voltage (being the drain voltage of transistor Ka). the voltage on delegation's line (is exactly that this row line is in the drain voltage of transistor Ka, the voltage of this row line and storage unit junction just) when being maintained high level, phase inverter Kc on this row line will control its corresponding transistor Kb with anti-phase low level voltage, make transistor Kb conducting and the voltage on this row line is maintained at high level. have only when the voltage on the row line to drop to a certain degree and when triggering that phase inverter Kb is anti-phase to come oxide-semiconductor control transistors Kb with high level, transistor Kb just understands anergy and closes and stop to influence voltage on the capable line.
About the operation situation of legacy memory 10, please refer to Fig. 2 (and in the lump with reference to figure 1); Fig. 2 signal be storer 10 runnings the time related signal waveform sequential synoptic diagram; The transverse axis of Fig. 2 is the time, and the longitudinal axis of each waveform is represented the power supply electrical level of each waveform (similarly being voltage) just.When beginning a store access cycle when wanting a certain storage unit of access, precharge signal Pre (Fig. 1) will be earlier makes precharge transistor Ka conducting on each row line (being bit line) in beginning between time point tp0 to tp1 with the signal of high level, unified all bit lines is carried out precharge.Simultaneously, column decoder 14A, row decoder 14B can decode respectively and desire capable line and the row line (being character line) that access memory cell connected.Suppose to desire the bit line that access memory cell connected and before time point tp0, be low level, after precharge transistor Ka begins precharge, desiring on the bit line that access memory cell connected, its bit-line voltage (drain voltage of transistor Ka on this bit line just) will begin to rise, and stably reaches high level (level of bias voltage V just) when time point tp1.
Arrived time point tp1, precharge signal Pre becomes low level, finishes the precharge program.Next, column decoder 14A will come activation to desire access memory cell with high level via desiring the character line that access memory cell connected; And desiring on the bit line that access memory cell connected, also can controlled conducting as the transistor Ks of switch element via the corresponding signal of row decoder 14B.Suppose to desire to be provided with transistor in the access memory cell, this transistor will be after storage unit begins activation, begins bit line discharges that it is connected, and its voltage is descended.Instantaneous through one section discharge arrived time point tp3, and this bit line will be discharged to low level with being stabilized, and sensing amplifier 18 (Fig. 1) just can come interpretation to desire recorded data in the access memory cell according to this bit-line voltage then.On the contrary, if desire do not have transistor in the access memory cell, even this storage unit is enabled behind time point tp1, this storage unit also can't change the voltage on this bit line.Because the voltage on this bit line is high level, the phase inverter Kc on this bit line can make corresponding transistor Kb conducting, keeps high level voltage on the bit line by the transistor Kb of conducting, realizes the function of voltage holding circuit.
Yet when having transistor in desiring access memory cell, the function of voltage holding circuit can be resisted with the transistor in this storage unit in fact, and the access time is increased.As shown in Figure 2, begin bit line discharges that it is connected from time point tp1 if desire to have transistor in the access memory cell, at this moment, this bit-line voltage also is maintained at high level, so transistor Kb still is conducting, can attempt its drain voltage is maintained at high level, resist the discharge of this storage unit.So at time point tp1 at the beginning, desiring on the bit line that access memory cell connected, the decline rate of its bit-line voltage can be slower, and this makes that also the instantaneous time of bit-line voltage is elongated.By the time this storage unit makes this bit-line voltage drop to (just can trigger phase inverter Kc and begin anti-phase threshold level) behind the level Vt, and phase inverter Kc just can be anti-phase comes the grid of oxide-semiconductor control transistors Kb with high level voltage, with this transistor Kb is closed.Because meeting of the transistor in the storage unit and the antagonism of voltage holding circuit, make the voltage of bit line just can reach stable state through the long time, in other words, legacy memory 10 will wait the long time could finish a store access cycle, therefore, also reduced the usefulness of access.In addition, by the circuit structure among Fig. 1 as can be known, legacy memory 10 is when carrying out precharge, and all bit lines (row line) all can be by precharge, and this has also caused a large amount of meaningless power consumptions.
Please refer to Fig. 3. Fig. 3 is the circuit diagram of another legacy memory 20. be similar to the storer 10 among Fig. 1, storer 20 also with character line W (1) to W (M), bit line B (1) connects the memory cell array of matrix form to B (K), plan the respectively data of record with transistorized having or not among each storage unit D, also has a governor circuit 22, one column decoder 24A, one row decoder 24B, terminating circuit 26A, 26B and sensing amplifier 28. at each bit line B (1) to B (K), storer 20 also carries out precharge with transistor Ka, form the voltage holding circuit with phase inverter Kc and transistor Kb, and with transistor Ks as switch element with control each row line whether can with voltage transmission to sensing amplifier 28. and storer 10 different be, on each bit line of storer 20, each precharge transistor Ka is that whether conducting determines whether carrying out precharge according to switch element Ks. during storage unit on access one bit line, switch element conducting on this bit line, its corresponding precharge transistor just can stop precharge, change or do not change voltage on this bit line according to its recorded data by this storage unit. in other words, legacy memory 20 among Fig. 3 also is all bit lines to be carried out precharge comprehensively. similarly, voltage holding circuit in the storer 20 also can resist the discharge trend of storage unit, make its access time longer, being unfavorable for the lifting of access usefulness. another shortcoming of storer 20 is, can do not continued to be enabled and lasting conducting by the storage unit of access, power hungry. for example, if the storage unit of wanting access bit line B (1) and character line W (1) to occur simultaneously, when the switch element conducting of bit line B (1), precharge transistor Ka on the bit line B (1) can conducting, but the precharge transistor Ka of other bit line B (2) to the B (K) can conducting, the voltage of these bit lines is maintained at high level. if in the storage unit that these bit lines and character line W (1) occur simultaneously transistor is arranged, these be biased in low level transistor will be between high level and low level conducting one direct current electric current, and consumed power constantly.
In order to overcome the above-mentioned shortcoming of traditional ROM (read-only memory), storer of the present invention adopts preferable voltage biasing structure, and the supplementary module on the line discharge of cooperation selective row and each row line is to reduce power consumption, enhancement access usefulness.Please refer to Fig. 4; Fig. 4 is the circuit diagram of storer 30 of the present invention.Storer 30 can be a ROM (read-only memory), is biased between the bias voltage V (for example being positive bias voltage Vdd) and low level ground terminal voltage G of high level.Have a plurality of storage unit D in the storer 30, each storage unit is used for writing down data (for example being one numerical data).Via each connection of row line (can be bit line) BL (1) to BL (K) and each row line (can be character line) WL (1) to WL (M), each storage unit D can connect the storage array that is arranged as matrix form.Each storage unit D can plan its recorded data content with having or not of n-type metal oxide semiconductor transistor.For example, do not have transistorized storage unit to can be used to the data of recorded content, have the data that transistorized storage unit then can be used to write down digital " 0 " for numeral " 1 ".In order to realize technology of the present invention, the present invention makes transistor biasing in the storage unit in the bias voltage V of high level; As shown in Figure 4, the transistor in storage unit D, its grid are connected in corresponding characters line (row line), and its a drain/source then end is connected in corresponding bit lines (row line), and an end is biased in bias voltage V.
Except storage array, also be provided with a governor circuit 32, a column decoder 34A, a row decoder 34B, terminating circuit 36A, 36B and sensing amplifier 38 in the storer 30.In order to realize technology of the present invention, also be provided with supplementary module Le, a discharge module Ld and a switch element Qs of a correspondence on each row line.Wherein, governor circuit 32 is used for the running of master control storer 30, coordinates the time sequences between other each circuit; For example, governor circuit 32 can provide a discharge signal Dis to control the running of each row line.Terminating circuit 36A, 36B then can include redundant storage unit (dummy cell), impedance matching circuit or bias circuit etc. are used for supporting the interlock circuit of memory cell matrix. when wanting the storage unit of a certain given address of access, column decoder 34A, row decoder 34B can decode the row line (character line) and row line (bit line) at this storage unit place respectively. after the decoding, column decoder 34A can be via this storage unit of character line activation at this storage unit place, make this storage unit change or not change power supply electrical level (similarly being voltage) on its corresponding bit line according to its recorded data. wherein, power supply electrical level (voltage) on row line (bit line) is meant the power supply electrical level of each row line and storage unit connecting place; As shown in Figure 4, the power supply electrical level of the capable line of k bar (bit line), the power supply electrical level of node N (k) just. on the other hand, after row decoder 34B decoding, then can with row select signal C (1) to C (K) control respectively the switch element Qs. of each row line BL (1) to the BL (K) at each row line BL (1) to BL (K), switch element Qs on each row line can realize with a n-type metal oxide semiconductor transistor, its drain/source is connected between capable line and the sensing amplifier 38, grid then is controlled by corresponding row and selects signal, whether its power supply electrical level can be transferred to sensing amplifier 38. for example to control each row line, when the storage unit of a certain particular address of access, if this storage unit is connected on the capable line of k bar, row decoder 34B just can select signal C (k) to make switch element Q s conducting (the then not conducting of switch element Qs on other row line) on the capable line BL (k) via row, makes the power supply electrical level on the capable line BL (k) transfer to sensing amplifier 38 via the switch element Qs of conducting.38 of sensing amplifiers are used for the power supply electrical level size on the sense bit line, and interpretation goes out to desire access memory cell recorded data content in view of the above.
To BL (K), the supplementary module Le on each row line can be provided with a control module Qi (an available phase inverter is realized) and a driver element Qp (an available p type metal oxide semiconductor transistor is realized) at each row line BL (1).With the supplementary module Le on the capable line of k bar is that example illustrates, the activation that the control module Qi in this supplementary module comes control drive unit Qp according to the power supply electrical level (being the voltage of node N (k)) on row line BL (k) whether.When the power supply electrical level scope of row line BL (k) is higher than the threshold level of control module Qi and Be Controlled unit Q i when being judged as a high level logic " 1 ", the control module Qi that realizes with phase inverter will make driver element Qp activation with anti-phase low-level logic " 0 ".Understand conducting after the driver element Qp activation and drive the power supply electrical level of drawing high capable line BL (k), make it reach the level of bias voltage V.On the contrary, when Be Controlled unit Qi is judged as a logical zero if the power supply electrical level scope of row line BL (k) is lower than the threshold level of control module Qi, control module Qi will make driver element Qp anergy and stop conducting with anti-phase logical one, and driver element Qp also will stop to influence the power supply electrical level of capable line BL (k).
On the other hand, each row discharge module Ld on line then can be provided with a drawing unit Qn (an available n-type metal oxide semiconductor transistor realizes) and a judging unit Qa (available one realize with door).With the discharge module Ld on the capable line BL of k bar (k) is example, and the judging unit Qa among this discharge module Ld can comprehensively select signal C (k) and discharge signal Dis to judge whether to want activation drawing unit Qn according to row.In the embodiment of Fig. 4, when row selects signal C (k) and discharge signal Dis to be all logical one, will make the Qn activation of drawing unit with the logical one of high level with judging unit Qa, and the drawing unit Qn of conducting activation just can drag down/be maintained at low level ground terminal voltage with the power supply electrical level of row line BL (k) with the door realization.Relatively, as long as row selects have one to be logical zero among signal C (k) and the discharge signal Dis, judging unit Qa can not make the Qn activation of drawing unit, and drawing unit Qn just can not change/influence the power supply electrical level on the row line BL (k).
The situation of storer 30 runnings of the present invention can be described below.During the given storage unit D of on wanting accessed row line BL (k) one, row decoder 34B can make the switch element Qs conducting (it then is logical zero that the row of other row line is selected signal) on the capable line BL (k) with the row selection signal C (k) of high level logic " 1 ", and governor circuit 32 also can send the discharge signal Dis of logical one earlier.The discharge signal Dis of integrated logic " 1 " selects signal C (k) with row, discharge module Ld on row line BL (k) will come into operation, and the power supply electrical level (voltage of node N (k) just) on the line BL (k) of will going drags down/be maintained at the level of ground terminal voltage G.At the same time, the discharge module on other row line can be that logical zero does not operate because of the row selection signal of its correspondence then.Like this, also just realized selective row line discharge mechanism of the present invention, only to desiring the capable line discharge at access memory cell place, other row line then need not discharge, and saves legacy memory because of all row lines are carried out the highly energy-consuming that precharge was caused comprehensively with this.
Next, after finishing discharge, governor circuit 32 can make discharge signal Dis transfer low level logical zero to, discharge module Ld on all row lines is decommissioned. and column decoder just can come this desire access memory cell of activation via desiring the capable line (character line) that access memory cell connected, make this desire access memory cell can influence the power supply electrical level of corresponding row line BL (k) according to the data content (just transistorized having or not) of its record. if be provided with transistor in this storage unit, this transistor will conducting after activation, to row line BL (k) charging. will go the voltage level of line BL (k) when the transistor in the storage unit and charge to more than a certain threshold level (in fact being exactly the threshold level of control module Qi), supplementary module Le on the row line BL (k) will begin to start, control module Qi in it can make driver element Qp begin conducting, transistor in storage unit will be gone the power supply electrical level of line BL (k) and be drawn high to the high level of bias voltage V. because that the enhancing of auxiliary unit drives is auxiliary, the level of row line BL (k) can reach the high level of stable state quickly. on the other hand, if do not have transistor in the storage unit, the power supply electrical level of row line BL (k) can be maintained at the low level of ground terminal voltage. and after the voltage of the line BL (k) that is expert at reached stable state, sensing amplifier 38 just can come interpretation to desire recorded data content in the access unit according to the power supply electrical level of row line BL (k).
By above-mentioned discussion as can be known, because storer 30 of the present invention has changed the bias voltage configuration, just the holding circuit in the legacy memory can be converted into the supplementary module in the storer of the present invention.In legacy memory, when in desiring access memory cell transistor being arranged, the holding circuit in the legacy memory can be resisted the trend that discharges and recharges of memory cell transistor, and the anti-instantaneous time time that access is interrogated in changing increases, and has reduced access usefulness.In comparison, in storer of the present invention, when the desire access memory cell had transistor, supplementary module can strengthen this transistorized trend that discharges and recharges, and so just can effectively shorten the instantaneous time in the store access cycle, promoted access usefulness.
For further specifying the operation situation of storer of the present invention, please refer to Fig. 5 (and in the lump with reference to figure 4); The waveform sequential synoptic diagram of related signal when Fig. 5 operates for storer 30 of the present invention, the transverse axis of Fig. 5 is the time, the longitudinal axis of each waveform is the height of power supply electrical level.In Fig. 5, the storage unit of supposing the desire access is the storage unit that row line WL (m) and row line BL (k) occur simultaneously.When store access cycle begins, governor circuit 32 (Fig. 4) can send the discharge signal Dis of logical one earlier, cooperate the capable selection of the logical one signal C (k) that is used for making on-off circuit Qs conducting on the row line BL (k), discharge module Ld on the row line BL (k) will begin the discharge to row line BL (k) from time point t0, carries out a discharge procedures.Discharge module Ld supposed that before time point t0 row line BL (k) goes up and is high level, so after time point t0, will be discharged to low level ground terminal voltage G with the voltage on the row line BL (k).Arrived time point t1, the power supply electrical level of row line BL (k) has reached stable state, and governor circuit 32 stops to send the discharge signal Dis of logical one, and the discharge module Ld on the capable line BL (k) is failed.Arrived time point t1, column decoder 34A (Fig. 4) just can go up with high level logic " 1 " at row line WL (m) and come activation to desire access memory cell.Supposing to desire has transistor in the access memory cell, and this transistor will begin the activation conducting behind time point t1, and the power supply electrical level of line BL (k) of will going up fills; Arrived time point t2, voltage on the row line BL (k) surpasses the anti-phase threshold level Vt of control module Qi, supplementary module Le on the row line BL (k) will open moving running, assist the transistor in the storage unit together row line BL (k) to be charged, make the power supply electrical level on the capable line BL (k) can reach high level more quickly.After power supply electrical level on the row line BL (k) reached stable state, sensing amplifier 38 just can just be judged the data content of desiring in the access memory cell according to the power supply electrical level of row line BL (k), and finishes this store access cycle.
Comprehensive above the discussion as can be known, the present invention can overcome the comprehensive precharge of highly energy-consuming in the prior art with optionally going discharge mechanism, and the holding circuit that can resist storage unit in the legacy memory can be converted into the supplementary module that can strengthen storage unit, make the power consumption of storer of the present invention lower, access usefulness is also better.In addition, discussed as previous, in the legacy memory of Fig. 3, even do not desire the storage unit of access on certain delegation's line, but the storage unit on this row line still might continue the conducting DC current because of comprehensive precharge, and consumed energy.Legacy memory in Fig. 3, storer of the present invention is then because be optionally capable line discharge, if do not desire the storage unit of access on certain delegation's line, just do not have storage unit and on this journey line, continue the conducting DC current, avoided meaningless power consumption.
In the example of Fig. 5, row line BL (k) its initial power supply electrical level when store access cycle begins is a high level, so its corresponding discharge module can operate practically and discharge. but, the initial power supply electrical level of row line BL (k) when store access cycle begins is to depend on that this row line is previous by the storage unit of access in fact. if row line BL (k) goes up previous is not have transistorized storage unit in the storage unit of access, the level of row line BL (k) can be maintained at low level. and when waiting next time storage unit on the accessed row line BL (k) again, the initial power supply electrical level of row line BL (k) will be a low level; In this case, even the discharge module Ld on the row line BL (k) can be enabled, this discharge module Ld does not need actual power consumption to discharge yet, because the power supply electrical level of row line BL (k) had been a low level just originally.
In addition, storer 30 of the present invention can be used as driver element Qp among the supplementary module Le with p type metal oxide semiconductor transistor, n-type metal oxide semiconductor transistor in the cooperation of the driver element Qp among supplementary module Le storage unit is together when the corresponding row line charges, even n-type metal oxide semiconductor transistor may can't charge to bias voltage V with the row line fully because of the restriction in the running, p type metal oxide semiconductor transistor still can charge to the power supply electrical level of corresponding row line the high level of bias voltage V fully.This also is one of additional functionality of supplementary module of the present invention.
In some memory construction, be to desire the capable line at access memory cell place, and the present invention also can be applicable to the storer of this kind structure with the addressing of decoding of layer-stepping (hierarchical) mechanism.Please refer to Fig. 6; Fig. 6 is the circuit diagram of another embodiment 40 of storer of the present invention.Be similar to the storer 30 among Fig. 4, also be provided with each row line BL, each row line WL in the storer 40 and be arranged as storage array so that each storage unit D is connected.Similarly, also be provided with column decoder 46A, row decoder 46B and relevant terminating circuit in the storer 40, also be provided with corresponding discharge module Ld and supplementary module Le on each row line.Comparatively different is that except corresponding switch element Qs is arranged, the capable line of every K bar is also shared the same switch element QsH that is realized by n-type metal oxide semiconductor transistor on every capable line, to constitute the capable choice mechanism of layer-stepping of two-layer.Equivalence just is considered as one group of row line with the capable line of every K bar; The 1st to the capable line of K bar be the capable line of K bar in the 0th group, the capable line of K+1 to 2*K bar then is the capable line of K bar in the 1st group, by that analogy; The capable line of k bar in the p group is exactly the capable line of (p*K+k) bar in all row lines.The switch element configuration of corresponding layer-stepping, row decoder 46B selects signal C (1) to control the capable line of K bar in same group respectively to C (K) with row, and selects signal CH (1) to control/select not on the same group capable line respectively to CH (p) or the like with row.Equivalence, this row decoder is to go pre decoding in fact; When a certain particular row line of addressing, it is the capable line of which bar that belongs in which group row that this row decoder decodable code goes out this row line.For example, when wanting the storage unit of a certain address of access, if decoding this storage unit, row decoder 46B belongs to the capable line of k bar in the p group row line, row decoder 46B just can send the signal CH (p) and the C (k) of logical one, makes the power supply electrical level on this row line transfer to sensing amplifier 48 via switch element Qs, the QsH of conducting.
For cooperating the row decoding mechanism of hierachical structure, be used among the present invention realizing that the discharge module Ld of selective row line discharge also can revise its design accordingly.Organizing the capable line of k bar with p among Fig. 6 is example (the capable line of (p*K+k) bar in all row lines just), among the discharge module Ld on this journey line, judge module Qa can be realized by one or three inputs and door, judge whether to make corresponding drawing unit Qn activation with comprehensive signal Dis, CH (p) and C (k).So, just can in the storer of hierachical structure, realize the technology of selective row line discharge of the present invention.
Generally speaking, compared to existing/traditional storer, storer proposed by the invention has adopted the mechanism of selective row line discharge to overcome the comprehensive precharge of highly energy-consuming of legacy memory, and the voltage holding circuit in the legacy memory is converted into supplementary module in the storer of the present invention with improved voltage biasing structure, can not only overcome the access time of elongating because of antagonism between storage unit and holding circuit, storer of the present invention can also shorten the access time energetically, so can effectively be promoted access usefulness.In storer of the present invention, each judging unit, drawing unit, driver element, control module and switch element can be realized with various different circuit.For example, in the embodiment of Fig. 4, switch element Qs realizes with n-type metal oxide semiconductor transistor, but switch element of the present invention also can be realized with transmission grid (transmission gate).
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. memory circuitry includes:
The storage unit of arranging with the form of matrix, wherein each storage unit can a corresponding delegation line and a row line;
At least one discharge module, it is linked to respectively on separately this row line accordingly, desires this row line at this storage unit place of access in order to discharge;
At least one supplementary module, it is connected to this discharge module separately respectively accordingly; And
One sensing amplifier is linked to this supplementary module, and in order to the power supply electrical level according to this row line, access goes out this storage unit;
Wherein this memory circuitry can select signal to desire this row line of this storage unit place correspondence of access in order to select discharge according to a discharge signal and delegation;
Wherein when this storage unit of desiring access was enabled, the power supply electrical level of this row line at this storage unit place changed, and wherein when the power supply electrical level of this row line surpassed a threshold level, this supplementary module made the power supply electrical level of this row line more increase.
2. memory circuitry as claimed in claim 1, wherein this memory circuitry also includes: a main control module, in order to send this discharge signal; One row decoder is linked to this main control module, and in order to decoding this row line of desiring this storage unit place of access, and the described row of this row line of activation correspondence is selected signal; And a column decoder, being linked to this main control module, the row line at this storage unit place of access is desired in decoding, and via this row line of desiring this storage unit place of access, this storage unit of activation.
3. memory circuitry as claimed in claim 2, wherein this storage unit can be provided with or not be provided with a transistor, wherein when this storage unit has this transistor, writes down one data, when this storage unit not during this transistor, does not write down any data; Wherein when this storage unit was enabled for this transistor and this storage unit, then this transistor made the power supply electrical level of this row line change to this row line charging.
4. memory circuitry as claimed in claim 1, wherein this discharge module includes a drawing unit and a judging unit; Wherein this judging unit judges whether to utilize this row line of this drawing cell discharge according to the level of this discharge signal and this row line selection signal.
5. memory circuitry as claimed in claim 1, wherein each this row line includes a switch, be connected between this supplementary module and this sensing amplifier, the described row that receives this row line is selected signal, whether be linked to this sensing amplifier in order to control this row line, wherein when this row line selects signal to be enabled, make this corresponding row line be connected to this sensing amplifier.
6. memory circuitry as claimed in claim 1, wherein this supplementary module includes a control module, an and driver element, wherein when the power supply electrical level of this row line surpasses this threshold level, if this storage unit has a transistor, then this control module makes this driver element conducting, in order to more to increase the power supply electrical level of this row line, if this storage unit is this transistor not, then make the power supply electrical level of this row line be maintained at the earth terminal power supply electrical level.
7. selectivity discharge memory circuitry includes:
A plurality of storage unit are arranged in the form of matrix, and wherein each this storage unit can a corresponding delegation line and a row line; And
A plurality of discharge modules, it is connected to respectively on separately this row line accordingly, receives a discharge signal and delegation and selects signal in order to this row line is discharged;
Wherein utilize this discharge signal and this row to select signal to desire this row line at this storage unit place of access in order to select discharge.
8. selectivity discharge memory circuitry as claimed in claim 7, wherein this memory circuitry also includes: a main control unit, in order to send this discharge signal; One row decoder is linked to this main control unit, and in order to decoding this row line of desiring this storage unit place of access, and this row of activation correspondence is selected signal; And a column decoder, be connected to this main control unit, desire the row line at this storage unit place of access in order to decoding.
9. selectivity discharge memory circuitry as claimed in claim 7, wherein this discharge module includes: a drawing unit and a judging unit; Wherein this judging unit is selected the level of signal according to the described row of this discharge signal and this row line, judge whether to utilize this row line of this drawing cell discharge, wherein select signal all during activation when the described row of this discharge signal and this row line, this row line then discharges.
10. selectivity as claimed in claim 7 discharge memory circuitry, wherein this memory circuitry also includes at least one supplementary module, and it is connected to this discharge module separately respectively accordingly, in order to the rising of the power supply electrical level that quickens this row line; One switch is connected to this supplementary module; And a sensing amplifier, be connected to this switch, utilize the power supply electrical level of this row line of this sensing amplifier that connects to read out the data of this storage unit; Wherein this switch is accepted feasible this row line of desiring this storage unit place of access of this row selection signal and can be connected to this sensing amplifier.
11. the method for storer selectivity discharge, wherein this storer includes a plurality of storage unit and arranges with matrix form, and wherein each this storage unit all has corresponding a delegation's line and a row line, and wherein this method includes:
Activation one discharge signal; And
The capable line of this storage unit of access is desired in decoding one, and activation is to going delegation's line selection signal of line;
Wherein select signal all during activation when this discharge signal and to going line, this row line discharges.
12. the method for a storage access, wherein this storer includes a plurality of storage unit and is arranged in matrix form, and wherein each this storage unit all has corresponding a delegation's line and a row line, and this method includes:
Capable line and this row line that discharges at this storage unit place of access desired in decoding;
Decoding is desired the row line at this storage unit place of access and via this this storage unit of row line activation, makes the power supply electrical level of this row line at this storage unit place change; And
According to the power supply electrical level of this row line, this storage unit of access;
Wherein when the power supply electrical level of this row line surpassed the threshold level of a control module, conducting one driver element made the power supply electrical level of this row line more increase.
13. as the access method of storage of claim 12, wherein select signal, according to the level of this a row line selection signal and a discharge signal, in order to discharge or this row line that stops to discharge according to delegation's line of decoded results activation correspondence.
14. as the access method of storage of claim 12, wherein when the power supply electrical level of this row line was lower than the threshold level of this control module, this driver element of stop conducting made the power supply electrical level of this row line not change.
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| CN1371101A (en) * | 2001-02-22 | 2002-09-25 | 三星电子株式会社 | Digit line setting and discharge circuit for programming nonvolatile memory |
| CN1495904A (en) * | 1998-01-28 | 2004-05-12 | ������������ʽ���� | Semiconductor memory, semiconductor device, and control method for semiconductor device |
| CN1503271A (en) * | 2002-11-21 | 2004-06-09 | ��ͳ�Ƽ��ɷ�����˾ | Single-ended SRAM |
| WO2006013632A1 (en) * | 2004-08-05 | 2006-02-09 | Fujitsu Limited | Semiconductor memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1495904A (en) * | 1998-01-28 | 2004-05-12 | ������������ʽ���� | Semiconductor memory, semiconductor device, and control method for semiconductor device |
| CN1371101A (en) * | 2001-02-22 | 2002-09-25 | 三星电子株式会社 | Digit line setting and discharge circuit for programming nonvolatile memory |
| CN1503271A (en) * | 2002-11-21 | 2004-06-09 | ��ͳ�Ƽ��ɷ�����˾ | Single-ended SRAM |
| WO2006013632A1 (en) * | 2004-08-05 | 2006-02-09 | Fujitsu Limited | Semiconductor memory |
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