CN1832335B - A CMOS Ultra Wideband Low Noise Amplifier - Google Patents

Abstract

The invention belongs to the technical field of radio frequency integrated circuit design, in particular to a CMOS low-noise amplifier (LNA) circuit used in an ultra-wideband (UWB) system receiver. This circuit is composed of matching stage, amplifier stage and load stage. Among them, the matching stage makes the signal source and the input impedance well matched; the amplifier stage not only ensures high gain and a certain input real impedance, but also enables the circuit to work at low voltage; Gain is flat. This circuit can achieve high gain at low power consumption, and the structure is also suitable for differential applications.

Description

A CMOS Ultra Wideband Low Noise Amplifier

technical field

The invention belongs to the technical field of radio frequency integrated circuit design, in particular to a CMOS ultra-wideband low-noise amplifier circuit capable of achieving high gain, low noise and good input matching under low-power applications and suitable for low-voltage applications.

Background technique

Ultra-wideband (UWB) technology originated in the late 1950s, and was mainly used as a military technology in communication equipment such as radar. With the rapid development of wireless communication, people have put forward higher requirements for high-speed wireless communication, and ultra-wideband technology has been proposed again, and has attracted much attention. UWB is different from common communication methods that use continuous carrier waves. It uses extremely short pulse signals to transmit information. Usually, the duration of each pulse is only tens of picoseconds to several nanoseconds. The bandwidth occupied by these pulses can even be as high as several GHz, so the maximum data transmission rate can reach hundreds of Mbps. At the same time of high-speed communication, the transmission power of UWB equipment is very small, only a few hundredth of that of existing equipment, which is similar to noise for ordinary non-UWB receivers, so theoretically speaking, UWB can communicate with existing There are radios that share the bandwidth. Therefore, UWB is a high-speed and low-power data communication method, and it is expected to be widely used in the field of wireless communication. At present, well-known large companies such as Intel, Freescale, and Sony are developing and promoting UWB wireless devices.

The U.S. Federal Communications Commission (FCC) announced in 2002 the UWB frequency band that allows civilian use, namely 3.1-10.6 GHz. At present, there are two schemes in the definition of the UWB system, direct sequence (DS-CDMA) and multi-band OFDM (MB-OFDM). In order to avoid conflict with the 5GHz working frequency band of WLAN-802.11a, the current scheme is roughly divided into two large frequency bands: the low frequency band is approximately 3.1-5.2 GHz, which is used as the development frequency band of the first generation UWB system; the high-frequency band is approximately 5.8-5. 10.6GHz. In addition, in the system structure of these two kinds of schemes, have used the indispensable module in the wireless communication—Low Noise Amplifier (LNA) .

The Low Noise Amplifier is one of the most critical blocks in the front end of an RF receiver. In a traditional narrowband LNA, the circuit is generally required to have a low noise figure, suitable gain, good input matching and high linearity. In an ultra-wideband system with a bandwidth of several GHz, due to the high operating frequency of the circuit, good input matching and flat and appropriate gain in the entire frequency band are the most important and most difficult performance requirements besides noise characteristics.

For UWB systems, low power consumption is a basic requirement. However, due to the large noise in the input signal, according to the system noise cascading formula, the low-noise amplifier at the receiving end must provide sufficient gain to ensure that the noise in the subsequent stage will not have an excessive impact on the system performance. At the same time, enough The gains require high power consumption to achieve. Therefore, there is a certain contradiction between the gain requirement and the power consumption requirement of the LNA. How to increase the gain as much as possible while reducing the power consumption is an important issue applied to the LNA design in the UWB system.

Secondly, due to the high operating frequency of the UWB system, in chip-level design, in order to increase the cut-off frequency of the MOS tube, a process with a small feature size, such as 0.18 μm or smaller, is often used, and the small-sized MOS tube is often accompanied by It is low voltage operation. For practical circuits, in order to reduce the interference of substrate noise, a differential structure with a current mirror is often used, and the current mirror consumes a part of the overdrive voltage, which highlights the difficulty of designing under low voltage. Therefore, designing a low-noise amplifier capable of operating at a low voltage is an inevitable challenge for ultra-wideband chip-level design.

In JSSC 2004, literature [1] proposed a structure based on traditional narrowband LNA, which consumes very little power, but it uses a source negative feedback structure, making the circuit gain only 9.6dB. For UWB systems, This cannot meet the system requirements; and the output terminal of this structure is connected with a load resistor of about 100Ω, which consumes a certain voltage margin, so it is not suitable for differential applications with current mirrors under low voltage.

references:

[1]Andrea Bevilacqua, Ali M Niknejad.An Ultrawideband CMOS Low-Noise Amplifier for3.1-10.6-GHz Wireless Receivers[J].IEEE J Solid-State Circuits,2004,39(12):2259-2268.

Contents of the invention

The object of the present invention is to design a circuit structure of a CMOS low noise amplifier which is applied to a UWB system receiver and has high gain under low power consumption and is suitable for low voltage operation.

The CMOS low-noise amplifier circuit designed by the present invention is composed of a matching stage 1, an amplifying stage 2 and a load stage 3 connected sequentially, wherein the matching stage is a multi-order inductor-capacitor series-parallel combined network, the amplifying stage is a CMOS circuit, and the load stage is Inductor resistor series circuit. Its structure is shown in Figure 1.

The function of each part is as follows: the matching network makes the signal source and the input impedance well matched; the amplifier stage ensures high gain and a certain input real impedance, and at the same time enables the circuit to work at low voltage; the load stage is an inductor and a resistor in series, Ensure that the circuit has a certain gain and a flat gain within the operating frequency band.

In the present invention, the equivalent input circuit of the matching stage and the amplifying stage together form a second-order or higher-order LC band-pass filter network, which is connected with the amplifying stage circuit through a series inductance.

In the present invention, the amplifier stage circuit is composed of a PMOS transistor and two NMOS transistors, wherein one PMOS transistor and one NMOS transistor are connected with a common gate and common drain to form a PMOS-NMOS pair, and the input signal enters from the gate and outputs from the drain; The source of the PMOS transistor is connected to a series inductor, and the source of the NMOS transistor is grounded or connected to a current mirror; the other NMOS transistor other than the PMOS-NMOS pair adopts a common gate connection method, that is, its source and the drain of the PMOS-NMOS pair Directly connected, the gate is connected to the bias DC voltage, and the drain is connected to the load stage.

In the present invention, the load stage is an inductance-resistance series circuit, the resistance terminal is connected to the power supply, and the inductance terminal is connected to the drain of the common-gate NMOS transistor.

There are three matching methods: resistor negative feedback, common gate input and matching network matching. The resistance negative feedback method can obtain better matching performance while increasing the gain, but this method introduces a feedback loop between the input and output, so the stability is poor. The common gate input method does not require a complex matching network, but precisely because the input needs to match the signal source, the gain of the input stage will be greatly affected, which will directly lead to the deterioration of the noise performance of the circuit. Based on the above considerations, the present invention adopts a matching network matching method.

The matching network of this circuit is a multi-order LC node pass-wave network, which is essentially an LC band-pass filter. Its function is to transform the input impedance generated by the amplifier stage to the signal source impedance to ensure input matching, that is, the circuit can obtain higher input power. Since the matching bandwidth reaches several GHz, the input matching network requires at least the second order, and the higher the frequency band, the higher the order requirement. In the selection of the matching network structure, considering the characteristics of integrated circuit implementation, that is, the bondwire of the chip pin is an inductor, and the filter is preferably a T-shaped structure. Figure 2 shows a circuit example of a second-order LC filter. Among them, R _s is the resistance of the input signal source, R _in is the equivalent input resistance of the amplifier stage, L ₂ is the sum of the inductance L _g connected between the matching stage and the amplifier stage and the series inductance L _i of the amplifier stage, and C ₂ is the inductance of the amplifier stage equivalent series capacitance.

其中L_p为串接电感感值，C_gsp为M_p管栅源电容。由于NMOS管M_n1迁移率比M_p大，在TSMC0.18μm RF工艺中，两者的比值达到5∶1，也即NMOS在放大能力上要强于PMOS，所以为了保证电路高增益，选择NMOS管M_n1作为主要的放大级；同时，为了克服电感负反馈的缺点，M_n1管没有接入串接电感，而是采用了共源连接，即图3中的M_n1管的源极在单端应用时接地或者在双端应用时接电流镜，以保证同样的功耗下能够达到更大的增益。The amplifier stage is the core part of this circuit, and its circuit structure is shown in Figure 3. Its input is a PMOS-NMOS pair. The source of the PMOS tube M _p is connected to the inductance L _p , and the inductance and the MOS tube are connected in series to generate real impedance , whose value is

Among them, L _p is the inductance value of the inductance connected in series, and C _gsp is the gate-source capacitance of the M _p tube. Since the mobility of the NMOS transistor M _n1 is larger than that of M _p , in the TSMC0.18μm RF process, the ratio of the two reaches 5:1, that is, the amplification capability of the NMOS is stronger than that of the PMOS. Therefore, in order to ensure the high gain of the circuit, the NMOS transistor is selected _Mn1 is used as the main amplification stage; at the same time, in order to overcome the shortcomings of inductive negative feedback, the _Mn1 tube is not connected to the series inductor, but uses a common source connection, that is, the source of the _Mn1 tube in Figure 3 is in the single-ended It should be grounded in application or connected to a current mirror in double-terminal application to ensure greater gain under the same power consumption.

The cascade stage is an NMOS transistor M _n2 connected with a common gate. On the one hand, this MOS tube reduces the output impedance of the input PMOS-NMOS pair tube to ensure that the PMOS-NMOS tube current amplification capability remains unchanged, while its voltage amplification capability is weakened. Then, according to the principle of the Miller effect, it can also be reduced. The impact of the small input tube gate-drain capacitance on the circuit; on the other hand, the MOS tube can isolate the input and output stages to ensure that the circuit has a good isolation.

The load stage of this circuit is an inductance resistance series circuit. In the design of narrow-band LNA, inductance-capacitor resonance is often used to select the required frequency. However, in broadband, gain flatness is a more important requirement. The parasitic capacitance at the load end will seriously attenuate the gain at the high-frequency end, so the inductance resistance is used in series. Among them, the inductance can weaken the influence of the capacitive load at the output end, and ensure that the circuit has a high output impedance in the high frequency band; the resistance can reduce the Q value of the inductance, so that the output impedance is flat in the working frequency band, instead of simple LC resonance, that is, to ensure The gain is flat over the operating frequency band.

Improvement of the present invention and principle thereof

This circuit is aimed at the design purpose, that is, the two requirements of high gain under low power consumption and differential application under low voltage. It is proposed based on the widely used JSSC 2004 "An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6-GHz Wireless Receivers". The structure was improved.

First of all, corresponding improvements have been made for differential applications at low voltages. For the structure proposed above, it is assumed that it is applied in a differential structure with current mirrors. Since the load end adopts a resistance-inductance series structure, its resistance is about 100, if the single-end consumption current is 4mA, the resistance consumption voltage is 0.4V; in addition, if it is assumed that the current mirror of the differential pair tube consumes a voltage margin of 0.3V, then for For low-voltage (eg 1.8V) differential applications, the two-stage NMOS transistors connected by the cascode can only have an oversaturation voltage of 1.1V. For a radio frequency circuit with a certain linearity requirement and a large operating current, it is very difficult to realize, and the working state is unstable.

This circuit introduces a PMOS transistor on the conventional circuit to shunt it with the resistor branch to reduce the current consumed by the resistor, that is to say, to increase the voltage margin for MOS bias design. In addition, the voltage margin consumed by the PMOS tube is almost the same as that consumed by the isolated MOS tube on the resistance branch. That is to say, in a fully differential application with a current mirror, only three MOS tubes are connected in series from the voltage source to the ground, and the resistance is one less. level, improving the voltage margin of the design.

Secondly, it is improved for the purpose of low power consumption and high gain. Generally speaking, if only high gain is required, it can be achieved by multi-stage amplification, but with one more stage of amplification circuit, the power consumption will be doubled, which is not a reasonable choice for UWB applications. For the above structure, there is only one stage of amplification, and in order to achieve input matching, an inductance is connected to the source of the amplifying NMOS tube, that is, negative feedback is introduced, so that the circuit gain is very small, and the maximum in the working frequency band is only 9.6dB.

This circuit considers the two performances of input matching and gain separately. The input matching is achieved through the inductance connected to the source of the PMOS tube, and the NMOS tube that plays a major role in the gain is connected to a common source to avoid the influence of negative feedback on the gain. At the same time, due to current multiplexing, the circuit is only equivalent to one stage of amplification, which meets the requirements of low power consumption and high gain.

Description of drawings

Figure 1. Schematic diagram of the structure of a wideband LNA.

Figure 2. Illustration of a second-order matching network.

Figure 3. Schematic diagram of the amplification stage circuit.

Figure 4. Input Equivalent Circuit.

Figure 5. Example circuit diagram.

Figure 6. Example S11 simulation results.

Figure 7. Example S21 and NF simulation results. Among them, the frequency at point A is 3.96G, the gain S21 is 16.0755dB; the frequency at point B is 3.60593G, and the noise figure is 1.65093dB.

Figure 8. Example kf simulation results. Among them, the frequency at point A is 5.77175G, and the stability coefficient is 10.7384.

Figure 9 illustrates the IIP3 simulation results.

Detailed ways

The specific implementation of the present invention mainly includes three parts: the design of the matching stage, the design of the amplification stage, and the design of the load stage.

The matching network is essentially a band-pass LC filter. According to the traditional filter design method, after determining the input and load resistance, it is necessary to look up the required order filter according to the requirements of the pass band and stop band. parameters of each component. However, the premise of this method is that the load resistance should have a certain value. For this LNA, since the output load is:

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&omega;</span>}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gsp</span>}}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Where ω is the operating angular frequency, L _p is the inductance connected to the source of the PMOS tube, and C _gsp is the gate-source capacitance of the PMOS tube. It can be seen from the formula (1) that the output load of the filter is a frequency-dependent value. Therefore, the traditional filter design method cannot achieve matching well.

Based on the above reasons, when implementing the input matching network of this circuit, the traditional filter design method is not referred to, but a more practical method is used. Considering that any input impedance can correspond to the points on the Smith chart, you can draw the input impedance of different frequency points on the Smith chart, and then observe the input impedance of each frequency point after passing through a certain reactive element. position, until all the frequency points are transformed by several components, they can be distributed around the dots, and the purpose of matching is achieved. The specific implementation can use Smith circle diagram CAD tools, such as Smith Charter and so on.

For the design of the amplifier stage, it is mainly the selection of the size of the NMOS tube, and the requirements of gain and impedance matching must be considered comprehensively.

According to the expression of gain:

${\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; v</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; mn</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="g\; mp"\; filenames="H2006100256884E00011.png"\; state="\{\{state\}\}">g</figure-callout></span><figure-callout\; id="1"\; label="g\; mp"\; filenames="H2006100256884E00011.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; mp</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Among them, g _mn is the transconductance of the NMOS tube, g _mp is the small signal transconductance of the PMOS tube, and Z _out is the load of the output terminal. It can be seen from formula (2) that to increase the gain of the circuit, the size of the NMOS tube can be increased.

其中Γ为输入反射系数，Z_in为输入阻抗，Z_S为信号源阻抗，一般来说，输入阻抗的虚部可以通过匹配网络来消除，所以电路能够达到的最大的反射系数为：

因此，如果此处输入匹配要达到系统要求的最大值-10dB，就必须有R_in≥24Ω。图4是该电路输入端的等效电路，由电路可知，输入阻抗的实部为：Consider impedance matching requirements. because

Among them, Γ is the input reflection coefficient, Z _in is the input impedance, and Z _S is the signal source impedance. Generally speaking, the imaginary part of the input impedance can be eliminated by the matching network, so the maximum reflection coefficient that the circuit can achieve is:

Therefore, if the input matching here is to reach the maximum value -10dB required by the system, there must be R _in ≥ 24Ω. Figure 4 is the equivalent circuit of the input end of the circuit. It can be seen from the circuit that the real part of the input impedance is:

$\mathrm{<span\; class="notranslate">\; Re</span>}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; mp</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gsp</span>}}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; mp</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C\; gsn"\; filenames="H2006100256884E00011.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="2"\; label="C\; gsn"\; filenames="H2006100256884E00011.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">gsn</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gsn</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C\; gsp"\; filenames="H2006100256884E00011.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="2"\; label="C\; gsp"\; filenames="H2006100256884E00011.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}^{\mathrm{<span\; class="notranslate">gsp</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}\mathrm{<span\; class="notranslate">\; \&omega;</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gsp</span>}}\mathrm{<span\; class="notranslate">\; \&omega;</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gsn</span>}}\mathrm{<span\; class="notranslate">\; \&omega;</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, C _gsp is the PMOS gate-source capacitance, and C _gsn is the NMOS gate-source capacitance. It can be seen from the expression that as the size of the NMOS increases, C _gsn increases, and the real part of the input impedance decreases. That is to say, according to the requirements of gain and input matching, the size of the NMOS tube needs to take a reasonable value, so as to ensure that the gain can be increased as much as possible under the premise of satisfying the input matching.

The main function of the output stage is to weaken the influence of the output parasitic capacitance on the gain, so as to increase the flatness of the gain in the working frequency band. Since the output load impedance is:

${\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; ,</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

Among them, L _d is the inductance of the output load end, C _d is the parasitic capacitance of the output end, and R is the resistance connected in series with the inductance. It can be seen from expressions (2) and (4) that to increase the circuit gain, the inductance value can be increased, but it must be ensured that L _d C _d ω ² <1; to increase the circuit gain flatness, the resistor R can be increased, At the same time, increasing R will also reduce the output impedance, which requires a good compromise.

A concrete implementation example is given below.

As shown in Figure 5, this example circuit is a differential application with a current mirror, and its working frequency band is UWB Bandl, that is, 3.1-5.2 GHz. Its structure is illustrated with a single end. The input is a second-order LC band-pass filter, L ₁ , C ₁ , L _g1 and the equivalent inductance and capacitance of the amplifier stage constitute a matching network; M _n1 , M _p1 , M _n2 and L _p1 constitute the amplifier stage; L _d1 and R ₁ constitutes the load stage. At the output end, a source follower M _b1 is added as a Buffer on the originally designed circuit, and its output impedance is 50Ω to facilitate the test of the output end.

The simulation of this circuit is based on the TSMC 0.18μm RF process, using the Cadence SpectreRF tool. The power supply voltage is 1.8V, and the double-terminal consumption current of this example circuit is 8mA. The simulation results are shown in Figure 6 to Figure 8. The results show that in the working frequency band, the matching degree S11 can reach below -10dB, and the gain S21 with Buffer is 16dB. Generally speaking, the Buffer will reduce the gain by about 3dB, so the gain of this circuit is about 19dB. The noise figure is 1.65～2.37dB, the stability factor can reach more than 10 in all working frequency bands, and the third-order intermodulation point IIP3 of the circuit is -10dBm, which shows that it has good linearity. It can still work stably, and can achieve high gain performance at low power consumption.

Claims (1)

1. a CMOS amplifier circuit in low noise is characterized in that being connected to form successively by matching stage (1), amplifying stage (2) and load stage (3), and wherein, matching stage is a multistage inductance capacitance connection in series-parallel combinational network, and amplifying stage is a cmos circuit;

The dummy input circuit of described matching stage and amplifying stage is common forms a second order or the above LC bandpass filtering of second order network, and it is connected by a series inductance with amplification grade circuit;

Described amplification grade circuit is made up of a PMOS pipe and two NMOS pipes, one of them PMOS pipe leaks altogether with the common grid of NMOS pipe and is connected, it is right to form PMOS-NMOS, input signal enters from grid, from drain electrode output, this PMOS pipe source electrode connects a series inductance, and this NMOS manages source ground or connects current mirror; Another NMOS pipe is grid level altogether, and the drain electrode that its source electrode and PMOS-NMOS are right directly is connected, and grid connects bias direct current voltage, drains to be connected with load stage;

Described load stage is an inductance resistance series circuit, the one termination power, and another termination is the drain electrode of grid NMOS pipe altogether.

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