CN1831925A - Semiconductor circuits, drive circuits for electro-optical devices, and electronic equipment - Google Patents

Abstract

The invention provides a semiconductor circuit and a driving circuit of electro-optical device. A semiconductor circuit includes a first circuit block, a second circuit block, and power wiring lines that supply a plurality of reference potentials. The first circuit block and the second circuit block are connected to a common power wiring line that is one of the power wiring lines and supplies a common reference potential. A width of the common power wiring line in the first circuit block is different from a width of the common power wiring line in the second circuit block.

Description

Semiconductor circuits, drive circuits for electro-optical devices, and electronic equipment

technical field

The present invention relates to a semiconductor circuit, a driving circuit of an electro-optical device, and electronic equipment.

Background technique

Semiconductor circuits realize complex functions through the combination of multiple circuit blocks. For example, a drive circuit for driving an electro-optical device such as a liquid crystal display device is composed of a plurality of circuit blocks corresponding to functions. In the above-mentioned circuit blocks, the power supply voltage supplied to operate the circuit elements may vary depending on the circuit block.

However, since the power supply wiring for supplying the power supply voltage has limited resistance, the potential on the wiring fluctuates temporarily when a large current flows. Furthermore, when a current with a density equal to or greater than a certain value flows in the power supply wiring, disconnection occurs in the power supply wiring due to Joule heat, migration, etc., resulting in a failure of the semiconductor circuit. The above-mentioned problems can all be avoided by increasing the line width of the power supply wiring and reducing the resistance and current density of the power supply wiring, but if the line width of the power supply wiring is increased corresponding to the instantaneous maximum current consumption of the semiconductor circuit, the semiconductor circuit area increases accordingly.

Here, Patent Document 1 proposes a method of suppressing the line width of the power supply wiring by suppressing the instantaneous maximum current consumption of the output buffer. In addition, Patent Document 2 proposes a method of optimizing the line width of power supply wiring whose voltage varies depending on the circuit block.

[Patent Document 1] Japanese Unexamined Patent Publication No. 7-273635

[Patent Document 2] Japanese Unexamined Patent Publication No. 9-69569

Functions required in semiconductor circuits are becoming more complex. For example, drive circuits for electro-optical devices are increasing in speed and scale as electro-optical devices become larger and more high-definition. For this reason, techniques have been sought for suppressing an increase in circuit area by reducing the line width of the power supply wiring to the necessary minimum while preventing disconnection of the power supply wiring due to migration or the like.

Contents of the invention

An object of the present invention is to provide a semiconductor circuit, a drive circuit for an electro-optical device, and an electronic device that prevent an increase in the circuit area by preventing disconnection of power supply wiring due to migration or the like and minimizing the line width of the power supply wiring as necessary. equipment.

In order to solve the above-mentioned problems, the present invention provides the following techniques.

The semiconductor circuit of the present invention has a first circuit block, a second circuit block, and a power supply wiring for supplying a plurality of reference potentials, and is characterized in that: the first circuit block and the second circuit block are both connected to the power supply wiring One of them is on a common power supply wiring that supplies a common reference potential; the line width of the common power supply wiring is different between the first circuit block and the second circuit block.

According to this invention, in the semiconductor circuit, in the first circuit block and the second circuit block, the line width of the common power supply wiring supplying a common reference potential can be independently set. This makes it possible to set the common power supply wiring for supplying a common reference potential to suit the line widths of the first circuit block and the second circuit block. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the semiconductor circuit by minimizing the line width of the power supply wiring.

The driving circuit of the electro-optical device of the present invention has: a plurality of scanning lines and a plurality of data lines, a switching unit connected to the scanning lines and the data lines, and a pixel electrode connected to the switching unit, characterized in that: A circuit block, a second circuit block, and a power supply wiring for supplying a plurality of reference potentials; both of the first circuit block and the second circuit block are connected to a common power supply wiring which is one of the power supply wirings and supplies a common reference potential Above; the line width of the common power supply wiring is different between the first circuit block and the second circuit block.

According to this invention, in the first circuit block and the second circuit block of the driving circuit of the electro-optical device, the line width of the common power supply wiring supplying a common reference potential can be independently set. Accordingly, the power supply wiring can be set to suit the line widths of the first circuit block and the second circuit block. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring.

Here, the driving circuit of the above-mentioned electro-optical device preferably: the above-mentioned first circuit block includes: a shift register composed of a unit circuit that transmits a signal output to the above-mentioned scanning line and the above-mentioned data line in synchronization with a clock signal; The second circuit block includes a buffer circuit for driving the scanning lines and the data lines.

According to this, the functions of the first circuit block and the second circuit block are different from each other. Therefore, in general, the first circuit block and the second circuit block consume different currents. Since the line width of the power supply wiring is set according to the current consumption in the power supply wiring, even if the power supply voltage supplied to the circuit block is the same, it is possible to independently set the power supply wiring suitable for each power supply wiring and each circuit block. line width. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring.

Here, the driving circuit of the above-mentioned electro-optical device is preferably: the above-mentioned first circuit block includes: a shift register composed of a unit circuit that transmits a signal output to the above-mentioned scanning line and the above-mentioned data line in synchronization with a clock signal; A clock control circuit for controlling supply of the clock signal to the unit circuit is provided based on a result of determining whether or not the transmitted data has reached an active level.

According to this, in the first circuit block, the supply of the clock signal to the part whose state does not change even when the clock signal is supplied can be stopped, and the current consumption can be suppressed. Since the line width of the power supply wiring is set according to the current consumption in each power supply wiring, it is possible to suppress the line width of the power supply wiring of the first circuit block in consideration of the stop of supply of the clock signal. For example, preferably: in the 1st circuit block that has clock control circuit, the line width of power supply wiring is proportional to the square of the diagonal dimension of screen; In the 2nd circuit block, the line width of power supply wiring is proportional to 3 of the diagonal dimension of screen. power. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring.

Here, the driving circuit of the above-mentioned electro-optical device preferably: the above-mentioned first circuit block includes: a shift register composed of a unit circuit that transmits a signal output to the above-mentioned scanning line and the above-mentioned data line in synchronization with a clock signal; The second circuit block includes a level shift circuit for boosting a signal input from an external circuit for driving the drive circuit of the electro-optical device.

In a level shift circuit, a constant leakage current on the order of several μA to several tens of μA often flows. On the other hand, the current consumption of the first circuit block tends to be simply proportional to the diagonal size of the screen of the electro-optical device. Therefore, when the screen diagonal size of the electro-optic device is small, the ratio of the constant leakage current of the level shift circuit to the consumption current of the second circuit block becomes dominant, and the first circuit block and the second circuit block The difference in current consumption becomes significant. Here, since the line width of the power supply wiring is set according to the current consumption in each power supply wiring, the line width of the common power supply wiring suitable for each of the first circuit block and the second circuit block can be independently set. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring.

Here, the driving circuit of the above-mentioned electro-optical device preferably: the above-mentioned first circuit block includes: a shift register composed of a unit circuit that transmits a signal output to the above-mentioned scanning line and the above-mentioned data line in synchronization with a clock signal; The second circuit block includes a buffer circuit for outputting a signal input from an external circuit for driving the drive circuit of the electro-optical device to the first circuit block at a signal rise and fall time within a predetermined range.

According to this, the functions of the first circuit block and the second circuit block are different from each other. Therefore, in general, the first circuit block and the second circuit block consume different currents. Since the line width of the power supply wiring is set according to the current consumption in the power supply wiring, even if the power supply voltage supplied to each circuit block is the same, the power supply suitable for each power supply wiring and each circuit block can be independently set. The line width of the route. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring.

Here, the driving circuit of the above-mentioned electro-optical device preferably: the above-mentioned first circuit block includes: a shift register composed of a unit circuit that transmits a signal output to the above-mentioned scanning line and the above-mentioned data line in synchronization with a clock signal; The second circuit block includes a DA conversion circuit for driving the data line at a predetermined potential.

Since a DA conversion circuit generally has ladder resistors and amplifiers, it consumes more current than a general logic circuit such as a clock generation circuit (CGC), for example. On the other hand, the current consumption of the first circuit block tends to be simply proportional to the diagonal size of the screen of the electro-optical device. Therefore, when the screen diagonal size of the electro-optical device is small, the ratio of the current consumption of the DA conversion circuit of the second circuit block increases, and the difference between the current consumption of the first circuit block and the second circuit block becomes significant. Here, since the line width of the power supply wiring is set according to the current consumption in each power supply wiring, the line width of the common power supply wiring suitable for each of the first circuit block and the second circuit block can be independently set. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring.

Here, in the drive circuit of the electro-optical device, it is preferable that the first drive voltage as the difference between the maximum value and the minimum value of the plurality of reference voltages supplied to the first circuit block is the same as the first drive voltage supplied to the second circuit block. The second driving voltage of the difference between the maximum value and the minimum value of the plurality of reference voltages of the block is different.

According to this, the first circuit block and the second circuit block include the power supply wiring for supplying different reference potentials in addition to the common power supply wiring, and the driving voltages are different from each other. In this case, too, the line widths of the common power supply lines suitable for the first circuit block and the second circuit block can be independently set in consideration of the current consumption in each power supply line. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring.

Here, in the drive circuit of the electro-optic device, it is preferable that the potential supplied to the common power supply line is a potential different from the ground potential supplied to the drive circuit.

According to this, a potential other than the ground potential can be supplied through the common power supply wiring, and the line width of the common power supply wiring can be independently set for each circuit block. Here, VD, which is the highest reference potential, can be wired as a common power supply. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring.

In addition, in the electro-optic device, the above-mentioned driving circuit, a plurality of scanning lines and a plurality of data lines, a switch unit connected to the above-mentioned scan line and the above-mentioned data line, and a pixel electrode connected to the above-mentioned switch unit are formed on the same substrate Therefore, it is possible to further suppress an increase in the circuit area of the driving circuit of the electro-optic device.

Furthermore, by including the above-mentioned electro-optical device in electronic equipment, an increase in circuit area can be suppressed, and electronic equipment corresponding to further miniaturization and higher performance can be provided.

Description of drawings

FIG. 1 is a configuration diagram of an active matrix substrate 101 incorporating a driving circuit of a liquid crystal display device.

FIG. 2 is a circuit diagram showing the configuration of the scanning line driving circuit 301 according to the first embodiment.

FIG. 3 is a configuration diagram of the level shift circuit 351 .

FIG. 4 is a circuit diagram showing the configuration of a scanning line driving circuit 701 according to the second embodiment.

FIG. 5 is a configuration diagram of the interface level shift circuit 751 .

FIG. 6 is a circuit diagram showing the configuration of a data line driving circuit 302 according to the third embodiment.

7 is a perspective configuration view (partial sectional view) of a liquid crystal display device incorporating a driving circuit of an electro-optical device.

FIG. 8 is a perspective view showing the configuration of a mobile personal computer to which the above-mentioned electro-optical device is applied.

FIG. 9 is a perspective view showing the configuration of a mobile phone to which the above-mentioned electro-optical device is applied.

FIG. 10 is a perspective view showing the configuration of a portable information terminal to which the above-mentioned electro-optical device is applied.

Description of reference symbols

1. 100...electro-optic device, 101...active matrix substrate, 201...scanning line, 202...data line, 301...scanning line drive circuit, 302...data line drive circuit, 331, 731, 831...unit shift circuit (S/R), 332, 732, 832...bidirectional transmission circuit, 333, 733, 833...clock control circuit (CCC), 334, 734, 834 ...clock generation circuit (CGC), 751...interface level shift circuit (IF L/S), 851...DA conversion circuit, 335, 735, 835, 855...power supply for reference potential VS 336 , 353 , 736 , 836 , 853 . . . a power supply wiring for supplying a reference potential VD, and 354 . . . a power supply wiring for supplying a reference potential VB.

Detailed ways

1. First Embodiment

FIG. 1 is a configuration diagram of an active matrix substrate 101 incorporating a driving circuit of a liquid crystal display device according to a first embodiment of the present invention. Here, the liquid crystal display device as the electro-optical device 100 includes: a plurality of scanning lines 201 and a plurality of data lines 202, and connected to the scanning lines 201 and the data lines 202, which are composed of n-type thin film transistors (TFTs) using polysilicon thin films. A switch unit 401, and a pixel electrode 402 connected to the switch unit 401.

Specifically, a plurality of scanning lines 201 and a plurality of data lines 202 are formed to intersect in a display region 310 on an alkali-free glass active matrix substrate 101 included in a liquid crystal display device as an electro-optic device 100 . Further, a data line driver circuit 302 and a scan line driver circuit 301 as driver circuits formed by integrating thin film transistors (TFTs) using polysilicon thin films are formed on the active matrix substrate 101 . Here, the data line driving circuit 302, the scanning line driving circuit 301, and the switching unit 401 are manufactured in the same manufacturing process.

The data line 202 is connected to the data line driving circuit 302 and driven; the scanning line 201 is connected to the scanning line driving circuit 301 and driven. The numbers of scanning lines 201 and data lines 202 vary depending on the resolution of the liquid crystal display device, for example, in the case of a liquid crystal display device of VGA resolution, they are 480 and 1920, respectively.

To the scanning line driving circuit 301 and the data line driving circuit 302 , necessary electrical signals and potentials are supplied via mounting terminals 601 .

Furthermore, on the active matrix substrate 101 , a plurality of common lines (capacitance lines) 203 are arranged in parallel and alternately with the scanning lines 201 . The common lines 203 are short-circuited to each other by the common wiring 305 , and further connected to the opposing conduction portion 304 for conducting conduction to the common electrode of the opposing substrate.

In the display area 310 on the active matrix substrate 101 , at the intersections of the scan lines 201 and the data lines 202 , switch units 401 composed of N-channel field effect thin film transistors are formed. The gate electrode, source electrode and drain electrode of the switch unit 401 are respectively connected to the scan line 201 , the data line 202 and the pixel electrode 402 . When the liquid crystal display device is assembled, the counter electrode COM of the counter substrate is connected to the common line 203 through the counter conductive portion 304 . Then, a liquid crystal capacitor is formed by the pixel electrode 402 and the counter electrode COM of the counter substrate that faces across the liquid crystal material that is an electro-optical substance. In addition, an auxiliary capacitor is formed by connecting the capacitor electrode on the pixel potential side and the common line 203 in parallel with the liquid crystal capacitor.

FIG. 2 is a circuit diagram showing the configuration of the scanning line driving circuit 301 . The scanning line driving circuit 301 includes a first circuit block 330, a second circuit block 350, and power supply lines for supplying a plurality of reference potentials.

The first circuit block 330 is equipped with a clock control circuit (CCC) 333, a clock generation circuit (CGC) 334, a unit shift circuit (S/R) 331, a bidirectional transmission circuit 332, a NAND (NAND) circuit 337 and an inverting circuit. Logic circuit block of circuit 338 . The first circuit block 330 is driven with 8V, for example.

The bidirectional transfer circuit 332 is a circuit that easily realizes screen inversion by switching the transfer direction forward and reverse based on a direction signal (DIR signal) and a reverse direction signal (DIRX signal). When the direction signal (DIR signal) is 0V and the reverse direction signal (DIRX signal) is 8V, in the bidirectional transmission circuit 332, the signal is transmitted in the direction from bottom to top of FIG. 2; and, the direction signal (DIR signal) is 8V and When the reverse direction signal (DIRX signal) is 0 V, the bidirectional transmission circuit 332 transmits the signal in the direction from the top to the bottom in FIG. 2 .

The unit shift circuit (S/R) 331 as a unit circuit is also a latch circuit that outputs an input signal in synchronization with a clock signal. A plurality of unit shift circuits (S/R) 331 and a bidirectional transfer circuit 332 for slave-connecting these constitute a shift register. A start signal indicating the start of a frame period is input to the shift register. The unit shift circuit (S/R) 331 sequentially shifts the signal output to the scan line 201 synchronously with the clock signal and outputs it.

The clock control circuit (CCC) 333 supplies clock signals only before and after stages driven by the H level in the shift register and stops clock signals to other stages in order to prevent an increase in the electrostatic capacitance of the clock line. supplied circuit.

The clock generation circuit (CGC) 334 is to generate the bipolar clock signal required in the operation of the unit shift circuit (S/R) 331 by the unipolar clock signal, and prevent the positive and negative clocks from A circuit that malfunctions due to phase shift.

The second circuit block 350 is provided with: a level shift circuit (L/S) 351 for boosting the low-amplitude signal output from the first circuit block 330 into a high-amplitude signal, and a pass level shift circuit (L/S) 351 to drive the external interface circuit block of the buffer circuit 352 connected to the scanning line 201 of a plurality of switching circuits. FIG. 3 is a detailed circuit diagram of a level shift circuit (L/S) 351, which constitutes a so-called flip-flop type level shift circuit.

The power supply lines 335 , 336 , 353 , and 354 supply a plurality of reference potentials VS, VD, and VB to the scanning line driving circuit 301 . For example, the reference potential VS serving as the ground potential is set to 0V, the reference potential VD is set to 8V, and the reference potential VB is set to -4V. The power supply lines 336 and 353 supply a common reference potential VD to the first circuit block 330 and the second circuit block 350, respectively. The power supply wiring 335 supplies the reference potential VS to the first circuit block 330 . The power supply wiring 354 supplies the reference potential VB to the second circuit block 350 .

The first circuit block 330 receives 8V as the common reference potential VD and 0V as VS, and operates with 8V. The second circuit block 350 receives 8V as the common reference potential VD and -4V as VB, and drives with 12V.

In the first circuit block 330, the current consumption is reduced by driving with a power supply voltage on the low potential side of 8V; 8V is boosted to 12V to write to the scanning line 201 so that the writing to the pixel electrode 402 does not become insufficient. In addition, by setting the reference potential VD on the high potential side to 8V in common in the first circuit block 330 and the second circuit block 350; In the second circuit block 350, VB is -4V; however, the power supply wiring can be used as a common power supply wiring. By sharing the reference potential in this way, it is possible to reduce the number of mounting terminals and external power supply ICs, contributing to cost reduction and circuit area reduction.

In addition, the power supply wiring is connected to the power supply nodes of the circuit elements constituting each circuit, but in the figure, the connection to the circuit elements is omitted for convenience.

Here, the line width of the power supply wiring of the first circuit block 330 and the second circuit block 350 will be described.

In driving a normal liquid crystal display device, for example, among 480 scanning lines 201, only one scanning line 201 is simultaneously selected and driven at the H level. In this case, among the unit shift circuits (S/R) 331 constituting the shift register, there are two stages that output the H level corresponding to the selected scanning line 201 . In this case, the clock control circuit (CCC) 333 needs to supply the clock signal only to the unit shift circuit (S/R) 331 in total of 4 stages of two stages at H level and before and after. For the remaining 476 stages, in order to maintain the L level output as it is, the supply of the clock signal to the portion whose state does not change even when the clock signal is supplied is stopped. Therefore, the current consumption of the first circuit block 330 is approximately only the current consumption of circuits corresponding to the four stages. Furthermore, the current consumption is proportional to the driving frequency of the scanning lines 201 , and the driving frequency of the scanning lines 201 of the first circuit block 330 is proportional to the number of the scanning lines 201 . That is, as long as the frame rate is constant, the current consumption of the first circuit block 330 is proportional to the number of scanning lines 201 as shown in Equation 1.

Current consumption of the first circuit block 330

∝Driving frequency of scanning line 201 ∝Number of scanning lines 201......(Formula 1)

Therefore, even if the diagonal size of the screen becomes larger or the resolution becomes higher and the number of scanning lines 201 and the number of driving stages increase, the consumption current of the first circuit block 330 basically increases linearly according to the number of scanning lines 201. Increase.

On the other hand, the current consumption of the second circuit block 350 is proportional to the product of the driving frequency of the scanning line 201 and the capacitance of the scanning line 201 as shown in Equation 2.

Current consumption of the second circuit block 350

∝The driving frequency of the scanning line 201×the electrostatic capacitance of the scanning line 201... (Formula 2)

As long as the resolution is constant and the frame rate is constant, the number of scanning lines 201 , the capacitance of the scanning lines 201 and the driving frequency of the scanning lines 201 are proportional to the diagonal size of the display area 310 .

In the above case, the current consumption of the first circuit block 330 is proportional to the number of scanning lines 201, and the number of scanning lines 201 is proportional to the diagonal size of the screen. That is, the current consumption of the first circuit block 330 is proportional to the diagonal size of the screen as shown in Equation 3.

Current consumption of the first circuit block 330 ∝ Diagonal size of the screen ...................(Formula 3)

Moreover, the consumption current of the second circuit block 350 is proportional to the product of the driving frequency of the scanning line 201 and the electrostatic capacitance of the scanning line 201, and the driving frequency of the scanning line 201 and the electrostatic capacitance of the scanning line 201 are all proportional to the diagonal of the screen. size. That is, the current consumption of the second circuit block 350 is proportional to the square of the diagonal size of the screen as shown in Equation 4.

Current consumption of the second circuit block 350∝Screen diagonal size^2......(Formula 4)

Here, the drop voltage of the power supply at the end of the power supply wiring is the product of the current consumption of the power supply and the resistance of the power supply wiring as shown in Equation 5.

Drop voltage of power supply = current consumption of power supply × resistance of power supply wiring... (Formula 5)

Furthermore, the resistance of the power supply wiring is proportional to the quotient of the length of the power supply wiring and the line width of the power supply wiring as shown in Equation 6.

Resistance of power wiring ∝ Length of power wiring ÷ Width of power wiring...(Equation 6)

Furthermore, the length of the power wiring is similar to the size of the scanning line driving circuit 301 on the substrate; and the size of the scanning line driving circuit 301 on the substrate is similar to the vertical size of the screen; and the vertical size of the screen is proportional to the size of the screen. Diagonal size. That is, the length of the power supply wiring is proportional to the diagonal size of the screen as shown in Equation 7.

The length of the power wiring and the size of the scanning line driving circuit 301 on the substrate

Size in the vertical direction of the screen ∝ Diagonal size of the screen...................(Formula 7)

Therefore, if the line width of the power supply wiring is set so that the drop voltage due to the power supply wiring becomes less than or equal to a certain value, the minimum value of the line width of the power supply wiring of the first circuit block 330 is proportional to The square of the diagonal size of the screen.

The minimum value of the line width of the power wiring of the first circuit block 330

∝Screen Diagonal Size^2................................( Formula 8)

In addition, the minimum value of the line width of the power supply wiring of the second circuit block 350 is proportional to the third power of the diagonal size of the screen as shown in Equation 9.

The minimum value of the line width of the power wiring of the second circuit block 350

∝Screen diagonal size^3................................( Formula 9)

For example, when the diagonal size of the screen is 4 inches, the resolution of the display screen is VGA, the definition is 200ppi, the aspect ratio is 4:3, and the frame frequency is 60Hz, as the logic circuit block of the first circuit block 330 The line width of the power supply wiring is 30 μm, and the line width of the power supply wiring of the external interface circuit block as the second circuit block 350 is 100 μm. Therefore, the wiring widths of the power supply wirings 335 and 336 are respectively set to 30 μm, and the wiring widths of the power supply wirings 353 and 354 are respectively set to 100 μm.

In this way, since the current consumption differs between the first circuit block 330 and the second circuit block 350 , it is possible to set appropriate line widths of the power supply lines. That is, it is possible to reduce the voltage in the power supply wiring within a certain range, prevent the disconnection of the power supply wiring due to migration, etc., and suppress the loss of the driving circuit of the liquid crystal display device by making the line width of the power supply wiring the necessary minimum. increase in circuit area. Thereby, the frame of the liquid crystal display device can be reduced in size, and the cost can be reduced. According to Equation 8 and Equation 9, it can be seen that the effect is more significant when the screen size is larger, and the effect is more obvious when the resolution is higher.

In addition, although the scanning line driving circuit 301 using a shift register has been described here, the shift register of the present invention is not limited to this, and signals may be transmitted through unit circuits and receive signals from the clock control circuit (CCC) 333. Control of the clock signal. For example, a logic circuit such as a line sequence selection circuit using a flip-flop circuit or the like, or a timing generator using a counting circuit may be used.

2. Second Embodiment

This embodiment differs from the first embodiment in the configuration of a circuit for boosting a low-amplitude signal to a high-amplitude signal.

FIG. 4 shows a scanning line driving circuit 701 according to the second embodiment. The scanning line driving circuit 701 includes a first circuit block 730, a second circuit block 750, and power supply lines for supplying a plurality of reference potentials.

The first circuit block 730 includes a clock control circuit (CCC) 733, a clock generation circuit (CGC) 734, a unit shift circuit (S/R) 731, a bidirectional transfer circuit 732, a first buffer circuit 737, and a NAND circuit 738. logic circuit block. The first circuit block 730 and the second circuit block 750 are driven by, for example, 12V.

The bidirectional transfer circuit 732, the unit shift circuit (S/R) 731 as unit circuits, the clock control circuit (CCC) 733, and the clock generation circuit (CGC) 734 are the same as those in the first embodiment. Furthermore, the first buffer circuit 737 is a buffer circuit for driving the scanning line 201 to which a plurality of switch circuits are connected by the output signal of the unit shift circuit (S/R) 731 .

The second circuit block 750 is an external interface circuit block including an interface level shift circuit (IF L/S) 751 and a second buffer circuit 752.

The interface level shift circuit (IF L/S) 751 is a circuit for boosting a low-amplitude signal input from an external circuit such as an external IC to a high-amplitude signal in order to drive the drive circuit of the electro-optical device. FIG. 5 is its circuit Detailed circuit diagram. It is a level shift circuit called a capacitive coupling type, and although it can realize an output ratio of 3 to 4 times even with a relatively low-capacity polysilicon thin-film transistor like this embodiment, it is a configuration in which a leakage current flows constantly .

The second buffer circuit 752 is a circuit that improves the drive capability of the signal output from the interface level shift circuit (IF L/S) 751 in order to meet the rising and falling times of the signal required for the normal operation of the first circuit block 730, Similar to the buffer circuit 352, it can be realized by connecting a plurality of inverter circuits in series.

The power supply lines 735 and 736 supply a plurality of reference potentials VS and VD to the first circuit block 730 . For example, the ground potential VS is 0V, and the reference potential VD is 12V. Furthermore, the power supply lines 755 and 756 supply the reference potentials VS and VD to the second circuit block 750 .

The power supply wiring 735, the power supply wiring 755, and the power supply wiring 736 and the power supply wiring 756 are respectively short-circuited on the substrate 101, and the first circuit block 730 and the second circuit block 750 receive 12 V as the common reference potential VD and 12 V as the common reference potential VD. The 0V supply of VS works with 12V.

In this embodiment, although it is necessary to input a 12V signal to the first circuit block 730 , an IC capable of outputting a high voltage amplitude of 12V is expensive. Therefore, the signal from an external circuit such as an external IC is made to have an amplitude of 3V, and the signal is boosted from 3V to 12V by the interface level shift circuit (IFL/S) 751, and the driving capability is further improved by the second buffer circuit 752.

By making: the first circuit block 730 and the second circuit block 750 are driven by 12V; the reference potential VD on the high potential side is shared by 12V in the first circuit block 730 and the second circuit block 750; the reference potential on the low potential side The potential VS is common to 0 V in the first circuit block 730 and the second circuit block 750 ; a common power supply wiring can be formed.

In addition, the power supply wiring is connected to the power supply nodes of the circuit elements constituting each circuit, but in the figure, the connection to the circuit elements is omitted for convenience.

Here, the line width of the power supply wiring of the first circuit block 730 and the second circuit block 750 will be described.

Since the first circuit block 730 includes a clock control circuit (CCC) 733 and a first buffer circuit 737, it is similar to the circuit block in which the first circuit block 330 and the second circuit block 350 are combined in the first embodiment. Therefore, the minimum value of the line width of the power supply wiring of the first circuit block 730 is proportional to the product of the third power of the diagonal size of the screen and the coefficient, and the product of the square of the diagonal size of the screen and the coefficient as shown in Equation 10. and.

The minimum value of the line width of the power wiring of the first circuit block 730

∝(screen diagonal size^3)×factor+(screen diagonal size^2)×factor

.........(Formula 10)

Furthermore, unlike the level shift circuit (L/S) 351 of the first embodiment, in the interface level shift circuit (IF L/S) 751 of this embodiment, a constant leakage current, that is, a constant leakage current flows. . This is because the level shift circuit (L/S) 351 of the first embodiment boosts the signal from 8V to 12V by a factor of 1.5, whereas the interface level shift circuit (IF L/S) of the present embodiment The /S) 751 needs to step up the signal by four times from 3V to 12V, and its circuit configuration is different from that of the level shift circuit (L/S) 351 of the first embodiment. The above-mentioned constant leakage current is determined by the configuration of the interface level shift circuit (IF L/S) 751, so it depends on the number of signals to be boosted, that is, the number of interface level shift circuits (IF L/S) 751 Determined, does not depend on the diagonal size of the screen and is constant. In addition, there is current consumed when the level of the input signal is switched. Therefore, the current consumption of the interface level shift circuit (IFL/S) 751 is proportional to the sum of the product of the driving frequency and the coefficient of the scanning line 201 and the constant leakage current as shown in Equation 11.

Current consumption of interface level shift circuit (IF L/S) 751

∝ coefficient × driving frequency of scanning line 201 + constant leakage current... (Formula 11)

The consumption current of the second buffer circuit 752 is proportional to the product of the capacitance of the signal wiring to be driven and the driving frequency of the scanning line 201 as shown in Expression 12.

Consumption current of the second buffer circuit 752

∝Capacitance of the signal wiring to be driven × driving frequency of the scanning line 201

.........(Formula 12)

As long as the resolution is constant, the number of scanning lines 201 , the capacitance of the signal wiring for driving, and the driving frequency of the scanning lines 201 are proportional to the screen diagonal size of the display area 310 .

On the other hand, the current consumption of the second circuit block 750 is the sum of the current consumption of the second buffer circuit 752 and the current consumption of the interface level shift circuit (IF L/S) 751. In the above case, the current consumption of the second circuit block 750 is the product of the square of the diagonal size of the screen and the coefficient, the product of the diagonal size of the screen and the coefficient, and the product of the constant leakage current and the coefficient as shown in Equation 13. and.

Current consumption of the second circuit block 750

= Current consumption of the second buffer circuit 752

+ Consumption current of the interface level shift circuit (IF L/S) 751

∝(screen diagonal size^2)×factor+screen diagonal size×factor

    +Constant leakage current×coefficient...................(Formula 13)

Since the length of the power wiring of the second circuit block 750 is substantially constant regardless of the diagonal size of the screen, the minimum value of the line width of the power wiring of the second circuit block 750 is proportional to the current consumption of the second circuit block 750 . That is, the minimum value of the line width of the power supply wiring of the second circuit block 750 is proportional to the product of the square of the diagonal size of the screen and the coefficient, the product of the diagonal size of the screen and the coefficient, and the constant leakage current and The sum of the products of the coefficients.

The minimum value of the line width of the power wiring of the second circuit block 750

∝ Current consumption of the second circuit block 750 × screen size

∝(screen diagonal size^2)×factor+screen diagonal size×factor

    +Constant leakage current×coefficient...................(Formula 14)

Comparing Equation 13 and Equation 14, generally speaking, the term of the constant leakage current in Equation 14 is relatively large (several μA to tens of μA/pc), so when the screen size is smaller than or equal to a certain value, the power supply of the second circuit block 750 The minimum value of the line width of the wiring becomes larger. For example, when the diagonal size of the screen is 4 inches, the resolution of the display screen is VGA, the resolution is 200ppi, the aspect ratio is 4:3, and the frame frequency is 60Hz, as the logic circuit block of the first circuit block 730 The line width of the power supply wiring is 100 μm, and the line width of the power supply wiring of the external interface circuit block as the second circuit block 750 is 300 μm. However, the difference becomes smaller as the screen diagonal size becomes larger, and the line width of the power supply wiring of the logic circuit block and the line width of the power supply wiring of the external interface circuit block are reversed when the screen diagonal size is about 12 inches.

Based on the above results, in the present embodiment, the wiring width of the power supply wiring 735 and the power supply wiring 736 is 100 μm, and the wiring width of the power supply wiring 755 and 756 is 300 μm.

In this way, since the current consumption differs between the first circuit block 730 and the second circuit block 750 , it is possible to set appropriate line widths of the power supply lines. That is, it is possible to keep the voltage drop in the power supply wiring within a certain range, prevent the disconnection of the power supply wiring due to migration, etc., and by making the line width of the power supply wiring to the necessary minimum, it is possible to suppress the driving circuit of the liquid crystal display device. increase in circuit area. Thereby, the frame of the liquid crystal display device can be reduced in size, and the cost can be reduced.

In this embodiment, two power supply wirings are used for the unit shift circuit (S/R) 731, the clock control circuit (CCC) 733, the clock generation circuit (CGC) 734, the first buffer circuit 737, and the NAND circuit 738. Supply 2 reference potentials. However, like the first embodiment, the first circuit block 730 can be further divided into a circuit block 730a including a first buffer circuit 737, and a circuit block 730a including a unit shift circuit (S/R) 731 and a clock control circuit ( CCC) 733, a clock generation circuit (CGC) 734, and a circuit block 730b of a NAND circuit 738, two circuit blocks. That is, the scanning line driving circuit 701 is divided into three circuit blocks of a circuit block 730a, a circuit block 730b, and a circuit block 750; the power supply wirings 735 and 736 can also be divided into two as 739a, 739b, 739c, and 739d. The line width of the power supply wiring considers the current consumption in each power supply wiring, so it is possible to independently set the line width of the common power supply wiring suitable for the circuit block 730a, the circuit block 730b, and the second circuit block 750, so as to prevent the loss due to migration. Disconnection of the power supply wiring caused by etc., and make the line width of the power supply wiring to the necessary minimum. Accordingly, it is possible to further suppress an increase in the circuit area of the drive circuit of the liquid crystal optical device. Thereby, the frame of the liquid crystal display device can be reduced in size, and the cost can be reduced.

Furthermore, this embodiment can also be combined with the first embodiment. That is, it is also possible to input a 3V signal from an external circuit such as an external IC, and use the interface level shift circuit (IF L/S) 751 to boost the signal from 3V to 8V; and use 8V to drive the unit shift circuit (S/R ) 731, etc., and further use a level shift circuit (L/S) to boost the signal from 8V to 12V and then output the output signal to the scanning line 201. That is, the scanning line driving circuit 701 can be divided into a first circuit block 730, a circuit block 750a including an interface level shift circuit (IF L/S) 751 for boosting a signal from 3V to 8V, and a circuit block 750a for boosting a signal from 8V. 3 circuit blocks of circuit block 750b to 12V. The line width of the power supply wiring considers the current consumption in each power supply wiring, so by independently setting the line width of the common power supply wiring suitable for the first circuit block, the circuit block 750a, and the circuit block 750b, it is possible to prevent problems caused by migration and the like. Make the line width of the power wiring to the minimum necessary. Accordingly, it is possible to further suppress an increase in the circuit area of the drive circuit of the liquid crystal optical device. As a result, since the frame of the liquid crystal display device can be reduced, and because the step-up ratio of the level shift circuit (IF L/S and L/S) can be reduced, high-performance transistors are not required, so the cost can be reduced .

For example, when the diagonal size of the screen is 4 inches, the resolution of the display screen is VGA, the definition is 200ppi, the aspect ratio is 4:3, and the frame frequency is 60Hz, the line width of the power wiring of the first circuit block 730 30 μm, the line width of the power supply wiring of the circuit block 750 a is 50 μm, and the line width of the power supply wiring of the circuit block 750 b is 300 μm.

3. The third embodiment

FIG. 6 is a circuit diagram of a data line driving circuit 302 according to a third embodiment of the present invention. The data line driving circuit 302 includes a first circuit block 830, a second circuit block 850, and a power supply wiring for supplying a plurality of reference potentials.

The first circuit block 830 is equipped with a clock control circuit (CCC) 833, a clock generation circuit (CGC) 834, a unit shift circuit (S/R) 831, a NAND circuit 837, an inverter circuit 838, and a bidirectional transmission circuit 832. logic circuit block.

A unit shift circuit (S/R) 831 , a clock control circuit (CCC) 833 , a clock generation circuit (CGC) 834 , and a bidirectional transfer circuit 832 as unit circuits are the same as those in the first embodiment.

The second circuit block 850 is written by including: a LAT circuit 852 that holds a digital image signal at the timing transmitted from the first circuit block 830, and converts the digital signal transmitted from the LAT circuit 852 into an analog signal of a predetermined potential. The external interface circuit block of the DA conversion circuit 851 input to the data line 202. The first circuit block 830 and the second circuit block 850 are driven by, for example, 8V.

The power supply lines 835 and 855 supply the reference potential VS to the data line drive circuit 302 ; the power supply lines 836 and 853 supply the reference potential VD to the data line drive circuit 302 . For example, the reference potential VS as the ground potential is set to 0V, and the reference potential VD is set to 8V.

The first circuit block 830 and the second circuit block 850 are supplied with 8V as a common reference potential VD and 0V as a reference potential VS, and operate at 8V.

In this embodiment, by making: the first circuit block 830 and the second circuit block 850 are driven by 8V; the reference potential VD on the high potential side is shared by 8V in the first circuit block 830 and the second circuit block 850; The reference potential VS on the low potential side is common to 0V in the first circuit block 830 and the second circuit block 850, and a common power supply wiring can be formed.

In addition, the power supply wiring is connected to the power supply nodes of the circuit elements constituting each circuit, but in the figure, the connection to the circuit elements is omitted for convenience.

Here, the line width of the power supply wiring of the first circuit block 830 and the second circuit block 850 will be described.

The first circuit block 830 includes a clock control circuit (CCC) 833 similarly to the first circuit block 330 of the first embodiment. Therefore, the current consumption of the first circuit block 830 is proportional to the diagonal size of the screen, similarly to the first circuit block 330 of the first embodiment. That is, the minimum value of the line width of the power supply wiring of the first circuit block 830 is proportional to the square of the diagonal size of the screen as in Equation 15.

The minimum value of the line width of the power wiring of the first circuit block 830

∝Screen Diagonal Size^2................................( Formula 15)

On the other hand, a general DA conversion circuit has larger current consumption than a general logic circuit such as a clock generation circuit (CGC) 834 , for example, because it includes ladder resistors and amplifiers. The current consumption of the DA conversion circuit 851 alone is proportional to the sum of the product of the capacitance of the data line 202 and the driving frequency of the data line 202 and the constant leakage current as shown in Equation 16.

DA conversion circuit 851 single consumption current

∝ Electrostatic capacitance of the data line 202 × driving frequency of the data line 202

+Constant Leakage Current...................................(Equation 16)

Furthermore, the consumption current of the LAT circuit 852 alone is proportional to the driving frequency of the data line 202 as shown in Equation 17.

Consumption current of LAT circuit 852 alone∝Driving frequency of data line 202... (Formula 17)

As long as the resolution is constant, the capacitance of the data line 202 and the driving frequency of the data line 202 are proportional to the diagonal size of the display area 310 . Moreover, the numbers of DA conversion circuits 851 and LAT circuits 852 in the data line driving circuit 302 are respectively proportional to the diagonal size of the screen of the display area 310 . Accordingly, the current consumption of the DA conversion circuit 851 as a whole is proportional to the cube of the screen diagonal size and the sum of the product of the screen diagonal size, the coefficient, and the constant leakage current, as shown in Equation 18.

The current consumption of the DA conversion circuit 851 as a whole

∝The consumption current of DA conversion circuit 851 unit × the number of DA conversion circuits 851

∝Screen diagonal size^3+screen diagonal size×coefficient×constant leakage current

................................................... ......(Formula 18)

Furthermore, the current consumption of the LAT circuit 852 as a whole is proportional to the square of the diagonal size of the screen as shown in Equation 19.

Current consumption of the LAT circuit 852 as a whole

∝LAT circuit 852 single consumption current × LAT circuit 852 number

∝Screen Diagonal Size^2................................( Formula 19)

The consumption current of the second circuit block 850 is the sum of the consumption current of the DA conversion circuit 851 and the consumption current of the LAT circuit 852 . In the above case, the current consumption of the second circuit block 850 is the product of the third power of the diagonal size of the screen and the coefficient, the product of the square of the diagonal size of the screen and the coefficient, and the diagonal size of the screen as shown in Equation 20. The sum of the product of the AND coefficient and the constant leakage current.

Current consumption of the second circuit block 850

＝The overall consumption current of DA conversion circuit 851

The overall consumption current of +LAT circuit 852

∝(screen diagonal size^3)×factor+(screen diagonal size^2)×factor

  + Screen diagonal size × coefficient × constant leakage current......(Formula 20)

The length of the power wiring of the second circuit block 850 is roughly proportional to the diagonal size of the screen. Therefore, the minimum value of the line width of the power supply wiring of the second circuit block 850 is proportional to the product of the current consumption of the second circuit block 850 and the diagonal size of the screen. That is, the minimum value of the line width of the power supply wiring of the second circuit block 850 is proportional to the product of the fourth power of the diagonal size of the screen and the coefficient, and the product of the third power of the diagonal size of the screen and the coefficient as shown in Equation 21. , and the sum of the square of the diagonal size of the screen and the product of the coefficient and the constant leakage current.

The minimum value of the line width of the power wiring of the second circuit block 850

∝Current consumption of the second circuit block 850×diagonal size of the screen

∝(screen diagonal size^4)×factor+(screen diagonal size^3)×factor

  + (screen diagonal size^2) × coefficient × constant leakage current... (Formula 21)

Referring to Equation 21 and Equation 15, it can be seen that, in general, the current consumption of the second circuit block 850 is considerably larger than the current consumption of the first circuit block 830 . Here, since the line width of the power supply wiring is set according to the current consumption of each power supply wiring, the line width of the common power supply wiring suitable for the first circuit block 830 and the second circuit block 850 can be independently set. Accordingly, it is possible to prevent disconnection of the power supply wiring due to migration or the like, and to suppress an increase in the circuit area of the driving circuit of the electro-optical device by minimizing the line width of the power supply wiring. Thereby, the frame of the liquid crystal display device can be reduced in size, and the cost can be reduced.

For example, when the diagonal size of the screen is 4 inches, the resolution of the display screen is VGA, the resolution is 200ppi, the aspect ratio is 4:3, and the frame frequency is 60Hz, as the logic circuit block of the first circuit block 830 The line width of the power supply wiring is 30 μm, and the line width of the power supply wiring of the external interface circuit block as the second circuit block 850 is 100 μm. That is, the power supply wiring 835 and the power supply wiring 836 have a wiring width of 30 μm, and the power supply wiring 853 and the power supply wiring 855 have a wiring width of 100 m.

4. Fourth Embodiment

Next, an electronic device to which the driving circuit of the electro-optical device according to the above-mentioned embodiment is applied will be described. 7 is a perspective configuration view (partial sectional view) of a liquid crystal display device incorporating the driving circuit of the electro-optic device according to the above-mentioned embodiment. The counter substrate 901 on which a common electrode is formed by forming a film of ITO on a color filter substrate is bonded to the active matrix substrate 101 through a sealing material 920 , and the liquid crystal element 910 is sealed therein. Although not shown in the figure, on the surface of both the active matrix substrate 101 and the counter substrate 901 that are in contact with the liquid crystal element 910, an alignment material made of polyimide or the like is coated, and the alignment material is applied in directions perpendicular to each other. Friction treatment. In addition, a conductive material is disposed on the opposite conductive portion 304 on the active matrix substrate 101 , and is short-circuited with the common electrode of the opposite substrate 901 .

The active matrix substrate 101 is connected to one or more driving ICs 940 on the driving circuit substrate 935 through the flexible substrate 930 mounted on the active matrix substrate 101 to supply required electrical signals and potentials.

Furthermore, the upper deflection plate 951 is arranged outside the counter substrate 901, and the lower deflection plate 952 is arranged outside the active matrix substrate 101, and the deflection directions are perpendicular to each other (crossed Nicol shape). Furthermore, a backlight unit 960 is disposed outside the lower deflector 952 . The backlight unit 960 may be a unit in which a light guide plate and a diffusion plate are mounted on a cold cathode tube, or may be a unit in which light is emitted by inorganic or organic LED elements. Although it is not shown in the figure, according to further needs, it is possible to cover the periphery with a casing or install a protective glass or acrylic plate on the upper part of the upper deflection plate, or paste an optical compensation film to improve the viewing angle.

5. Modified examples and improved examples

In addition, this invention is not limited to the said embodiment, The deformation|transformation, improvement, etc. within the range which can achieve the object of this invention are included in this invention. For example, the present invention may combine the characteristic parts of the above-described embodiments.

For example, in the foregoing embodiments, the electro-optical device has been described as a device including a drive circuit, but the present invention is not limited thereto. For example, instead of forming part or all of the driving circuit on the element substrate as an electro-optic device, for example, it is also possible to use the TAB (Tape Automated Bonding) technology to install the driving circuit on the film, by setting An anisotropic conductive film at a predetermined position on the component substrate is electrically and mechanically connected; it can also be connected to an IC chip formed with a drive circuit using COG (Chip On Glass) technology. There is a configuration of a predetermined position of an element substrate of an electro-optical device.

In addition, in the present embodiment, the allowable drop voltage range of the power supply of the entire circuit block is fixed, but it may be changed for each circuit block according to the suitability of the circuit block. For example, in the digital circuit block, the allowable range is increased so as not to malfunction, and in the analog circuit block, the allowable range is narrowed so that the display quality is not affected. In addition, in the present embodiment, the wiring width is obtained from the drop voltage of the power supply, but the wiring width may be determined from the current density of the wiring according to requirements such as a manufacturing process.

In addition, in the present embodiment, the power supply wiring in the same circuit block has the same wiring width in the high-potential power supply wiring and the low-potential power supply wiring, but depending on factors such as differences in characteristics of n-type transistors and p-type transistors, Instead, the high-potential power supply wiring and the low-potential power supply wiring have different wiring widths.

6. Electronic equipment

Next, an electronic device to which the electro-optical device 100 of the above-mentioned embodiments and application examples is applied will be described. FIG. 8 shows the configuration of a mobile personal computer to which the electro-optical device 100 is applied. A personal computer 2000 includes an electro-optical device 100 as a display unit and a main body 2010 . On the main body 2010, a power switch 2001 and a keyboard 2002 are provided. The electro-optic device 100 has sufficient reliability because the power wiring width is optimized, and the frame is small, so that the personal computer 2000 can also be miniaturized.

FIG. 9 shows the configuration of a mobile phone to which the electro-optical device 100 is applied. A mobile phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002, and an electro-optical device 100 as a display unit. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 can be scrolled. FIG. 10 shows the configuration of a portable information terminal (PDA: Personal Digital Assistants) to which the electro-optical device 100 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and an electro-optical device 100 as a display unit. When the power switch 4002 is operated, various information such as address book and schedule are displayed on the electro-optical device 100 .

In addition, as electronic equipment to which the electro-optical device 100 is applied, in addition to those shown in FIGS. Devices, pagers, electronic notebooks, calculators, word processors, workstations, TV phones, POS terminals, devices with touch panels, etc. Furthermore, the above-mentioned electro-optical device 100 can be applied as a display unit of these various electronic devices.

Claims (11)

1. semiconductor circuit, the power-supply wiring that it has the 1st circuit block, the 2nd circuit block and supplies with a plurality of reference potentials is characterized in that:

Above-mentioned the 1st circuit block and above-mentioned the 2nd circuit block all are connected to as in the common source wiring one of above-mentioned power-supply wiring, that supply with shared reference potential; The live width of the above-mentioned common source wiring in above-mentioned the 1st circuit block is than the line width of the above-mentioned common source wiring in above-mentioned the 2nd circuit block.

2. the driving circuit of an electro-optical device, it has: many sweep traces and many data lines, be connected to the switch element of above-mentioned sweep trace and above-mentioned data line and the pixel electrode that disposes corresponding to above-mentioned switch element, it is characterized in that:

Possess: the 1st circuit block, the 2nd circuit block and supply with the power-supply wiring of a plurality of reference potentials;

Above-mentioned the 1st circuit block and above-mentioned the 2nd circuit block all are connected to as in the common source wiring one of above-mentioned power-supply wiring, that supply with shared reference potential; The live width of the above-mentioned common source wiring in above-mentioned the 1st circuit block is than the line width of the above-mentioned common source wiring in above-mentioned the 2nd circuit block.

3. according to the driving circuit of the described electro-optical device of claim 2, it is characterized in that:

Above-mentioned the 1st circuit block possesses: by being synchronized with the shift register that unit circuit constituted that clock signal ground transmits the signal that outputs to above-mentioned sweep trace, above-mentioned data line;

Above-mentioned the 2nd circuit block possesses the buffer circuit that drives above-mentioned sweep trace, above-mentioned data line.

4. according to the driving circuit of the described electro-optical device of claim 2, it is characterized in that:

Above-mentioned the 1st circuit block possesses: by being synchronized with the shift register that unit circuit constituted that clock signal ground transmits the signal that outputs to above-mentioned sweep trace, above-mentioned data line;

Also possess: according to judging that whether the above-mentioned data that transmit become the result of significant level, control the clock control circuit of above-mentioned clock signal to the supply of above-mentioned unit circuit.

5. according to the driving circuit of the described electro-optical device of claim 2, it is characterized in that:

Above-mentioned the 1st circuit block possesses: by being synchronized with the shift register that unit circuit constituted that clock signal ground transmits the signal that outputs to above-mentioned sweep trace, above-mentioned data line;

Above-mentioned the 2nd circuit block possesses: will be used to drive the level shift circuit that the signal of importing from external circuit of the driving circuit of above-mentioned electro-optical device boosts.

6. according to the driving circuit of the described electro-optical device of claim 2, it is characterized in that:

Above-mentioned the 1st circuit block possesses: by being synchronized with the shift register that unit circuit constituted that clock signal ground transmits the signal that outputs to above-mentioned sweep trace, above-mentioned data line;

Above-mentioned the 2nd circuit block possesses: be used for the signal that will be used to drive the driving circuit of above-mentioned electro-optical device and import from external circuit, with the signal in the predetermined scope rise, fall time is to the buffer circuit of above-mentioned the 1st circuit block output.

7. according to the driving circuit of the described electro-optical device of claim 2, it is characterized in that:

Above-mentioned the 1st circuit block possesses: by being synchronized with the shift register that unit circuit constituted that clock signal ground transmits the signal that outputs to above-mentioned sweep trace, above-mentioned data line;

Above-mentioned the 2nd circuit block possesses: the DA translation circuit that is used for driving with predetermined current potential above-mentioned data line.

8. according to the driving circuit of any one the described electro-optical device in the claim 2～7, it is characterized in that:

As the 1st driving voltage of the difference of the maximal value of the above-mentioned a plurality of reference potentials that supply to above-mentioned the 1st circuit block and minimum value, inequality with the 2nd driving voltage as the difference of the maximal value of the above-mentioned a plurality of reference potentials that supply to above-mentioned the 2nd circuit block and minimum value.

9. electro-optical device is characterized in that:

On same substrate, be formed with: the driving circuit described in the claim 2～8, many sweep traces and many data lines, the pixel electrode that is connected to the switch element of above-mentioned sweep trace and above-mentioned data line and is connected to above-mentioned switch element.

10. according to the described electro-optical device of claim 9, it is characterized in that:

Supply to the current potential of above-mentioned common source wiring, inequality with the earthing potential that supplies to above-mentioned electro-optical device.

11. an electronic equipment is characterized in that:

Possess claim 9 or 10 described electro-optical devices.

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