CN1828887A - Chip-type micro connector and packaging method thereof - Google Patents
Chip-type micro connector and packaging method thereof Download PDFInfo
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- CN1828887A CN1828887A CNA2005100517555A CN200510051755A CN1828887A CN 1828887 A CN1828887 A CN 1828887A CN A2005100517555 A CNA2005100517555 A CN A2005100517555A CN 200510051755 A CN200510051755 A CN 200510051755A CN 1828887 A CN1828887 A CN 1828887A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims description 58
- 239000011241 protective layer Substances 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000012856 packing Methods 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
一种芯片型微型连接器，包括一封装基板、一微型连接器、多个芯片与一封盖层。该微型连接器包括一连接基板、多组连接导线布设于该连接基板中，以及多组连接垫分别与各该组连接导线电连接，并暴露于该连接基板的表面。这些芯片分别与该微型连接器电连接，并透过该微型连接器的各该组连接垫与各该组连接导线电连接以互相沟通。
A chip-type micro connector includes a packaging substrate, a micro connector, a plurality of chips and a cover layer. The micro connector includes a connection substrate, a plurality of groups of connection wires arranged in the connection substrate, and a plurality of groups of connection pads electrically connected to each group of connection wires and exposed on the surface of the connection substrate. The chips are electrically connected to the micro connector respectively, and are electrically connected to each group of connection wires through each group of connection pads of the micro connector to communicate with each other.
Description
Technical field
The present invention relates to a kind of chip type minitype connector and its method for packing, particularly relate to a kind of chip type minitype connector and its method for packing that utilizes micro connector as the communication bridge of a plurality of chips.
Background technology
The development trend of just present electronic product, the multifunction of electronic product has become main direction with microminiaturization, and its multi-functional performance often needs can reach in conjunction with the running of a plurality of chips, yet the connection between each chip certainly will be caused the increase of the volume of electronic product if seeing through the circuit office of joining of printed circuit board (PCB) reaches.Therefore present trend is to utilize the routing mode to be connected the interconnected chip of a plurality of needs, and said chip directly is packaged into an encapsulating structure, uses the double requirements that reaches multi-functional with microminiaturized.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of an existing encapsulating structure 10.As shown in Figure 1, existing encapsulating structure 10 comprises a base plate for packaging 12, and two chips 14 and 16 are attached at the surface of base plate for packaging 12 respectively.Chip 14 comprises a plurality of connection gasket 14A and 14B, and chip 16 comprises a plurality of connection gasket 16A and 16B, its chips 14 and 16 sees through connection gasket 14A and 16A and utilizes lead 18 to interconnect, and chip 14 and 16 sees through connection gasket 14B and 16B again respectively, and utilizes lead 20 to be connected the connection gasket 24 of base plate for packaging 12 with 22 respectively.
Generally speaking, encapsulating structure 10 also comprises a capping layer (figure does not show) again, be coated on base plate for packaging 12 and chip 14 and 16, and a plurality of solder projections (figure does not show), or the pin of different size (figure does not show), in order to encapsulating structure 10 is installed in a printed circuit board (PCB) (figure do not show), uses with other active or passive component and form a complete electronic system.
Because chip 14 and 16 utilizes lead 18 to interconnect, if under the excessive situation of the distance of chip 14 and 16, cause lead 18 to produce the problem excessive that get loose easily with resistance value, also can cause simultaneously the increase of encapsulating structure area, therefore under the requirement of microminiaturization, general wish and then can cause the routing degree of difficulty to increase apart from dwindling between chip 14 and 16 that the while may be caused problems such as chip 14 and 16 s' electromagnetic interference (EMI) and heat radiation.In addition, for the encapsulating structure that comprises the more heterogeneous chip that connects, the existing practice will make the making of the lead 18 between each chip and configuration difficult more.
In view of this, the applicant proposes a kind of chip type minitype connector and its method for packing of improvement at the shortcoming of existing encapsulating structure, reduces the degree of difficulty and and then the rate of finished products of lifting packaging technology of routing by this.
Summary of the invention
Main purpose of the present invention is in that a kind of chip type minitype connector and its method for packing are provided, to overcome the difficult problem that prior art can't overcome.
According to claim of the present invention, provide a kind of chip type minitype connector.Said chip type micro connector comprises that a base plate for packaging, a micro connector are arranged on this base plate for packaging, a plurality of chip and a capping layer are arranged on this micro connector and these chips, and with this micro connector and these Chip Packaging on this base plate for packaging.This micro connector comprise one connect substrate, many groups connect lead and are laid in this connections substrate, and organize connection gasket more and be connected the lead electrical connection with this group respectively respectively, and be exposed to the surface of this connection substrate.These chips are electrically connected with this micro connector respectively, and see through respectively this group connection gasket of this micro connector and be connected the lead electrical connection to communicate with each other with this group respectively.
According to claim of the present invention, a kind of method that encapsulates a plurality of chips also is provided, include the following step.At first provide one to connect substrate.Then connect and form many groups on substrate and connect leads in this, and many groups and the connection gaskets that should many groups be connected the lead electrical connection.Subsequently a plurality of chips are electrically connected with this group connection gasket respectively respectively.Utilize a capping layer should connect substrate and these Chip Packaging on a base plate for packaging at last.
Because chip type minitype connector of the present invention utilizes the communication media of micro connector as a plurality of chips, therefore the resistance of the connection lead of micro connector inside can utilize the thickness of adjusting conductive layer to be adjusted with the live width that is connected lead, uses to make to have preferable electrical connection between each chip.In addition, the present invention utilizes the practice of micro connector also to reduce the degree of difficulty of routing, and has avoided problems such as prior art heat radiation and electromagnetic interference.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
Fig. 1 is the schematic diagram of an existing encapsulating structure.
Fig. 2 and Fig. 3 are the schematic diagram of one embodiment of the present invention chip type minitype connector.
Fig. 4 is the schematic appearance of another preferred embodiment chip type minitype connector of the present invention.
Fig. 5 to Figure 13 encapsulates the method schematic diagram of a plurality of chips for the present invention.
The simple symbol explanation
10 encapsulating structures, 12 base plate for packaging
14 chip 14A connection gaskets
14B connection gasket 16 chips
16A connection gasket 16B connection gasket
18 leads, 20 leads
22 leads, 24 connection gaskets
30 chip type minitype connectors, 32 micro connectors
32A connection gasket 32B connection gasket
32C connection gasket 34 first chips
34A connection gasket 36 second chips
36A connection gasket 38 base plate for packaging
38A connection gasket 40 capping layers
42 leads, 44 leads
46 leads, 48 printed circuit board (PCB)s
50 chip type minitype connectors, 52 base plate for packaging
54 micro connector 54A connection gaskets
54B connection gasket 54C connection gasket
54D connection gasket 56 first chips
56A connection gasket 58 second chips
58A connection gasket 60 the 3rd chip
60A connection gasket 62 four-core sheets
62A connection gasket 64 leads
66 leads, 68 leads
70 leads, 72 printed circuit board (PCB)s
100 connect substrate 102 silicon oxide layers
104 conductive layers 106 first connect lead
108 dielectric layers, 110 contact holes
112 conductive layers 114 second connect lead
116 protective layers, 118 connection gaskets
Embodiment
Please refer to Fig. 2 and Fig. 3, Fig. 2 and Fig. 3 are the schematic diagram of one embodiment of the present invention chip type minitype connector 30, and wherein Fig. 2 is the schematic appearance of chip type minitype connector 30, and Fig. 3 is the generalized section of chip type minitype connector 30.As Fig. 2 and shown in Figure 3, chip type minitype connector 30 of the present invention comprises a micro connector 32, one first chip 34 stick in the upper surface of micro connector 32, one second chip 36 lower surface that is arranged at micro connector 32, the below that a base plate for packaging 38 is arranged at second chip 36, and one capping layer 40 be positioned on first chip 34, micro connector 32, second chip 36 and the base plate for packaging 38, and first chip 34, micro connector 32 and second chip 36 are covered on the base plate for packaging 38.
The foregoing description is a rectilinear chip type minitype connector, and chip type minitype connector of the present invention also can be depicted as a horizontal chip type minitype connector as following embodiment.Please refer to Fig. 4, Fig. 4 is the schematic appearance of another preferred embodiment chip type minitype connector 50 of the present invention.As shown in Figure 4, chip type minitype connector 50 comprises a base plate for packaging 52, a micro connector 54, one first chip 56, one second chip 58, one the 3rd chip 60 and a four-core sheet 62, and micro connector 54, first chip 56, second chip 58, the 3rd chip 60 and four-core sheet 62 all are arranged at the surface of base plate for packaging 52.The inside of micro connector 54 comprises that many groups connect lead (figure does not show), and utilize a plurality of connection gasket 54A, 54B, 54C and 54D usefulness respectively as link, wherein connection gasket 54A is in order to connect first chip 56, connection gasket 54B is in order to connect second chip 58, connection gasket 54C is in order to connect the 3rd chip 60, and connection gasket 54D is then in order to connect four-core sheet 62.In addition, first chip 56 comprises a plurality of connection gasket 56A, and utilize lead 64 to be electrically connected with the connection gasket 54A of micro connector 54, second chip 58 comprises a plurality of connection gasket 58A, and utilizing lead 66 to be electrically connected with the connection gasket 54B of micro connector 54, the 3rd chip 60 comprises a plurality of connection gasket 60A, and utilizes lead 68 to be electrically connected with the connection gasket 54C of micro connector 54, and four-core sheet 62 comprises a plurality of connection gasket 62A, and utilizes lead 70 to be electrically connected with the connection gasket 54D of micro connector 54.The connection lead of micro connector 54 inside (figure do not show) is connected and need be designed with circuit between the four-core sheet 62 according to first chip 56, second chip 58, the 3rd chip 60, first chip 56, second chip 58, the 3rd chip 60 and four-core sheet 62 can be linked up each other through micro connector 54 by this, to bring into play its function.On the other hand, micro connector 54 is connected with base plate for packaging 52 through solder projection (figure does not show) in present embodiment, first chip 56, second chip 58, the 3rd chip 60 can be connected with base plate for packaging 52 with four-core sheet 62, and base plate for packaging 52 utilize welding or pin modes such as (figure do not show) to be installed on the printed circuit board (PCB) 72.By above-mentioned configuration, first chip 56, second chip 58, the 3rd chip 60 can see through micro connector 54 with four-core sheet 62 and do suitably to be connected, and further be connected on the printed circuit board (PCB) 72 through micro connector 54 simultaneously, constitute a complete electronic system with or passive component active with other.
The characteristics of chip type minitype connector of the present invention are for using the communication media of micro connector as a plurality of chips, design and layout as for the connection lead of micro connector inside can be adjusted according to the size of each chip, or comply with the needs that circuit connects between each chip and do different designs, for example adopt designs such as individual layer conductor structure or multi-layer conductor leads structure, if wherein connect lead multi-layer conductor leads structure, then between each group connection lead a screen can be set, for example a metal level is organized the interference that connects between lead to avoid each.In addition, the design of micro connector also can be produced the connection lead layout that is fit to many core assemblies sheet in advance at many core assemblies sheet, and the actual chip that encapsulates only need utilize routing or his mode of base to be connected with corresponding connection gasket, and each chip can see through corresponding connection lead and do correct communication.Moreover, being connected between each chip and the micro connector, and being connected between micro connector and the base plate for packaging etc., visual actual needs adopts routing, solder projection, or alternate manner is reached.
Please refer to Fig. 5 to Figure 13, Fig. 5 to Figure 13 encapsulates the method schematic diagram of a plurality of chips for the present invention.As shown in Figure 5, at first provide one to connect substrate 100, a silicon substrate for example, and form one silica layer 102 in the surface that connects substrate 100, as preventing layer (preventable layer) usefulness with stress-buffer layer (stress buffer layer).Then as Fig. 6 and shown in Figure 7, form a conductive layer 104 in the surface of silica 102, for example a metal level then carries out a lithography corrosion process, removes partially conductive layer 104 and connects lead 106 to form first.Wherein the thickness of the conductive layer 104 visual resistance value demand of live width that is connected lead 106 with first adjusts, and for obtaining bigger resistance value, the thickness of conductive layer 104 with greater than 0.5 micron preferred, first connects the live width of lead 106 then with preferred greater than 10 microns.
As Fig. 8, then form a dielectric layer 108, as the usefulness of insulating barrier in first surface that connects lead 106 and oxide layer 102.As shown in Figure 9, then carry out a lithography corrosion process, remove part dielectric layer 108 and expose first and connect lead 106 to form a plurality of contacts hole 110, to use.Carry out a cleaning subsequently again, to remove the oxide on the first connection lead, 106 surfaces that expose by contact hole 110.
As Figure 10 and shown in Figure 11, then form another conductive layer 112 in the surface of dielectric layer 108, and carry out a lithography corrosion process, connect lead 114 to form second, but wherein the thickness of conductive layer 112 be connected lead 114 with second live width also apparent resistance need adjust, and for obtaining bigger resistance value, the thickness of conductive layer 112 with greater than 0.5 micron preferred, second connects the live width of lead 114 then with preferred greater than 10 microns.
As shown in figure 12, then form a protective layer 116, for example a silicon nitride layer in the surface of conductive layer 112.As shown in figure 13, carry out a lithography corrosion process at last, remove partial protection layer 116, to form a plurality of connection gaskets 118.
So far, micro connector of the present invention promptly completes, and more a plurality of chips are electrically connected with each connection gasket respectively subsequently, and utilize a capping layer will connect substrate and Chip Packaging on a base plate for packaging, can form as Fig. 2 or chip type minitype connector shown in Figure 4.Wherein it should be noted that Fig. 5 to method shown in Figure 13 embodiment for the connection lead of making the pair of lamina structure, it is different and produce the micro connector of the connection lead that includes single layer structure or sandwich construction that in fact the present invention's method of encapsulating a plurality of chips can connect design according to the circuit of each chip.
Chip type minitype connector of the present invention utilizes the communication media of micro connector as a plurality of chips, its advantage is that the resistance of the connection lead of micro connector inside can utilize the thickness of adjusting conductive layer to be adjusted with the live width that is connected lead, uses to make to have preferable electrical connection between each chip.In addition,, utilize the practice of micro connector also to reduce the degree of difficulty of routing, and avoided problems such as prior art heat radiation and electromagnetic interference compared to prior art.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005100517555A CN1828887A (en) | 2005-03-01 | 2005-03-01 | Chip-type micro connector and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2005100517555A CN1828887A (en) | 2005-03-01 | 2005-03-01 | Chip-type micro connector and packaging method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1828887A true CN1828887A (en) | 2006-09-06 |
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ID=36947153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005100517555A Pending CN1828887A (en) | 2005-03-01 | 2005-03-01 | Chip-type micro connector and packaging method thereof |
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| Country | Link |
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| CN (1) | CN1828887A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431034B (en) * | 2008-11-27 | 2010-10-06 | 江苏康众数字医疗设备有限公司 | Method for multi-chip planar packaging |
| CN101388370B (en) * | 2007-09-14 | 2013-09-11 | 英飞凌科技股份有限公司 | Semiconductor device |
-
2005
- 2005-03-01 CN CNA2005100517555A patent/CN1828887A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388370B (en) * | 2007-09-14 | 2013-09-11 | 英飞凌科技股份有限公司 | Semiconductor device |
| CN101431034B (en) * | 2008-11-27 | 2010-10-06 | 江苏康众数字医疗设备有限公司 | Method for multi-chip planar packaging |
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