CN1812264A - Output circuit for slew rate control - Google Patents

Abstract

The invention relates to a slew rate controlled output circuit, which comprises an input node, an output node, a first output transistor, a second output transistor, a first slew rate control circuit and a second slew rate control circuit. The first output transistor and the second output transistor are coupled in series. The first slew rate control circuit is coupled between the first output transistor and the first power supply terminal. The second slew rate control circuit is coupled between the second output transistor and the second power supply terminal. The input node is coupled to the gate of the first output transistor and the gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second output transistor.

Description

Output circuit for slew rate control

technical field

The present invention relates to an output circuit, in particular to an output circuit controlled by slew rate.

Background technique

An electronic device such as a personal computer usually includes a plurality of integrated circuits (ICs) or semiconductor chips that communicate with each other through, for example, a common bus. Each IC chip has an output circuit (also known as an output buffer) for driving signals from the IC chip to the bus, or driving signals from the IC chip directly to one or more other IC chips. The speed at which the output circuit switches a signal (for example, from logic low to logic high) is called the slew rate of the output circuit, generally measured in volts per unit of time. In order to ensure circuit speed compatibility between the IC chip and the associated busbars, the output circuits used on the IC chip must generally have a specific range of slew rates. If the output circuit does not meet the slew rate specification, its host IC chip may not be able to operate at a specific frequency and may not be compatible with other chips or devices. The degree of symmetry between ascending and descending slew rates may also affect this compatibility. Furthermore, if the slew rate is too high, the output signal may introduce noise that would otherwise not be present. Therefore, it is important for the output driver to maintain a specific rise and fall slew rate.

The slew rate of the output circuit will vary with variations in the manufacturing process, operating voltage, operating temperature, and external load capacitance at the output. As the physical size of IC dies becomes smaller, it becomes more difficult to control operating characteristics such as the slew rate of transistors in the die. Process variations in semiconductor wafer fabrication may cause transistors of the same design to have different characteristics. For example, the amount of current supplied by a transistor affects its slew rate, and this amount of current is related to many factors, including transistor size, gate-source voltage, and manufacturing-related parameters. Although transistor size and gate-source voltage can be well controlled, manufacturing process characteristics typically vary from transistor to transistor due to imperfections in existing doping techniques and other manufacturing techniques. Consequently, output circuits with the same design and the same specific operating characteristics may not operate as expected at different speeds, and may have out-of-spec slew rates.

In addition, the operating characteristics of transistors also change with temperature. When the IC die is hot, the transistors work more slowly, and conversely, when the IC die is colder, the transistors work faster. Therefore, normal output circuits do not expect the slew rate to change with temperature. Variations in the operating temperature of the output drivers may cause the slew rates of these output drivers to deviate from an otherwise specified slew rate.

Therefore, there is a need for an improved output circuit that maintains a specific and more symmetrical slew rate regardless of process, voltage, and temperature (PVT) variations.

It can be seen that the above-mentioned existing output circuit still has many defects, and needs to be further improved urgently. In order to solve the problems existing in the output circuit, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above problems. This is obviously a problem. Issues that relevant industry players are eager to solve.

In view of the defects in the above-mentioned existing output circuits, the inventor actively researches and innovates based on his rich practical experience and professional knowledge in the design and manufacture of such products, in order to create a new output circuit with slew rate control, which can Improve the general existing output circuit to make it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.

Contents of the invention

The purpose of the present invention is to overcome the defects of the existing output circuit and provide a new output circuit with slew rate control. And symmetrical slew rate (slew rate), which is more suitable for practical use, and has industrial utilization value.

Another object of the present invention is to provide an output circuit with slew rate control. The technical problem to be solved is that the slew rate of the output voltage on the output node will not vary with the process, voltage and temperature variations. Obvious changes, which are more suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to an output circuit proposed by the present invention, it includes: an input node; an output node; a first output transistor and a second output transistor coupled in series; a first slew rate (slew rate) control circuit, coupled to between the first output transistor and a first power supply terminal, configured to provide variable resistance; and a second slew rate control circuit coupled between the second output transistor and a second power supply terminal , is configured to provide variable resistance; wherein, the input node is coupled to the gate of the first output transistor and the gate of the second output transistor, and the output node is coupled to the first output transistor and the gate of the second output transistor A common node for the second output transistor.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The aforementioned output circuit further includes: an output resistor coupled to the output node and a common node of the first output transistor and the second output transistor.

The aforementioned output circuit further includes: a first capacitor coupled to the second power supply terminal and the common node of the first output transistor and the first slew rate control circuit; and a second capacitor coupled to the first Two power terminals and a common node of the second output transistor and the second slew rate control circuit.

The aforementioned output circuit, wherein the first slew rate control circuit includes a first variable resistor, wherein the resistance of the first variable resistor responds to a first bias signal from a first bias circuit; And the second slew rate control circuit includes a second variable resistor, wherein the resistance of the second variable resistor responds to a second bias signal from a second bias circuit.

The aforementioned output circuit, wherein the first variable resistor includes a first resistor and a first control transistor coupled in parallel, wherein the gate of the first control transistor is coupled to a first bias circuit of the first a bias signal node; and

The second variable resistor includes a second resistor and a second control transistor coupled in parallel, wherein the gate of the second control transistor is coupled to a second bias signal node of the second bias circuit.

In the aforementioned output circuit, both the first output transistor and the first control transistor are PMOS transistors, and the second output transistor and the second control transistor are both NMOS transistors.

The aforementioned output circuit, wherein the first bias circuit includes a first bias transistor and a second bias transistor coupled in series and across between the first power supply terminal and the second power supply terminal, the The first bias signal node is coupled to the gate of the first bias transistor, the gate of the second bias transistor, and the common node of the first bias transistor and the second bias transistor;

The second bias circuit includes a third bias transistor and a fourth bias transistor coupled in series and connected between the first power supply terminal and the second power supply terminal, the second bias voltage signal node is coupled to to the gate of the third bias transistor, the gate of the fourth bias transistor, and the common node of the third bias transistor and the fourth bias transistor; and

The electrical characteristics of the first bias transistor and the electrical characteristics of the third bias transistor are substantially the same as the electrical characteristics of the first output transistor, and the electrical characteristics of the second bias transistor and the fourth bias transistor The electrical characteristics of are substantially the same as the electrical characteristics of the second output transistor.

The aforementioned output circuit, wherein the first output transistor, the first control transistor, the first bias transistor and the third bias transistor are all PMOS transistors, and the second output transistor, the second control transistor , the second bias transistor and the fourth bias transistor are all NMOS transistors.

The aforementioned output circuit, wherein said first bias circuit includes a first bias variable resistor, a first bias transistor, a first bias operational amplifier and a rising slew rate control resistor; the first bias The first terminal of the voltage variable resistor is coupled to the first power supply terminal, the second terminal of the first bias variable resistor is coupled to the first terminal of the first bias transistor, and the first bias transistor The second terminal is coupled to the positive input terminal of the first bias operational amplifier and the first terminal of the rising slew rate control resistor, the second terminal of the rising slew rate control resistor is coupled to the second power supply terminal, and the first terminal of the rising slew rate control resistor is coupled to the second power supply terminal. The gate of a bias transistor is coupled to the second power supply terminal, the negative input terminal of the first bias voltage operational amplifier is coupled to a power supply terminal, and the voltage of the power supply terminal is the voltage of the first power supply terminal and the second power supply terminal. Voltage average, the output terminal of the first bias voltage operational amplifier is coupled to the adjustment terminal of the first bias voltage variable resistor and the first bias voltage signal node; the second bias voltage circuit includes a second bias voltage variable resistor, a second bias transistor, a second bias operational amplifier, and a falling slew rate control resistor; and the first end of the falling slew rate control resistor is coupled to the first power supply terminal, the falling slew rate control resistor The second terminal of the second biased operational amplifier is coupled to the positive input terminal of the second biased operational amplifier and the first terminal of the second biased transistor, the negative input terminal of the second biased operational amplifier is coupled to a power supply terminal and the power supply The voltage at terminal is the average voltage of the first power supply terminal and the second power supply terminal, the second terminal of the second bias transistor is coupled to the first terminal of the second bias variable resistor, the second bias transistor The gate is coupled to the first power terminal, the second terminal of the second bias variable resistor is coupled to the second power terminal, and the adjustment terminal of the second bias variable resistor is coupled to the second bias The output terminal of the voltage operational amplifier and the second bias signal node; wherein, the first bias variable resistor and the first bias transistor are respectively connected with the first variable resistor and the first slew rate control circuit The first output transistor has substantially the same electrical characteristics, the second bias voltage variable resistor and the second bias voltage transistor respectively have the same electrical characteristics as the second variable resistor and the second output transistor of the second slew rate control circuit. With substantially the same electrical characteristics, the rising slew rate control resistor and the falling slew rate control resistor have substantially the same impedance.

The aforementioned output circuit, wherein the first bias circuit includes a first bias resistor, a first adjustment transistor, a first bias transistor, a first bias operational amplifier and a rising slew rate control resistor, Wherein the first bias resistor and the first adjusting transistor are coupled in parallel to form a first bias variable resistor; the first bias resistor, the first bias transistor and the rising slew rate control resistor are coupled in series and Connected between the first power supply terminal and the second power supply terminal, the positive input terminal of the first bias operational amplifier is coupled to the common node of the first bias transistor and the rising slew rate control resistor, the first bias operational amplifier The negative input terminal of a bias operational amplifier is coupled to a power supply terminal, and the voltage of the power supply terminal is the average of the voltages of the first power supply terminal and the second power supply terminal, and the output terminal of the first bias operational amplifier is coupled to the first power supply terminal. A gate electrode of an adjustment transistor and the first bias signal node; the second bias circuit includes a second bias resistor, a second adjustment transistor, a second bias transistor, a second bias operational amplifier, and a falling slew rate control resistor, wherein the second bias resistor and the second adjusting transistor are coupled in parallel to form a second bias voltage variable resistor; and the falling slew rate control resistor, the second bias transistor and the first Two bias resistors are coupled in series and connected between the first power supply terminal and the second power supply terminal, and the positive input terminal of the second bias voltage operational amplifier is coupled to the falling slew rate control resistor and the second bias voltage. The common node of the voltage transistor, the negative input terminal of the second bias operational amplifier is coupled to a power supply terminal and the voltage of the power supply terminal is the average of the voltages of the first power supply terminal and the second power supply terminal, the second bias operational amplifier The output terminal of the second adjustment transistor is coupled to the gate of the second adjustment transistor and the second bias signal node; wherein, the first bias voltage variable resistor and the first bias voltage transistor are respectively connected to the first slew rate control circuit The first variable resistor and the first output transistor have substantially the same electrical characteristics, and the second bias variable resistor and the second bias transistor are respectively the same as the second variable resistor of the second slew rate control circuit. The resistor and the second output transistor have substantially the same electrical characteristics, and the rising slew rate control resistor and the falling slew rate control resistor have substantially the same impedance.

The aforementioned output circuit, wherein the first variable resistor includes a first control transistor and a second control transistor coupled in parallel, the first end of the first control transistor is coupled to the first end of the second control transistor end and the first power supply end, the second end of the first control transistor is coupled to the second end of the second control transistor, the gate of the first control transistor and the first output transistor, the second control transistor the gate of which is coupled to a first bias signal node of the first bias circuit; and the second variable resistor includes a third control transistor and a fourth control transistor coupled in parallel, the third control transistor The first terminal is coupled to the first terminal of the fourth control transistor, the gate of the third control transistor and the second output transistor, and the second terminal of the third control transistor is coupled to the first terminal of the fourth control transistor. The two terminals, the second power supply terminal and the gate of the fourth control transistor are coupled to a second bias signal node of the second bias circuit.

The purpose of the present invention and the solution to its technical problems are also achieved by the following technical solutions. An output circuit according to the present invention includes: an input node and an input complementary node; an output node and an output complementary node; a first output transistor and a second output transistor coupled in series; a third output The transistor and a fourth output transistor are coupled in series; a first slew rate control (slew rate) circuit is coupled to a first power supply terminal and a common node (common node) of the first output transistor and the third output transistor between, is configured to provide variable resistance; and a second slew rate control circuit, coupled between a second power supply terminal and the common node of the second output transistor and the fourth output transistor, is configured Used to provide variable resistance; wherein, the input node is coupled to the gate of the first output transistor and the gate of the second output transistor, and the output node is coupled to the first output transistor and the second output A common node of transistors, the input complementary node is coupled to the gate of the third output transistor and the gate of the fourth output transistor, the output complementary node is coupled to the common of the third output transistor and the fourth output transistor node.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The aforementioned output circuit further includes: a first output resistor coupled to the output node and a common node between the first output transistor and the second output transistor; and a second output resistor coupled to the output complementary node and a common node of the third output transistor and the fourth output transistor.

The aforementioned output circuit further includes: a first capacitor coupled to the second power supply terminal and the common node of the first output transistor, the third output transistor and the first slew rate control circuit; and a second The capacitor is coupled to the second power terminal and a common node of the second output transistor, the fourth output transistor and the second slew rate control circuit.

The aforementioned output circuit, wherein the first slew rate control circuit includes a first variable resistor, wherein the resistance of the first variable resistor responds to a first bias signal from a first bias circuit; And the second slew rate control circuit includes a second variable resistor, wherein the resistance of the second variable resistor responds to a second bias signal from a second bias circuit.

The aforementioned output circuit, wherein the first variable resistor includes a first resistor and a first control transistor coupled in parallel, wherein the gate of the first control transistor is coupled to a first bias circuit of the first a bias signal node; and

The second variable resistor includes a second resistor and a second control transistor coupled in parallel, wherein the gate of the second control transistor is coupled to a second bias signal node of the second bias circuit.

In the aforementioned output circuit, both the first output transistor and the first control transistor are PMOS transistors, and the second output transistor and the second control transistor are both NMOS transistors.

The aforementioned output circuit, wherein the first bias circuit includes a first bias transistor and a second bias transistor coupled in series and across between the first power supply terminal and the second power supply terminal, the The first bias signal node is coupled to the gate of the first bias transistor, the gate of the second bias transistor, and the common node of the first bias transistor and the second bias transistor;

The second bias circuit includes a third bias transistor and a fourth bias transistor coupled in series and connected between the first power supply terminal and the second power supply terminal, the second bias voltage signal node is coupled to to the gate of the third bias transistor, the gate of the fourth bias transistor, and the common node of the third bias transistor and the fourth bias transistor; and

The electrical characteristics of the first bias transistor and the electrical characteristics of the third bias transistor are substantially the same as the electrical characteristics of the first output transistor, and the electrical characteristics of the second bias transistor and the fourth bias transistor The electrical characteristics of are substantially the same as the electrical characteristics of the second output transistor.

The aforementioned output circuit, wherein the first output transistor, the first control transistor, the first bias transistor and the third bias transistor are all PMOS transistors, and the second output transistor, the second control transistor , the second bias transistor and the fourth bias transistor are all NMOS transistors.

The aforementioned output circuit, wherein said first bias circuit includes a first bias variable resistor, a first bias transistor, a first bias operational amplifier and a rising slew rate control resistor; the first bias The first terminal of the voltage variable resistor is coupled to the first power supply terminal, the second terminal of the first bias variable resistor is coupled to the first terminal of the first bias transistor, and the first bias transistor The second terminal is coupled to the positive input terminal of the first bias operational amplifier and the first terminal of the rising slew rate control resistor, the second terminal of the rising slew rate control resistor is coupled to the second power supply terminal, and the first terminal of the rising slew rate control resistor is coupled to the second power supply terminal. The gate of a bias transistor is coupled to the second power supply terminal, the negative input terminal of the first bias voltage operational amplifier is coupled to a power supply terminal, and the voltage of the power supply terminal is the voltage of the first power supply terminal and the second power supply terminal. Voltage average, the output terminal of the first bias voltage operational amplifier is coupled to the adjustment terminal of the first bias voltage variable resistor and the first bias voltage signal node; the second bias voltage circuit includes a second bias voltage variable resistor, a second bias transistor, a second bias operational amplifier, and a falling slew rate control resistor; and the first end of the falling slew rate control resistor is coupled to the first power supply terminal, the falling slew rate control resistor The second terminal of the second biased operational amplifier is coupled to the positive input terminal of the second biased operational amplifier and the first terminal of the second biased transistor, the negative input terminal of the second biased operational amplifier is coupled to a power supply terminal and the power supply The voltage at terminal is the average voltage of the first power supply terminal and the second power supply terminal, the second terminal of the second bias transistor is coupled to the first terminal of the second bias variable resistor, the second bias transistor The gate is coupled to the first power terminal, the second terminal of the second bias variable resistor is coupled to the second power terminal, and the adjustment terminal of the second bias variable resistor is coupled to the second bias The output terminal of the voltage operational amplifier and the second bias signal node; wherein, the first bias variable resistor and the first bias transistor are respectively connected with the first variable resistor and the first slew rate control circuit The first output transistor has substantially the same electrical characteristics, the second bias voltage variable resistor and the second bias voltage transistor respectively have the same electrical characteristics as the second variable resistor and the second output transistor of the second slew rate control circuit. With substantially the same electrical characteristics, the rising slew rate control resistor and the falling slew rate control resistor have substantially the same impedance.

The aforementioned output circuit, wherein the first bias circuit includes a first bias resistor, a first adjustment transistor, a first bias transistor, a first bias operational amplifier and a rising slew rate control resistor, Wherein the first bias resistor and the first adjusting transistor are coupled in parallel to form a first bias variable resistor; the first bias resistor, the first bias transistor and the rising slew rate control resistor are coupled in series and Connected between the first power supply terminal and the second power supply terminal, the positive input terminal of the first bias operational amplifier is coupled to the common node of the first bias transistor and the rising slew rate control resistor, the first bias operational amplifier The negative input terminal of a bias operational amplifier is coupled to a power supply terminal, and the voltage of the power supply terminal is the average of the voltages of the first power supply terminal and the second power supply terminal, and the output terminal of the first bias operational amplifier is coupled to the first power supply terminal. A gate electrode of an adjustment transistor and the first bias signal node; the second bias circuit includes a second bias resistor, a second adjustment transistor, a second bias transistor, a second bias operational amplifier, and a falling slew rate control resistor, wherein the second bias resistor and the second adjusting transistor are coupled in parallel to form a second bias voltage variable resistor; and the falling slew rate control resistor, the second bias transistor and the first Two bias resistors are coupled in series and connected between the first power supply terminal and the second power supply terminal, and the positive input terminal of the second bias voltage operational amplifier is coupled to the falling slew rate control resistor and the second bias voltage. The common node of the voltage transistor, the negative input terminal of the second bias operational amplifier is coupled to a power supply terminal and the voltage of the power supply terminal is the average of the voltages of the first power supply terminal and the second power supply terminal, the second bias operational amplifier The output terminal of the second adjustment transistor is coupled to the gate of the second adjustment transistor and the second bias signal node; wherein, the first bias voltage variable resistor and the first bias voltage transistor are respectively connected to the first slew rate control circuit The first variable resistor and the first output transistor have substantially the same electrical characteristics, and the second bias variable resistor and the second bias transistor are respectively the same as the second variable resistor of the second slew rate control circuit. The resistor and the second output transistor have substantially the same electrical characteristics, and the rising slew rate control resistor and the falling slew rate control resistor have substantially the same impedance.

The aforementioned output circuit, wherein the first variable resistor includes a first control transistor and a second control transistor coupled in parallel, the first terminal of the first control transistor is coupled to the second control transistor of the second control transistor One terminal and the first power supply terminal, the second terminal of the first control transistor is coupled to the second terminal of the second control transistor, the gate of the first control transistor and the first output transistor, the second control transistor the gate of the transistor is coupled to a first bias signal node of the first bias circuit; and the second variable resistor includes a third control transistor and a fourth control transistor coupled in parallel, the third control transistor The first end of the third control transistor is coupled to the first end of the fourth control transistor, the gate of the third control transistor and the second output transistor, and the second end of the third control transistor is coupled to the fourth control transistor. The second terminal, the second power supply terminal, and the gate of the fourth control transistor are coupled to a second bias signal node of the second bias circuit.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from the above technical solutions, in order to achieve the aforementioned object of the invention, the main technical contents of the present invention are as follows:

The present invention proposes an output circuit, including an input node, an output node, a first output transistor, a second output transistor, a first slew rate control circuit and a second slew rate control circuit. The first output transistor and the second output transistor are coupled in series. The first slew rate control circuit is coupled between the first output transistor and the first power terminal. The second slew rate control circuit is coupled between the second output transistor and the second power terminal. The input node is coupled to the gate of the first output transistor and the gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second output transistor.

By means of the above-mentioned technical solution, the present invention has at least the following advantages: the output circuit of the slew rate control of the present invention maintains a specific and symmetrical slew rate (slew rate) regardless of how the process, voltage and temperature change, so that it is more suitable It is practical and has industrial utilization value.

To sum up, the output circuit of the slew rate control of the special structure of the present invention has the above-mentioned many advantages and practical value, and no similar structural design has been published or used in similar products, so it is indeed an innovation. There are great improvements in structure or function, and great progress in technology, and have produced easy-to-use and practical effects, and have improved multiple functions compared with existing output circuits, so they are more suitable for It is practical, and has wide application value in the industry. It is a novel, progressive and practical new design.

The above description is only an overview of the technical solutions of the present invention. In order to understand the technical means of the present invention more clearly and implement them according to the contents of the description, the preferred embodiments of the present invention and accompanying drawings are described in detail below.

Description of drawings

Fig. 1 is a circuit diagram of a preferred embodiment of the output circuit in the present invention.

Fig. 2 is a circuit diagram of another preferred embodiment of the output circuit in the present invention.

FIG. 3 is a circuit diagram of the output circuit shown in FIG. 2 , wherein the variable resistor includes a resistor and a transistor coupled in parallel.

FIG. 4 is a circuit diagram of the output circuit shown in FIG. 2 , wherein the variable resistor includes two transistors coupled in parallel.

Fig. 5 is a circuit diagram of the first preferred embodiment of the bias circuit in the present invention.

6A and 6B are circuit diagrams of the second preferred embodiment of the bias circuit in the present invention.

FIGS. 7A and 7B are circuit diagrams of the bias circuit shown in FIGS. 6A and 6B , wherein the variable resistor includes a resistor and a transistor coupled in parallel.

FIG. 8 is a circuit diagram of a preferred embodiment of an output circuit with different input and output signals in the present invention.

FIG. 9 is a circuit diagram of another preferred embodiment of the output circuit with different input and output signals in the present invention.

100, 200, 800, 900: output circuit 110: input node

120: output node 130: first output transistor

140: The second output transistor 150, 850: The first slew rate control circuit

160, 860: the second slew rate control circuit 170, 870: the first power supply terminal

180, 880: Second power supply terminal 210, 910, 920: Output resistance

220, 930: the first capacitor 230, 940: the second capacitor

240, 950: the first variable resistor 250, 960: the second variable resistor

310: first resistor 320: first control transistor

330: Second resistor 340: Second control transistor

410: first control transistor 420: second control transistor

430: The third control transistor 440: The fourth control transistor

500, 600, 650: bias circuit 510, 520: bias transistor

610: first bias variable resistor 620, 720: first bias transistor

630, 730: first bias operational amplifier 640, 740: rising slew rate control resistor

660: second bias variable resistor 670, 770: second bias transistor

680, 780: second bias op amp 690, 790: falling slew rate control resistor

710: first bias resistor 715: first adjustment transistor

760: second bias resistor 765: second adjustment transistor

810: Input node 815: Input complementary node

820: Output node 825: Output complementary node

830: the first output transistor 835: the third output transistor

840: Second output transistor 845: Fourth output transistor

Detailed ways

The specific implementation, structure, features and functions of the output circuit for slew rate control according to the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

Please refer to FIG. 1 , which is a circuit diagram of a preferred embodiment of the output circuit in the present invention. The output circuit 100 includes an input node 110 , an output node 120 , a first output transistor 130 , a second output transistor 140 , a first slew rate control circuit 150 and a second slew rate control circuit 160 . The first output transistor 130 and the second output transistor 140 are coupled in series. The first slew rate control circuit 150 is coupled between the first power terminal 170 and the first output transistor 130 . The second slew rate control circuit 160 is coupled between the second output transistor 140 and the second power terminal 180 . The input node 110 is coupled to the gate of the first output transistor 130 and the gate of the second output transistor 140 . The output node 120 is coupled to a common node of the first output transistor 130 and the second output transistor 140 .

When the output voltage switches from a high level to a low level or from a low level to a high level, both the first output transistor 130 and the second output transistor 140 are turned on and work in a saturation region. The resistance values of the first output transistor 130 and the second output transistor 140 will affect the rising slew rate and the falling slew rate. Due to variations in process, power supply voltage and temperature, electrical characteristics (such as resistance values of the first output transistor 130 and the second output transistor 140 ) will also vary accordingly. Therefore, the rising slew rate as well as the falling slew rate of the output voltage from the output node 120 may not meet the required range and may not be symmetrical.

Preferably, the first and second slew rate control circuits provide a variable resistance to compensate any difference in resistance between the first output transistor 130 and the second output transistor 140 . By adjusting the variable resistance, the equivalent resistance of the first slew rate control circuit 150 and the first output transistor 130 (the upper half of the output circuit shown in FIG. 1 ), and the second slew rate control circuit 160 The equivalent resistance of the second output transistor 140 (the lower half of the output circuit shown in FIG. 1 ) is substantially the same. For example, if the resistance of the first output transistor 130 is higher than the resistance of the second output transistor 140, the variable resistance of the first slew rate control circuit will be adjusted to be higher than the variable resistance of the second slew rate control circuit. The value is low to compensate for the resistance difference between the first output transistor 130 and the second output transistor 140 . Since the upper half and the lower half of the output circuit 100 have substantially the same resistance, the rising slew rate is substantially the same as the falling slew rate. Therefore, the output voltage of the transistor is symmetrical from high level to low level and from low level to high level.

Because the variable resistances of the first slew rate control circuit 150 and the second slew rate control circuit 160 are dynamically adjusted in response to changes in power supply voltage and temperature, the resistance of the upper part of the output circuit 100 is still substantially the same as the output The lower half of circuit 100 has the same resistance. Therefore, the rising and falling slew rates remain symmetrical during these moves.

In one embodiment, the first output transistor 130 is a PMOS transistor, and the second output transistor 140 is an NMOS transistor. The first power terminal provides a positive voltage VDD to the output circuit 100 , and the second power terminal provides a ground voltage to the output circuit 100 . The source of the PMOS transistor 130 is coupled to the first slew rate control circuit 150 . The output node 120 is coupled to the drain of the PMOS transistor 130 and the drain of the NMOS transistor 140 . The source of the NMOS transistor 140 is coupled to the second slew rate control circuit 160 . The input node 110 of the output circuit 100 is coupled to the gate of the PMOS transistor 130 and the gate of the NMOS transistor 140 . In other embodiments, the first output transistor 130 and the second output transistor 140 may be other types of transistors. The second power terminal 180 may provide a lower positive voltage than that provided by the first power terminal, or may provide a negative voltage.

Please refer to FIG. 2 , which is a circuit diagram of another preferred embodiment of the output circuit in the present invention. Compared with the output circuit 100 shown in FIG. 1 , the output circuit 200 shown in FIG. 2 further includes a resistor 210 and two capacitors 220 and 230 . In addition, the first slew rate control circuit 150 includes a first variable resistor 240 , and the second slew rate control circuit 160 includes a second variable resistor 250 . The first variable resistor 240 is adjusted according to the first bias signal from the first bias circuit. The second variable resistor 250 is adjusted according to the second bias signal from the second bias circuit. The output resistor 210 is coupled between the output node 120 and a common node of the first output transistor 130 and the second output transistor 140 . The output resistor 210 can mitigate signal reflections and distortion caused by any impedance mismatch between the output circuit 200 and the external load circuit.

In the circuit of FIG. 2 , the first capacitor 220 is coupled to the second power terminal 180 and the common node of the first output transistor 130 and the first variable resistor 240 . The second capacitor 230 is coupled to the second power terminal 180 and a common node of the second output transistor 140 and the second variable resistor 250 . The first capacitor 220 and the second capacitor 230 can improve the symmetry of the output rising and falling slew rate, but also slow down the working speed of the circuit.

In the first embodiment, the first output transistor 130 is a PMOS transistor, and the second output transistor 140 is an NMOS transistor. The first power terminal 170 provides a positive voltage VDD to the output circuit 100 , and the second power terminal 180 provides a ground voltage to the output circuit 100 . One end of the output resistor 210 is coupled to the output node 120 . The other end of the output resistor 210 is coupled to the drain of the PMOS transistor 130 and the drain of the NMOS transistor 140 . One terminal of the first capacitor 220 is coupled to the ground voltage. The other end of the first capacitor 220 is coupled to the first variable resistor 240 and the source of the PMOS transistor 130 . One end of the second capacitor 230 is coupled to the ground voltage. The other end of the second capacitor 230 is coupled to the second variable resistor 250 and the source of the NMOS transistor 140 .

Please refer to FIG. 3 , which is a circuit diagram of the output circuit shown in FIG. 2 , wherein the variable resistor includes a resistor and a transistor coupled in parallel. As shown in FIG. 3 , a first preferred embodiment of the first variable resistor 240 includes a first resistor 310 and a first control transistor 320 coupled in parallel. The gate of the first control transistor 320 is coupled to the first bias signal node of the first bias circuit. Likewise, the first preferred embodiment of the second variable resistor 250 includes the second resistor 330 and the second control transistor 340 coupled in parallel. The gate of the second control transistor 340 is coupled to the second bias signal node of the second bias circuit.

The first resistor 310 and the first control transistor 320 are coupled in parallel to realize the function of the variable resistor 240 . The larger the resistance value of the first resistor 310 is, the larger the adjustable resistance range of the first variable resistor is. The gate of the first control transistor 320 receives the first bias signal from the first bias circuit to control the amount of current flowing through the first control transistor 320 and the first resistor 310 respectively, so as to provide the required equivalent resistance . The same principle of operation applies to the second resistor 330 and the second control transistor 340 .

Due to variations in the semiconductor manufacturing process, the first output transistor 130 may operate with a lower resistance than the second output transistor 140 . The voltage of the first bias signal is increased as much as possible to increase the resistance of the first variable resistor 240 . The voltage of the second bias signal is increased as much as possible to reduce the resistance of the second variable resistor 250 . Therefore, the equivalent resistance values of the first output transistor 130 and the first variable resistor 240 and the equivalent resistance values of the second output transistor 140 and the second variable resistor 250 are substantially the same.

When the operating temperature increases, the resistance of the first output transistor 130 will increase. In response to temperature changes, the first bias circuit reduces the voltage of the first bias signal as much as possible, so that the resistance of the first variable resistor 240 decreases. Likewise, due to the increase of the operating temperature, the resistance of the second output transistor 140 will also increase. In response to temperature changes, the second bias circuit increases the voltage of the second bias signal as much as possible, so that the resistance of the second variable resistor 250 decreases. Therefore, during the period of temperature fluctuation, the equivalent resistance values of the first output transistor 130 and the first variable resistor 240, and the equivalent resistance values of the second output transistor 140 and the second variable resistor 250 will still substantially vary. same.

When the power voltage of the first power terminal increases, the resistance of the first output transistor 130 generally decreases due to the increase of the operating speed. In response to the change of the power supply voltage, the first bias circuit increases the voltage of the first bias signal as much as possible, so that the resistance of the first variable resistor 240 increases. Likewise, the resistance of the second output transistor 140 generally decreases in response to the increase of the power supply voltage. Then, in response to the voltage change, the second bias circuit reduces the voltage of the second bias signal as much as possible to increase the resistance of the second variable resistor 250 . Therefore, during the fluctuation of the power supply voltage, the equivalent resistance values of the first output transistor 130 and the first variable resistor 240 and the equivalent resistance values of the second output transistor 140 and the second variable resistor 250 are substantially the same. will be the same.

In one embodiment, both the first output transistor 130 and the first control transistor 320 are PMOS transistors. Both the second output transistor 140 and the second control transistor 340 are NMOS transistors. The first power terminal 170 provides a positive voltage VDD, and the second power terminal 180 provides a ground voltage. The source of the PMOS transistor 320 is coupled to one terminal of the first resistor 310 and VDD. The drain of the PMOS transistor 320 is coupled to the other end of the first resistor 310 , the source of the PMOS transistor 130 and one end of the first capacitor 220 . The source of the NMOS transistor 340 is coupled to one end of the second resistor 330 and ground. The drain of the NMOS transistor 340 is coupled to the other end of the second resistor 330 , the source of the NMOS transistor 140 and one end of the second capacitor 230 .

When the gate of the PMOS transistor 320 receives a lower voltage of the first bias signal, the PMOS transistor 320 is turned on to a higher degree. More current flows through PMOS transistor 320 . The resistance of the first variable resistor 240 will decrease. When the voltage of the first bias signal received by the gate of the PMOS transistor 320 is relatively high, the conduction degree of the PMOS transistor 320 is low. Less current flows through PMOS transistor 320 . The resistance of the first variable resistor 240 will increase. When the voltage of the second bias signal received by the gate of the NMOS transistor 340 is low, the conduction degree of the NMOS transistor 340 is low. Less current flows through NMOS transistor 340 . The resistance of the second variable resistor 250 will increase. When the gate of the NMOS transistor 340 receives a higher voltage of the second bias signal, the NMOS transistor 340 is turned on to a higher degree. More current flows through NMOS transistor 340 . The resistance of the second variable resistor 250 will decrease.

Please refer to FIG. 4 , which is a circuit diagram of the output circuit shown in FIG. 2 , wherein the variable resistor includes two transistors coupled in parallel. As shown in FIG. 4 is a second embodiment of the first variable resistor 240 and the second variable resistor 250 . Here, the first variable resistor 240 includes a first control transistor 410 and a second control transistor 420 coupled in parallel, and the second variable resistor 250 includes a third control transistor 430 and a fourth control transistor 440 coupled in parallel. Those skilled in the art can use various other methods to realize the first variable resistor 240 and the second variable resistor 250 .

The first control transistor 410 and the second control transistor 420 are coupled in parallel to complete the function of the first variable resistor 240 . The gate of the second control transistor 420 receives the first bias signal from the first bias circuit to control the amount of current flowing through the first control transistor 410 and the second control transistor 420 respectively, so as to provide the required equivalent resistance. value. The same principle of operation applies to the third control transistor 430 and the fourth control transistor 440 .

In one embodiment, both the first control transistor 410 and the second control transistor 420 are PMOS transistors. Both the third control transistor 430 and the fourth control transistor 440 are NMOS transistors. The first power terminal 170 provides a positive voltage VDD, and the second power terminal 180 provides a ground voltage. The sources of the PMOS transistors 410 and 420 are both coupled to VDD. The drains of the PMOS transistors 410 and 420 and the gate of the PMOS transistor 410 are both coupled to the first output transistor 130 . The gate of the PMOS transistor 420 is coupled to the first bias signal node of the first bias circuit. Likewise, for the second variable resistor, the drains of the NMOS transistors 430 and 440 are both coupled to the second output transistor 140 . The sources of NMOS transistors 430 and 440 are both grounded. The gate of the NMOS transistor 430 is coupled to the second output transistor 140 . The gate of the NMOS transistor 440 is coupled to the second bias signal node of the second bias circuit.

The first PMOS transistor 410 acts like a resistor when V _DS > _VPth , and is non-conductive when V _DS < _VPth , where V _DS is the voltage difference between the drain and source of the PMOS transistor, and _VPth is The threshold voltage of the PMOS transistor. The second PMOS transistor 420 acts like a resistor when V _DS < _VPth , and has a very large resistance when V _DS > _VPth . Therefore, the first PMOS transistor 410 and the second PMOS transistor 420 are coupled in parallel, functioning as a variable resistor, and the resistance of the variable resistor is related to the entire voltage range of the first bias signal. The same principle applies to the first NMOS transistor 430 and the second NMOS transistor 440 .

The first bias circuit and the second bias circuit function as a sensor for sensing process, power voltage and temperature variations (referred to as PVT variations). To reflect the resistance values of the first output resistor 130 and the second output resistor 140 changed by PVT changes, the first bias circuit adjusts the first bias signal to control the first variable resistor 240, and the second bias circuit adjusts the first variable resistor 240. Two bias signals are used to control the second variable resistor 250 . Therefore, the equivalent resistance values of the first variable resistor 240 and the first output transistor 130 , and the equivalent resistance values of the second variable resistor 250 and the second output transistor 140 are substantially the same.

Please refer to FIG. 5 , which is a circuit diagram of the first preferred embodiment of the bias circuit in the present invention. As shown in FIG. 5 , the bias circuit 500 provides the same bias signal to control the first variable resistor 240 and the second variable resistor 250 . Therefore, the common bias signal node can be applied to the first bias signal node and the second bias signal node. The bias circuit 500 includes a first bias transistor 510 and a second bias transistor 520 coupled in series and connected across the first power terminal 170 and the second power terminal 180 . The first bias signal node and the second bias signal node are coupled to the gate of the first bias transistor 510, the gate of the second bias transistor 520, and the gates of the first bias transistor 510 and the second bias transistor 520. shared node. In addition, the electrical characteristics of the first bias transistor 510 are substantially the same as those of the first output transistor 130 , and the electrical characteristics of the second bias transistor 520 are substantially the same as those of the second output transistor 140 .

In one implementation of the first preferred embodiment, the first bias transistor 510 is a PMOS transistor, and the second bias transistor 520 is an NMOS transistor. The first power terminal 170 provides a positive voltage VDD, and the second power terminal 180 provides a ground voltage. The source of the PMOS transistor 510 is coupled to the power supply VDD. The source of the NMOS transistor 520 is grounded. Both the gate and the drain of the PMOS transistor 510 and the NMOS transistor 520 are coupled to a common bias signal node.

Due to their similar characteristics, if the PMOS transistor 130 operates with a lower resistance than the NMOS transistor 140 , the PMOS transistor 510 will also operate with the same lower resistance than the NMOS transistor 520 . The voltage of the bias signal from the bias circuit 500 is higher than VDD/2. The higher voltage bias signal reduces the resistance of the first variable resistor 240 (including the PMOS transistor), and increases the resistance of the second variable resistor 250 (including the NMOS transistor). Therefore, during the process variation, the equivalent resistance values of the PMOS transistor 130 and the first variable resistor 240 , and the equivalent resistance values of the NMOS transistor 140 and the second variable resistor 250 will be substantially the same.

When the temperature or power supply voltage rises and causes the resistance values of the first output transistor 130 and the second output transistor 140 to change differently, the adjusted bias signal can change the first variable resistor 240 and the second variable resistor 250 to compensate The difference in resistance between the first output transistor 130 and the second output transistor 140 .

Please refer to FIGS. 6A and 6B , which are the second embodiment of the first bias circuit and the second bias circuit, which respectively provide the first bias signal and the second bias signal. These two independent bias signals can more precisely control and maintain the first slew rate and the second slew rate through the negative feedback work of an operational amplifier over process, supply voltage and temperature variations.

6A and 6B are circuit diagrams of the second preferred embodiment of the bias circuit in the present invention. 6A and 6B respectively show the second embodiment of the first bias circuit 600 and the second bias circuit 650 . The first bias circuit 600 includes a first bias variable resistor 610 , a first bias transistor 620 , a first bias operational amplifier 630 and a rising slew rate control resistor 640 . A first terminal of the first bias variable resistor 610 is coupled to the first power terminal 170 . The second terminal of the first bias variable resistor 610 is coupled to the first terminal of the first bias transistor 620 . The second terminal of the first bias transistor 620 is coupled to the positive input terminal of the first bias operational amplifier 630 and one terminal of the rising slew rate control resistor 640 . The other terminal of the rising slew rate control resistor 640 is coupled to the second power terminal 180 . The gate of the first bias transistor 620 is coupled to the second power terminal 180 . The negative input terminal of the first bias operational amplifier 630 is coupled to a power terminal, and the voltage of the power terminal is the average voltage of the first power terminal 170 and the second power terminal 180 . The output terminal of the first bias voltage operational amplifier 630 is coupled to the adjustment terminal of the first bias voltage variable resistor 610 and the first bias voltage signal node. In addition, the electrical characteristics of the first bias variable resistor 610 are substantially the same as the electrical characteristics of the first variable resistor 240 of the first slew rate control circuit, and the electrical characteristics of the first bias transistor 620 are substantially the same as the first output The electrical characteristics of transistor 130 are the same.

Likewise, the second bias voltage circuit 650 includes a second bias voltage variable resistor 660 , a second bias voltage transistor 670 , a second bias voltage operational amplifier 680 and a down slew rate control resistor 690 . One terminal of the falling slew rate control resistor 690 is coupled to the first power supply terminal 170 . The other terminal of the falling slew rate control resistor 690 is coupled to the positive input terminal of the second bias operational amplifier 680 and the first terminal of the second bias transistor 670 . The negative input terminal of the second bias operational amplifier 680 is coupled to a power terminal, and the voltage of the power terminal is the average voltage of the first power terminal 170 and the second power terminal 180 . A second terminal of the second bias transistor 670 is coupled to a first terminal of the second bias variable resistor 660 . The gate of the second bias transistor 670 is coupled to the first power terminal 170 . A second terminal of the second bias variable resistor 660 is coupled to the second power terminal 180 . The adjustment terminal of the second bias variable resistor 660 is coupled to the output terminal of the second bias operational amplifier 680 and the second bias signal node. In addition, the electrical characteristics of the second bias variable resistor 660 are substantially the same as the electrical characteristics of the second variable resistor 250 of the second slew rate control circuit, and the electrical characteristics of the second bias transistor 670 are substantially the same as the second output The electrical characteristics of transistor 140 are the same. Moreover, the resistance of the rising slew rate control resistor 640 is substantially the same as that of the falling slew rate control resistor 690 .

Based on the above, the resistance (R) of the rising and falling slew rate control resistors 640 and 690 is determined by the desired rising time (τ) of the output circuit and the capacitance ( _CL ) of the load circuit.

For a first-order system, R∼τ/C _L .

For example, assuming that the required rise time is 200 ps and the load capacitance is 10 pf, the resistance of the balancing resistor is 20 ohms (Ω). Rise slew rate is approximately the voltage difference from logic low to logic high divided by the required rise time.

Because of the negative feedback function of the first bias operational amplifier 630 , the equivalent resistances of the first bias variable resistor 610 and the first bias transistor 620 are substantially the same as the resistance of the rising slew rate control resistor 640 . The rising slew rate control resistor 640 has a fixed resistance value as desired. In order to respond to changes in the resistance of the first bias transistor 620 due to PVT fluctuations, the first bias variable resistor 610 will be adjusted to ensure that the first bias variable resistor 610 is equivalent to the first bias transistor 620 The resistance value will still be the same. In addition, the first bias variable resistor 610 simulates the first variable resistor 240 of the first slew rate control circuit. The first bias transistor 620 simulates the first output transistor 130 . Through the first bias signal generated from the first bias operational amplifier 630, the equivalent resistance of the first variable resistor 240 and the first output transistor 130, and the first bias variable resistor 610 and the first bias transistor The equivalent resistance of 620, the two will be essentially the same. Therefore, during PVT fluctuations, the rising slew rate remains substantially constant. The same principle applies to the second bias circuit. By setting the resistance of the rising slew rate control resistor 640 to be substantially the same as that of the falling slew rate control resistor 690 , the rising slew rate and the falling slew rate of the output voltage should be the same and symmetrical to each other.

For the second embodiment of the first bias circuit 600 and the second bias circuit 650 shown in Figures 6A and 6B, those who are familiar with the art should know that the first bias variable resistor 610 and the The two bias variable resistors 660 can be implemented in many different ways as long as they respectively simulate the first variable resistor 240 of the first slew rate control circuit and the second variable resistor 250 of the second slew rate control circuit.

Please refer to FIG. 7A , which is a circuit diagram of the bias circuit shown in FIG. 6A , wherein the variable resistor includes a resistor and a transistor coupled in parallel. As shown in FIG. 7A, the first bias voltage variable resistor 610 may include a first bias voltage resistor 710 and a first adjustment transistor 715. This first bias voltage variable resistor 610 acts as a first variable resistor like a first slew rate control circuit. The variable resistor 240 works like the first preferred embodiment, in which the first variable resistor 240 includes a first resistor 310 and a first control transistor 320 . FIG. 7B is a circuit diagram of the bias circuit shown in FIG. 6B , wherein the variable resistor includes a resistor and a transistor coupled in parallel. As shown in FIG. 7B, the second bias voltage variable resistor 660 may include a second bias voltage transistor 760 and a second adjustment transistor 765. The second bias voltage variable resistor 660 acts as a second variable resistor like a second slew rate control circuit. The second variable resistor 250 in this embodiment includes a second resistor 330 and a second control transistor 340 .

In one embodiment, both the first adjustment transistor 715 and the first bias transistor 720 are preferably PMOS transistors. Both the second adjustment transistor 765 and the second bias transistor 770 are preferably NMOS transistors. The first power terminal 170 provides a positive voltage VDD, and the second power terminal 180 provides a ground voltage. The first bias resistor 710 , the PMOS transistor 720 and the rising slew rate control resistor 740 are coupled in series across the power supply (VDD) and ground. The gate of PMOS transistor 720 is grounded. The PMOS transistor 715 and the first bias resistor 710 are coupled in parallel. The positive input terminal of the first bias operational amplifier 730 is coupled to the common node of the PMOS transistor 720 and the rising slew rate control resistor 740 . The negative input terminal of the first bias operational amplifier 730 is coupled to a power supply having a reference voltage VDD/2. The output terminal of the first bias operational amplifier 730 is coupled to the gate of the PMOS transistor 715 and the first bias signal node.

The falling slew rate control resistor 790 , the NMOS transistor 770 and the second bias resistor 760 are coupled in series and across the power supply (VDD) and ground. The gate of NMOS transistor 770 is coupled to VDD. The NMOS transistor 765 and the second bias resistor 760 are coupled in parallel. The positive input terminal of the second bias operational amplifier 780 is coupled to the common node of the down slew rate control resistor 790 and the NMOS transistor 770 . The negative input terminal of the second bias operational amplifier 780 is coupled to a power supply having a reference voltage VDD/2. The output terminal of the second bias operational amplifier 780 is coupled to the gate of the NMOS transistor 765 and the second bias signal node.

Please refer to FIG. 8 , which is a circuit diagram of a preferred embodiment of an output circuit with different input and output signals in the present invention. As shown in FIG. 8 , an output circuit 800 with different input and output signals can reduce the ground bounce effect caused by signal switching. The output circuit 800 includes an input node 810, an input complementary node 815, an output node 820, an output complementary node 825, a first output transistor 830 coupled in series with a second output transistor 840, a third output transistor 835 coupled in series with a fourth output transistor 845 Connected to the first slew rate control circuit 850 and the second slew rate control circuit 860. The first slew rate control circuit 850 is coupled between the first power terminal 870 and the common node of the first output transistor 830 and the third output transistor 835 . The second slew rate control circuit 860 is coupled between the second power terminal 880 and the common node of the second output transistor 840 and the fourth output transistor 845 . The input node 810 is coupled to the gate of the first output transistor 830 and the gate of the second output transistor 840 . The complementary input node 815 is coupled to the gate of the third output transistor 835 and the gate of the fourth output transistor 845 . The output node 820 is coupled to a common node of the first output transistor 830 and the second output transistor 840 . The complementary output node 825 is coupled to a common node of the third output transistor 835 and the fourth output transistor 845 .

In one embodiment, both the first output transistor 830 and the third output transistor 835 are PMOS transistors, and the second output transistor 840 and the fourth output transistor 845 are both NMOS transistors. The input node 810 is coupled to the gate of the PMOS transistor 830 and the gate of the NMOS transistor 840 . The complementary input node 815 is coupled to the gate of the PMOS transistor 835 and the gate of the NMOS transistor 845 . The output node 820 is coupled to the drain of the PMOS transistor 830 and the drain of the NMOS transistor 840 . The complementary output node 825 is coupled to the drain of the PMOS transistor 835 and the drain of the NMOS transistor 845 . The first slew rate control circuit 850 is coupled to the sources of the PMOS transistors 830 and 835 . The second slew rate control circuit 860 is coupled to the sources of the NMOS transistors 840 and 845 .

Please refer to FIG. 9 , which is a circuit diagram of another preferred embodiment of the output circuit with different input and output signals in the present invention. As shown in FIG. 9 , the output circuit 900 further includes a first resistor 910 , a second resistor 920 , a first capacitor 930 and a second capacitor 940 . The first slew rate control circuit 850 includes a first variable resistor 950 , and the second slew rate control circuit 860 includes a second variable resistor 960 . The first output resistor 910 is coupled between the output node 820 and a common node of the first output transistor 830 and the second output transistor 840 . The second output resistor 920 is coupled between the complementary output node 825 and the common node of the third output transistor 835 and the fourth output transistor 845 . The first output resistor 910 and the second output resistor 920 can reduce reflection and signal distortion caused by impedance mismatch between the output circuit and the load circuit.

In addition, the first capacitor 930 is coupled to the second power supply terminal 880 , and is coupled to a common node of the first output transistor 830 , the third output transistor 835 and the first variable resistor 950 . The second capacitor 940 is coupled to the second power supply terminal 880 and is coupled to a common node of the second output transistor 840 , the fourth output transistor 845 and the second variable resistor 960 . The first capacitor 930 and the second capacitor 940 can improve the symmetry of the output rise and fall slew rate, but may also slow down the circuit operation speed.

In one embodiment, both the first output transistor 830 and the third output transistor 835 are PMOS transistors, and the second output transistor 840 and the fourth output transistor 845 are both NMOS transistors. The first power terminal 870 provides a positive voltage VDD, and the second power terminal 880 provides a ground voltage. One end of the first output resistor 910 is coupled to the output node 820 . The other end of the first output resistor 910 is coupled to the drain of the PMOS transistor 830 and the drain of the NMOS transistor 840 . One end of the second output resistor 920 is coupled to the complementary output node 825 . The other end of the second output resistor 920 is coupled to the drain of the PMOS transistor 835 and the drain of the NMOS transistor 845 . One terminal of the first capacitor 930 is coupled to the ground voltage. The other end of the first capacitor 930 is coupled to the first variable resistor 950 , the source of the PMOS transistor 830 and the source of the PMOS transistor 835 . One end of the second capacitor 940 is coupled to the ground voltage. The other end of the second capacitor 940 is coupled to the second variable resistor 960 , the source of the NMOS transistor 840 and the source of the NMOS transistor 845 .

Both the first and second preferred embodiments of the first variable resistor 240 can be used to implement the first variable resistor 950, while the first and second preferred embodiments of the second variable resistor 250 It can be used to implement the second variable resistor 960. Likewise, both the first and second preferred embodiments of the first bias circuits 500 and 600 can be used to generate a first bias signal to the first variable resistor 950, while the second bias circuits 500 and 650 Both the first and second preferred embodiments can be used to generate the second bias signal to the second variable resistor 960 .

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but all the content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence still belong to the scope of the technical solutions of the present invention.

Claims (22)

1, a kind of output circuit is characterized in that it comprises:

One input node;

One output node;

One first output transistor and one second output transistor coupled in series;

One first revolution rate (slew rate) control circuit is coupled between this first output transistor and one first power end, is that configuration is in order to provide variable resistance; And

One second turnover rate control circuit is coupled between this second output transistor and the second source end, is that configuration is in order to provide variable resistance;

Wherein, this input node is coupled to the gate of this first output transistor and the gate of this second output transistor, and this output node is coupled to the common points of this first output transistor and this second output transistor.

2, output circuit according to claim 1 is characterized in that it more comprises:

One output resistance is coupled to the common points of this output node and this first output transistor and this second output transistor.

3, output circuit according to claim 1 is characterized in that it more comprises:

One first electric capacity is coupled to the common points of this second source end and this first output transistor and this first turnover rate control circuit; And

One second electric capacity is coupled to the common points of this second source end and this second output transistor and this second turnover rate control circuit.

4, output circuit according to claim 1 is characterized in that wherein said

First turnover rate control circuit comprises one first variable resistor, and wherein this first variable-resistance resistance is the one first bias voltage signal of responding from one first bias circuit; And

This second turnover rate control circuit comprises a second adjustable resistance, and wherein the resistance of this second adjustable resistance is the one second bias voltage signal of responding from one second bias circuit.

5, output circuit according to claim 4 is characterized in that wherein said

First variable resistor comprises one first resistance and one first oxide-semiconductor control transistors coupled in parallel, and wherein the gate of this first oxide-semiconductor control transistors is coupled to one first bias voltage signal node of this first bias circuit; And

This second adjustable resistance comprises one second resistance and one second oxide-semiconductor control transistors coupled in parallel, and wherein the gate of this second oxide-semiconductor control transistors is coupled to one second bias voltage signal node of this second bias circuit.

6, output circuit according to claim 5 is characterized in that wherein said

First output transistor and this first oxide-semiconductor control transistors all are the PMOS transistors, and this second output transistor and this second oxide-semiconductor control transistors all are nmos pass transistors.

7, output circuit according to claim 5 is characterized in that wherein said

First bias circuit comprises one first bias transistor and one second bias transistor coupled in series and cross-over connection between this first power end and this second source end, and this first bias voltage signal node is coupled to the gate of this first bias transistor, the gate of this second bias transistor and the common points of this first bias transistor and this second bias transistor;

This second bias circuit comprises one the 3rd bias transistor and one the 4th bias transistor coupled in series and cross-over connection between this first power end and this second source end, and this second bias voltage signal node is coupled to the gate of the 3rd bias transistor, the gate of the 4th bias transistor and the common points of the 3rd bias transistor and the 4th bias transistor; And

The electrical characteristic of the electrical characteristic of this first bias transistor and the 3rd bias transistor in fact all electrical characteristic with this first output transistor is identical, and the electrical characteristic of the electrical characteristic of this second bias transistor and the 4th bias transistor in fact all the electrical characteristic with this second output transistor is identical.

8, output circuit according to claim 7 is characterized in that wherein said

First output transistor, this first oxide-semiconductor control transistors, this first bias transistor and the 3rd bias transistor all are the PMOS transistors, and this second output transistor, this second oxide-semiconductor control transistors, this second bias transistor and the 4th bias transistor all are nmos pass transistors.

9, output circuit according to claim 4 is characterized in that wherein said

First bias circuit comprises one first bias-variable resistance, one first bias transistor, one first bias voltage operational amplifier and a rising revolution rate controlling resistance;

First end of this first bias-variable resistance is coupled to this first power end, second end of this first bias-variable resistance is coupled to first end of this first bias transistor, second end of this first bias transistor is coupled to the positive input terminal of this first bias voltage operational amplifier and first end that should rising revolution rate controlling resistance, second end of this rising revolution rate controlling resistance is coupled to this second source end, the gate of this first bias transistor is coupled to this second source end, the voltage that the negative input end of this first bias voltage operational amplifier is coupled to a power end and this power end is that the voltage of this first power end and this second source end is average, and the output of this first bias voltage operational amplifier is coupled to adjustment end and this first bias voltage signal node of this first bias-variable resistance;

This second bias circuit comprises one second bias-variable resistance, one second bias transistor, one second bias voltage operational amplifier and a decline revolution rate controlling resistance; And

First end of this decline revolution rate controlling resistance is coupled to this first power end, second end of this decline revolution rate controlling resistance is coupled to the positive input terminal of this second bias voltage operational amplifier and first end of this second bias transistor, the voltage that the negative input end of this second bias voltage operational amplifier is coupled to a power end and this power end is that the voltage of this first power end and this second source end is average, second end of this second bias transistor is coupled to first end of this second bias-variable resistance, the gate of this second bias transistor is coupled to this first power end, second end of this second bias-variable resistance is coupled to this second source end, and the adjustment end of this second bias-variable resistance is coupled to output and this second bias voltage signal node of this second bias voltage operational amplifier;

Wherein, this first bias-variable resistance and this first bias transistor have identical in fact electrical characteristic with this first variable resistor and this first output transistor of this first turnover rate control circuit respectively, this second bias-variable resistance and this second bias transistor have identical in fact electrical characteristic with this second adjustable resistance and this second output transistor of this second turnover rate control circuit respectively, and this rising revolution rate controlling resistance has identical in fact impedance with this decline revolution rate controlling resistance.

10, output circuit according to claim 5 is characterized in that wherein said

First bias circuit comprises one first bias resistance, one first adjustment transistor, one first bias transistor, one first bias voltage operational amplifier and a rising revolution rate controlling resistance, and wherein this first bias resistance and this first adjustment transistor coupled in parallel form one first bias-variable resistance;

This first bias resistance, this first bias transistor and should rising revolution rate controlling resistance coupled in series and cross-over connection between this first power end and this second source end, the positive input terminal of this first bias voltage operational amplifier is coupled to the common points of this first bias transistor and this rising revolution rate controlling resistance, the voltage that the negative input end of this first bias voltage operational amplifier is coupled to a power end and this power end is that the voltage of this first power end and this second source end is average, and the output of this first bias voltage operational amplifier is coupled to this and first adjusts transistorized gate and this first bias voltage signal node;

This second bias circuit comprises one second bias resistance, one second adjustment transistor, one second bias transistor, one second bias voltage operational amplifier and a decline revolution rate controlling resistance, and wherein this second bias resistance and this second adjustment transistor coupled in parallel form one second bias-variable resistance; And

This decline revolution rate controlling resistance, this second bias transistor and this second bias resistance coupled in series and cross-over connection are between this first power end and this second source end, the positive input terminal of this second bias voltage operational amplifier is coupled to the common points of this decline revolution rate controlling resistance and this second bias transistor, the voltage that the negative input end of this second bias voltage operational amplifier is coupled to a power end and this power end is that the voltage of this first power end and this second source end is average, and the output of this second bias voltage operational amplifier is coupled to this and second adjusts transistorized gate and this second bias voltage signal node;

Wherein, this first bias-variable resistance and this first bias transistor have identical in fact electrical characteristic with this first variable resistor and this first output transistor of this first turnover rate control circuit respectively, this second bias-variable resistance and this second bias transistor have identical in fact electrical characteristic with this second adjustable resistance and this second output transistor of this second turnover rate control circuit respectively, and this rising revolution rate controlling resistance has identical in fact impedance with this decline revolution rate controlling resistance.

11, output circuit according to claim 4 is characterized in that wherein said

First variable resistor comprises one first oxide-semiconductor control transistors and one second oxide-semiconductor control transistors coupled in parallel, first end of this first oxide-semiconductor control transistors is coupled to first end and this first power end of this second oxide-semiconductor control transistors, second end of this first oxide-semiconductor control transistors is coupled to second end of this second oxide-semiconductor control transistors, gate and this first output transistor of this first oxide-semiconductor control transistors, and the gate of this second oxide-semiconductor control transistors is coupled to one first bias voltage signal node of this first bias circuit; And

This second adjustable resistance comprises one the 3rd oxide-semiconductor control transistors and one the 4th oxide-semiconductor control transistors coupled in parallel, first end of the 3rd oxide-semiconductor control transistors is coupled to first end of the 4th oxide-semiconductor control transistors, gate and this second output transistor of the 3rd oxide-semiconductor control transistors, second end of the 3rd oxide-semiconductor control transistors is coupled to second end and this second source end of the 4th oxide-semiconductor control transistors, and the gate of the 4th oxide-semiconductor control transistors is coupled to one second bias voltage signal node of this second bias circuit.

12, a kind of output circuit is characterized in that it comprises:

An one input node and an input complementary node;

One output node and an output complementary node;

One first output transistor and one second output transistor coupled in series;

One the 3rd output transistor and one the 4th output transistor coupled in series;

One first turnover rate control circuit is coupled between the common points of one first power end and this first output transistor and the 3rd output transistor, is that configuration is in order to provide variable resistance; And

One second turnover rate control circuit is coupled between the common points of a second source end and this second output transistor and the 4th output transistor, is that configuration is in order to provide variable resistance;

Wherein, this input node is coupled to the gate of this first output transistor and the gate of this second output transistor, this output node is coupled to the common points of this first output transistor and this second output transistor, this input complementary node is coupled to the gate of the 3rd output transistor and the gate of the 4th output transistor, and this output complementary node is coupled to the common points of the 3rd output transistor and the 4th output transistor.

13, output circuit according to claim 12 is characterized in that it more comprises:

One first output resistance is coupled to the common points of this output node and this first output transistor and this second output transistor; And

One second output resistance is coupled to the common points of this output complementary node and the 3rd output transistor and the 4th output transistor.

14, output circuit according to claim 12 is characterized in that more comprising at it:

One first electric capacity is coupled to the common points of this second source end and this first output transistor, the 3rd output transistor and this first turnover rate control circuit; And

One second electric capacity is coupled to the common points of this second source end and this second output transistor, the 4th output transistor and this second turnover rate control circuit.

15, output circuit according to claim 12 is characterized in that described therein

First turnover rate control circuit comprises one first variable resistor, and wherein this first variable-resistance resistance is the one first bias voltage signal of responding from one first bias circuit; And

This second turnover rate control circuit comprises a second adjustable resistance, and wherein the resistance of this second adjustable resistance is the one second bias voltage signal of responding from one second bias circuit.

16, output circuit according to claim 15 is characterized in that described therein

First variable resistor comprises one first resistance and one first oxide-semiconductor control transistors coupled in parallel, and wherein the gate of this first oxide-semiconductor control transistors is coupled to one first bias voltage signal node of this first bias circuit; And

This second adjustable resistance comprises one second resistance and one second oxide-semiconductor control transistors coupled in parallel, and wherein the gate of this second oxide-semiconductor control transistors is coupled to one second bias voltage signal node of this second bias circuit.

17, output circuit according to claim 16 is characterized in that described therein

First output transistor and this first oxide-semiconductor control transistors all are the PMOS transistors, and this second output transistor and this second oxide-semiconductor control transistors all are nmos pass transistors.

18, output circuit according to claim 16 is characterized in that described therein

First bias circuit comprises one first bias transistor and one second bias transistor coupled in series and cross-over connection between this first power end and this second source end, and this first bias voltage signal node is coupled to the gate of this first bias transistor, the gate of this second bias transistor and the common points of this first bias transistor and this second bias transistor;

This second bias circuit comprises one the 3rd bias transistor and one the 4th bias transistor coupled in series and cross-over connection between this first power end and this second source end, and this second bias voltage signal node is coupled to the gate of the 3rd bias transistor, the gate of the 4th bias transistor and the common points of the 3rd bias transistor and the 4th bias transistor; And

The electrical characteristic of the electrical characteristic of this first bias transistor and the 3rd bias transistor in fact all electrical characteristic with this first output transistor is identical, and the electrical characteristic of the electrical characteristic of this second bias transistor and the 4th bias transistor in fact all the electrical characteristic with this second output transistor is identical.

19, output circuit according to claim 12 is characterized in that described therein

First output transistor, this first oxide-semiconductor control transistors, this first bias transistor and the 3rd bias transistor all are the PMOS transistors, and this second output transistor, this second oxide-semiconductor control transistors, this second bias transistor and the 4th bias transistor all are nmos pass transistors.

20, output circuit according to claim 15 is characterized in that described therein

First bias circuit comprises one first bias-variable resistance, one first bias transistor, one first bias voltage operational amplifier and a rising revolution rate controlling resistance;

First end of this first bias-variable resistance is coupled to this first power end, second end of this first bias-variable resistance is coupled to first end of this first bias transistor, second end of this first bias transistor is coupled to the positive input terminal of this first bias voltage operational amplifier and first end that should rising revolution rate controlling resistance, second end of this rising revolution rate controlling resistance is coupled to this second source end, the gate of this first bias transistor is coupled to this second source end, the voltage that the negative input end of this first bias voltage operational amplifier is coupled to a power end and this power end is that the voltage of this first power end and this second source end is average, and the output of this first bias voltage operational amplifier is coupled to adjustment end and this first bias voltage signal node of this first bias-variable resistance;

This second bias circuit comprises one second bias-variable resistance, one second bias transistor, one second bias voltage operational amplifier and a decline revolution rate controlling resistance; And

First end of this decline revolution rate controlling resistance is coupled to this first power end, second end of this decline revolution rate controlling resistance is coupled to the positive input terminal of this second bias voltage operational amplifier and first end of this second bias transistor, the voltage that the negative input end of this second bias voltage operational amplifier is coupled to a power end and this power end is that the voltage of this first power end and this second source end is average, second end of this second bias transistor is coupled to first end of this second bias-variable resistance, the gate of this second bias transistor is coupled to this first power end, second end of this second bias-variable resistance is coupled to this second source end, and the adjustment end of this second bias-variable resistance is coupled to output and this second bias voltage signal node of this second bias voltage operational amplifier;

Wherein, this first bias-variable resistance and this first bias transistor have identical in fact electrical characteristic with this first variable resistor and this first output transistor of this first turnover rate control circuit respectively, this second bias-variable resistance and this second bias transistor have identical in fact electrical characteristic with this second adjustable resistance and this second output transistor of this second turnover rate control circuit respectively, and this rising revolution rate controlling resistance has identical in fact impedance with this decline revolution rate controlling resistance.

21, output circuit according to claim 16 is characterized in that described therein

First bias circuit comprises one first bias resistance, one first adjustment transistor, one first bias transistor, one first bias voltage operational amplifier and a rising revolution rate controlling resistance, and wherein this first bias resistance and this first adjustment transistor coupled in parallel form one first bias-variable resistance;

This first bias resistance, this first bias transistor and should rising revolution rate controlling resistance coupled in series and cross-over connection between this first power end and this second source end, the positive input terminal of this first bias voltage operational amplifier is coupled to the common points of this first bias transistor and this rising revolution rate controlling resistance, the voltage that the negative input end of this first bias voltage operational amplifier is coupled to a power end and this power end is that the voltage of this first power end and this second source end is average, and the output of this first bias voltage operational amplifier is coupled to this and first adjusts transistorized gate and this first bias voltage signal node;

This second bias circuit comprises one second bias resistance, one second adjustment transistor, one second bias transistor, one second bias voltage operational amplifier and a decline revolution rate controlling resistance, and wherein this second bias resistance and this second adjustment transistor coupled in parallel form one second bias-variable resistance; And

This decline revolution rate controlling resistance, this second bias transistor and this second bias resistance coupled in series and cross-over connection are between this first power end and this second source end, the positive input terminal of this second bias voltage operational amplifier is coupled to the common points of this decline revolution rate controlling resistance and this second bias transistor, the voltage that the negative input end of this second bias voltage operational amplifier is coupled to a power end and this power end is that the voltage of this first power end and this second source end is average, and the output of this second bias voltage operational amplifier is coupled to this and second adjusts transistorized gate and this second bias voltage signal node;

Wherein, this first bias-variable resistance and this first bias transistor have identical in fact electrical characteristic with this first variable resistor and this first output transistor of this first turnover rate control circuit respectively, this second bias-variable resistance and this second bias transistor have identical in fact electrical characteristic with this second adjustable resistance and this second output transistor of this second turnover rate control circuit respectively, and this rising revolution rate controlling resistance has identical in fact impedance with this decline revolution rate controlling resistance.

22, output circuit according to claim 15 is characterized in that described therein

This first variable resistor comprises one first oxide-semiconductor control transistors and one second oxide-semiconductor control transistors coupled in parallel, first end of this first oxide-semiconductor control transistors is coupled to first end and this first power end of this second oxide-semiconductor control transistors, second end of this first oxide-semiconductor control transistors is coupled to second end of this second oxide-semiconductor control transistors, gate and this first output transistor of this first oxide-semiconductor control transistors, and the gate of this second oxide-semiconductor control transistors is coupled to one first bias voltage signal node of this first bias circuit; And

This second adjustable resistance comprises one the 3rd oxide-semiconductor control transistors and one the 4th oxide-semiconductor control transistors coupled in parallel, first end of the 3rd oxide-semiconductor control transistors is coupled to first end of the 4th oxide-semiconductor control transistors, gate and this second output transistor of the 3rd oxide-semiconductor control transistors, second end of the 3rd oxide-semiconductor control transistors is coupled to second end and this second source end of the 4th oxide-semiconductor control transistors, and the gate of the 4th oxide-semiconductor control transistors is coupled to one second bias voltage signal node of this second bias circuit.

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