CN1808328A - Pipelined buffer clocked with different phases of a rotary clock - Google Patents

Abstract

Disclosed are a system and a method used for distributing involved clocks into one system. A frequency- locking loop is used to make a rotary traveling wave oscillator keep synchronous with a reference clock. A plurality of binary system waveform blocks are used to form a local clock for each module in the system. The local clocks are formed by the rotary traveling wave oscillator. Each binary system block is synchronous with the neighboring element, so that the phases of the formed local clocks are concerned with each other. The binary system block can include a counter which can be divided by N, a single-triggering moving point sequencer or a thermal insulation frequency divider. The frequency- locking loop can includes a charge pump or an up- sequence/ down- sequence counter and a switching capacitor array for tuning the rotary traveling wave oscillator.

Description

Pipelined buffer clocked

The cross reference of related application

The application's case is the part of the PCT/GB03/000719 international application of submission on February 14th, 2003; It requires the right of priority of GB0218834.0 that submits in the GB0212869.2 that submits in the GB0203605.1 that submitted on February 15th, 2002, on June 6th, 2002, the GB0214850.0 that on June 27th, 2002 submitted to, on August 14th, 2002 and the GB0225814.3 that submitted on November 6th, 2002.The theme of PCT/GB03/000719 international application is incorporated in this division by reference.

The cross reference of related application

The background material of this application case is in patent application case PCT/GB00/00175, and it all is incorporated herein by reference.

This application case is the part of PCT/GB00/00175.

Technical field

The present invention relates generally to the timing network, and more particularly relate to the purposes of rotary traveling wave oscillator (RTWO) in the timing network.

Background technology

Conventional timing network can't provide and spread all over total system, such as the distributed relevant clock of SIC (semiconductor integrated circuit).Relevant clock means and spreads all over clock that system distributes and have given frequency and phase relation each other.For example, suppose to come some part of timekeeping system with the frequency that equals master oscillator frequency fosc, and must come the timing other parts with the frequency that equals fosc/10.Must be with the part of the system of fosc/10 timing with phase alignment each other, so that the communication between these parts may not have metastability, described metastability requires synchronously again and causes time waste.Spread all over described system if a global synchronizing signal is distributed, it must navigate in the total system with the accurate timing of time lag with master oscillator frequency part so.In a big system, this is impossible.Therefore, need the clock that to be concerned with to be distributed in the system and method for the improvement that spreads all over total system.

Summary of the invention

The present invention is directed to above-mentioned needs.System according to an embodiment of the invention is that the relevant clock that is used to distribute spreads all over the timing network of the system of a plurality of modules.Described networking comprises: a rotary traveling wave oscillator, a frequency locking loop, a main waveform block and one or more less important binary waveform block.Described rotary traveling wave oscillator provides by being positioned at the plurality of interconnected loop that spreads all over described system, and each loop of wherein said rotary traveling wave oscillator provides a pair of opposite phasing clock at the tap position place.Described frequency locking loop receives the stabilized frequency source of importing from reference clock and is provided for the controlled output in loop of tuning rotary traveling wave oscillator frequency.Described main binary waveform block approximately is positioned at system's middle position.Described main waveform block has a pair of clock input that is connected to the rotary traveling wave oscillator and provides a pair of synchronous output and a local clock to one or more proximity modules.Described one or more less important binary waveform block is positioned at all places that spreads all over system.Wherein each less important binary waveform block has a pair of synchronous input and the input of a pair of clock that is connected to the rotary traveling wave oscillator.Synchronous output and described less important waveform block that the synchronous input of at least one less important binary waveform block is connected to main binary waveform block provide a pair of synchronous output and local clock to one or more proximity modules.

Method according to an embodiment of the invention is the method that is used to provide relevant clock to spread all over the system of a plurality of modules.Described method comprises: make a rotary traveling wave oscillator and a reference clock that comprises one or more interconnection loop synchronous; By using rotary traveling wave oscillator and binary waveform block to derive one or more local clock, make each module have at least one local clock; Make the binary waveform block synchronized with each other, relevant each other to force described local clock.

Frequency partition/pulse is latched/adiabatic system

This conceptual design framework (Rotary Clocking Architecture) when being used for making tropometer can be supported traditional low-speed clock network topology technology and allow the timing of the direct high speed low energy of RTWO to be embedded into to be used for newly-designed block simultaneously.

Also assisted and wherein required the integrated SOC design of clock frequency and clock phase for a long time.

The method that realizes low frequency division available energy " thermal insulation " clock from the RTWO with special waveform and phase characteristic has also been described.

Attention: in the text, suppose to exist in the built-in control program of VLSI device or other old wafer hardware that it can load and read various shift registers and data register---serial or parallel.The method of doing this as everyone knows and standardization.

Notion is with overclocking frequency distribution RTWO widely.This clock (as 10GHz) provides the inversion clock edge in each the 1/2 circulation 50pS (100pS circulation) of 10GHz clock (for example for).Clock is directly applied for many application (high speed ALU, SERDES I/O port) at full speed.Centrally-located FLL (frequency locking loop) is with main control system " overclocking " and better to phase-lock loop.

The present invention is a feature with (i) thick control (frequency division---numeral), (ii) medium control (switch capacitor---numeral) and (iii) smart control (variable reactor---simulate).

Implementing to compare advantage of the present invention with PLL comprises:

--more stable loop;

--low energy-reduce area;

--at a high speed;

--better stable (shake, time lag); With

--the phase locking between multifrequency.

Phase locking is provided and is operated under following principle by RTWO proper phase locking mechanism (2 classes: node locking (between wafer), postpone coupling link (in the wafer)): if frequency lock, phase locking is to make the synchronous simple thing of " outside indifference phase place " rotation wave so.

Use " overclocking " with not only produce frequency division but also generation be used for various application for reference clock and the random waveform of phase alignment, such as

--traditional uP (microprocessor) clock---is as pulse clock

--overall low-frequency clock (as, cache (Cache), the parallel bus of long-range)

The present invention

--allow to substitute initiatively " going time lag (deskew) " mechanism.

--digital controlled shifting to an earlier date/delay phasing (phasing).

---eliminate the cross-conduction current peak.

--any repetitive pattern---may be high/low cycle, classification (fractional) N.

--provide all the required features of high-end processor that comprise test clock etc.

--provide the high-speed phase that is used for SERDES (Serial/Deserial) and lock peripheral clock.

--from the local high speed timing that is used for ALU etc. of major clock.

Description of drawings

Figure 1A shows the general framework of one embodiment of the invention;

Figure 1B shows the structural drawing of one embodiment of the invention;

Fig. 2 A shows a division (divide) of being undertaken by the N counter that is connected to the rotary traveling wave oscillator;

Fig. 2 B shows the single transfer point sequencer that triggers that is connected to the rotary traveling wave oscillator;

Fig. 3 shows the special logic version of transfer point register;

Fig. 4 shows each enforcement of register shown in Fig. 3;

Fig. 5 shows a circuit, and it docks with the output of transfer point generator via impact damper shown in Figure 6, digitally to set the cycle of " the opening " and " pass " of exporting clock waveform according to 1/2 cycle of high resolution R TWO;

Fig. 6 shows the employed impact damper of Fig. 5 circuit;

Fig. 7 shows adiabatic frequency divider;

Fig. 8 shows the various waveforms that are used for Fig. 7 circuit;

Fig. 9 shows the charge pump that is used for the frequency locking loop;

Figure 10 shows the numerical frequency error detector;

Figure 11 shows inverter module;

Figure 12 shows strobe pulse unit (strobe cell);

Figure 13 shows the shift register cell with retentivity;

Figure 14 shows latch unit;

Figure 15 shows the cell layout that is used for single phase inverter;

Figure 16 shows the cell layout that is used for single switch capacitor; With

Figure 17 shows the switch capacitor unit.

Embodiment

Topology

Before be extensive use of and be positioned at the distributed component that is used for around the RTWO transmission line path that frequency control, sense of rotation depart from etc., such as the back of the body-back of the body phase inverter, switch capacitor, variable reactor etc. about the description of RTWO structure.

In this used, these parts (piece) became the modularization framework with the waveform generation assembly, and we are called " binary waveform block " (Binary Waveshaping Block) (BWB).

Described framework makes RTWO need not to change essential method promptly applicable to the employed VLSI of electric current widely synchronous timing method in current industry.

Directly use the RTWO ripple to have inherent advantages in the type 2 mutually non-overlapped the latching that method not exclusively thus realizes, and the mixing that is contemplated to the pure RTWO timing of New Parent and classification timing to use will be best compromise in the multifrequency environment.

Fig. 1 framework

Representative VLSI wafer is showed with RTWO transmission line and obvious phase inverter.

REFCLK input is used to make RTWO system and the external reference frequency precise synchronization that provides on the wafer on this pin.

--show phase locking " band synchronously " point in the left side.It has formerly been described in the application case and its permission realizes phase locking by hard lock between the RTWO wafer.(other method of PLL class aligning is not left in the basket as another solution).

Central authorities at wafer have showed two blocks: binary waveform block and frequency locking loop block.

BWB0

--it is main " the binary waveform block " of wafer.

--it provides Qn and many circulations of * Qn source of synchronising signal (further vide infra and Fig. 2).

FLL

The frequency locking loop.

This circuit is guaranteed the main RTWO frequency of operation of wafer by closed-loop control, so that it just is can be from several times of the input REF CLK of external system standard (as quartz crystal).

In fact, if the high what of the frequency of RTWO (REF_CLK xX) reduces up to it it accurately till the locking frequency by the control of variable reactor or switch capacitor so.

Hereinafter will further describe detailed operation.

Lack: PLL

In theory, use PLL and phase frequency comparator frequency and phase control can be arrived the external reference amount.In fact, especially when its advance enter and when crossing wafer then the phase place on REF_CLK exist a lot of uncertain, to such an extent as to it is useless as phase reference.

By using rigid line locking (formerly describing in the application case) or implying phase information by using, for example till data sampling synchronously, can reach the phase locking between RTWO wafer and outside phase place by edge that detects input NRZ data stream and the phase place (via variable reactor control) of regulating the RTWO ring.

Many times of overall situations, frequency-dividing clock

The purpose of this framework is to be created in the clock that frequency around all wafers and phase place are relative to each other.Main RTWO timing array has provided that the precise phase of institute between having a few concerns on owing to the wafer that is used for 360 degree phase places of the pulse combined mechanism on the transmission line.Referring to JSSC paper.

Wherein, many recurrence events treat synchronization (as, producing frequency is the clock of main RTWO frequency 1/10), not only need in many circulations, carry out the sequential state machines of ordering, and because this/the N clock should with on the wafer other/phase alignment of N clock, so must exist the global synchronizing signal of state synchronized of some hold mode machine so that its common experience state 0.

A tangible method is for deriving clock (derived clock) the distribution overall situation " synchronously " line to each around wafer---but this line need be designed to navigate on entire wafer with the accurate timing with main RTWO clock round-robin part time lag.This is the problem that and generation conventional H are set the same difficulty of clock, and infeasible.

Instead, when before forming the loop, finishing sequence, make each state machine in the BWB block send signal to its adjacent element.Therefore the distance of signaling is very short.In fact, each BWB sends signal to its adjacent element: it will make " loop " to become state 0 in next RTWO circulation (or 1/2 circulation), the BWB that is received with this as the order that becomes state 0 at its next RTWO clock edge, finally to guarantee all BWB state synchronized on the wafer.(energy consumption for this is very low--and frequency is only to be a pair of receiver gate circuit at each BWB place less than the Nx of RTWO frequency and load capacitance.)

The defective of the method be its entire wafer make its many recurrent states machine synchronously before, carry out the circulation of Nx (number of BWB) RTWO clock.

For alleviating this, may be from main BWB " fan-out " (fan-out) to drive 4 adjacent elements from each BWB.

The result of all these logics is to exist " overall situation ", anticipates promptly, and the wafer width sequence of available number of times (or RTWO circulation), it allows the logic rate of the sync response on entire wafer lower than fRTWO.

The BWB circuit details

From this function of the Qn of sequencer/state machine and * Qn output execution graph 1, and its on the embedding serial chain between the BWB block as seen.Qn and * Qn are the truths of the loop end-state in sequencer and replenish.

Fig. 2/D2 has showed the waveform of two possible sequencer state machines.Described machine can be simply have output logic with produce end-state (that is, and N-1) /the N counter, or be " single triggering (One-Hot) " a.k.a " transfer point " state machine, wherein end-state is sent out signal in definite output.

Fig. 2 a/D2 illustrated one have " last in, first out " input and " afterwards going out the advanced person " output /the N counter, it allows to make it synchronous by the previous/N counter in BWB, and allows its use to go out elder generation thereafter and then make the next one/N counter synchronisation among the BWB subsequently.

Just getting back to inside at described/N counter is before zero, after go out advanced counting and raise.Last in, first out for depositing input, and its forced counting device when logic high becomes counting 0 when it counts next time.

Sequence can be in order to produce random waveform.Under the simplest situation ,/N counter is a sequencer, and when giving its whole N time clock, it provides the output sequence of 0-＞1-＞0.

Random waveform

Can be by N state sequencer (" single scrambler that triggers " (one-hot encoder)) or " transfer point " of use and gating and output buffer coupling) make the clock waveform generator of more general purpose.

This and described/N counter have similar many circulations synchronized system and had before discussed.It uses * SYNC and SYNC input to import with * Qn and the Qn that receives from previous stage, and exports himself * Qn and Qn to next stage.

Attention: turn to the N clock synchronization synchronously, wherein have phase deviation in the circulation fixed according to the position of BWB block on the RTWO line.

Fig. 2 b/D2 shows " transfer point " structural drawing and the timing sequence based on sequencer.Main BWB (BWBO) is different with other BWB, and reason is that it produces the feedback of self via MUX from its output.

The selection of when microprocessor (on being connected to wafer or outside the wafer) MUX allows the variation in the enterprising line programization of sequence length if desired, so.

A kind of method of making this transfer point register is to use shift register elements.Shown in Fig. 3/D3, another kind of method is to use special logic.Illustrate that two " transfer point " generators obtain single coded signal that triggers true and additional on output Q0...Q9.5.This example provides the sequence of 20 (bit), and loads the RTWO line symmetrically, RTWO_A and RTWO_B.Described state is in advance in each 1/2 circulation (that is rotation) of RTWO clock signal.

Fig. 4/D4 shows and is used for the intraware of " transfer point " element of band of composition diagram 3.

* SYNC and SYNC are equal to the signal in graphic left side, and Qn and * Qn are equal to the signal Q9.5 and the * Q9.5 on right side.

Use the wave producer ratio/N counter of " transfer point " sequence to have more dirigibility.

Can use have with the resolution digital of 1/2RTWO clock period the logic high and the random waveform of logic low time that define.

Fig. 5/D5 shows a circuit, and it docks with the output of transfer point generator via impact damper shown in Fig. 6/D6, and output clock waveform (CLK_ARB) " is opened " and the time of " pass " to set according to the high-resolution digital ground in 1/2 cycle of RTWO.

" 1 " in the SET register is open at the CLK_ARB output of the described sequence in the transfer point sequence.Similarly, " 0 " in the RESET register disconnects the output in the moment described in the described sequence.CLK_ARB can each RTWO cycle maximum rate conversion once and once with the minimum rate conversion of each RTWO cycle/N sequence length, thereby provide frequency (twice conversion) scope of the fRTWO/10 of 20 sequencers.The dirigibility of CLK_ARB derives from programmability.

--can be by global sequence's numeral of set condition change place regulating frequency.

--can independently set logic high time (high time), logic low time (low time)---this helps pulse clock.

----the global sequence able to programme numeral at the beginning in logic high cycle and logic low cycle can individually be programmed for each clock in BWB--allows resolution of going time lag to arrive the %RTWO cycle able to programme (as, 50pS@10GHz RTWO frequency) effectively to go time lag.

--gating--may turn-off gated clock

--can produce strobe pulse and other specific nonstandard sync signal and it is with global synchronization.

For each BWB, can produce more than one CLK_ARB partly; In described situation, each independent clock that is produced is produced SET and RESET and buffer circuits again.The BWB sequence can be any needed length and decides according to needed minimum frequency.

Be not that all BWB need to have same sequence length (when the sequencer when long 20 chains long 10 sequencer, can use the OR door to be distributed in the SYNCH pulse of intermediate point).

When using BWB, can for using, tradition frequency reduce clock rate (clock rate), obtain and the very approaching approximate value of true single-phase timing.

The part of the waveform edge of (construction again) and RTWO ripple arrives synchronously arbitrarily.For having 360 degree, routine, the regular RTWO loop array of 2 rotations (each Rotate 180 degree) at edge that need be on RTWO, its on the loop farthest the highest level of the asynchronous degree between 2 (the relatively person that has come--phase difference of half rotation each other diagonally) promptly, differ 90 degree (circulation) at Foverclock.

A single-point that specifies on the RTWO is " phasing degree zero " point; To find: by using * CLK or CLK line, any other point can not surpass on phase error+/-90 degree (for example, move on to+95 degree points from-90, you can use other phase place and described+95 degree to become-85 degree).

At the 10GHz place, this is+/-25pS, representative suitably be in 10% typical time lag 1GHz on budget " empty single-phase " clock+/-2.5%.

Error is stable and computable, and can be by preventing any race condition to the increase time in minimum delay and being explained.The known fact of phase place makes that its shake than time lag random variation (jitter) is easier to handle.

And synchronized with each other, described internal wiring is from the one-level Qn output of supplying with next stage * SYNC SYNCH input in the serial chain mode by internal wiring (interwiring line) for BWB.

Controlled clock gating and orderly close-down relate to can not determine that Qn*Qn is from main BWB.

In the process opposite with initiating process, BWB will stop (because its SYNCH pulse stops) in turn.

Perhaps, indivedual BWB can change its sequence data, to allow to implement the variation of new waveform, phase place, frequency.

Velocity variations relates to new data is loaded in the SEQ_CTRL register, and it obtained upgrading before counting #0 or any other suitable count code.

After each sequence, the array stores that is used for different sequence datas waits to be written into (having prolonged sequence effectively).

BWB and sequencer also can be used for making special clock, for example, and synchronous exchange signal, strobe pulse etc.

The generation of adiabatic clock--Fig. 7/D7, Fig. 8/D8 (substituting of mechanism shown in Fig. 5 and Fig. 6)

Because when going ripple when closed path is advanced, electricity (capacitive character) and magnetic (inductive) energy re-use continuously, so RTWO signal conserve energy.When the RTWO loop was applied to the VLSI size, it tended to produce very high frequency.

For supporting traditional interface and clock frequency, before mentioned frequency partition (that is, dividing clock frequency) to produce another lower clock frequency for RTWO.

Very unfortunate, as described conventional frequency divider and impact damper were not adiabatic just now, that is, it is dissipation energy when driving load capacitance.

This part has been described the principle of adiabatic frequency division.Yet, may relate to other and select to reduce RTWO.

--formulate higher inductance value and reduce this circuit--increases load capacitance and reduces circuit

--a plurality of loops of " winding " RTWO circuit are to extend length of transmission line but keep girth around the zone.

The adiabatic frequency divider that this paper summarized provides another " reduction of speed " and selects.In the burst transmissions wire system such as RTWO, line current is charged to the distributed capacitor at " edge " that forward direction is advanced.Thereby can control described electric current comes the charging of other electric capacity and discharge with the frequency relevant with the major loop Frequency Synchronization and therefore produces low frequency.The RTWO line is " understanding " described difference not.

In practice, this is difficult to adopt other any effective means except that very modern (0.18u or littler) CMOS method to reach.

Employed principle is that 2 phase clocks of observed frequency F can be divided into (2*N) phase (referring to Fig. 8/D8) at frequency F/N place.A simplified example is that 2 phase 4GHz clocks are divided into 4 phase 2GHz clocks.

Table 1 is blocked operation during sequence

Counting	Count switchover operation during this circulation initial conversion, * is optional
		0	A-J、B-L、*A-M、*B-K
0.5	A-M、B-K、*A-L、*B-J
		1	A-L、B-J、*A-K、*B-M
1.5	A-&B-M、*A-J、*B-L

Switching is by " the single triggering " state machine control, and it is similar to the description that the BWB unit is carried out, but only is 4 state machines herein.

Optionally, above-mentioned transistor formerly steady state (SS) (peak level) is activated allowing transistor to have the opening time before next edge takes place, and this means that transistor opens when peace and quiet, to have lower loss.

The unit that is marked with " logic " is incorporated simple gate circuit into to reach the extra output gating of the * item needs in last table.If there is not described selection, one or more gate circuit that export 0 so, 0.5...1.5 only directly drives the nmos pass transistor that is used for quadrature output.

Employing orthogonal signal sequence does not have specific reasons (left side of Fig. 8/D8) and can produce any sequence of any number of phases.Only restriction is that each edge of (ideally) RTWO clock should all switch to identical electric capacity at every turn.

A kind of useful version is " the single triggering " clocking scheme of showing on the timing diagram right side.Although at the energy of " unlatching " ohmic loss I2R of MOSFET and RTWO transmission line conductors, these clock signals that produce at J, K, L, M can drive electric capacity adiabaticly,, are not subjected to the influence of CV2F energy that is.

In theory, can derive the switching transistor grid capacitance from any clock, so this can not cause energy dissipation adiabaticly.

The effective capacitance that is used for main RTWO line:

Because at any time, RTWO (differential ground) charges to two series capacitances, so the capacity load of each described/2 frequency output phases be C_ slow (represent the logic load capacitance), being used to of then presenting in the RTWO place differential capacitance of analyzing speed and impedance be C_ slowly/2.The RTWO line is operation as usual, do not discover (be positioned at the frequency divider that can be arbitrary number Anywhere of ring) at adiabatic frequency divider place and take place " phase-splitting "---it only drives electric capacity as usual.

The driving of localized capacitance load has been considered in above-mentioned explanation.

Perhaps or in addition, clock can drive other transmission line, for example drive " the single triggering " pulse clock to remote location.

In fact, J, K, L or M clock serve as the branch road on the RTWO heat input and require impedance matching (identical condition be suitable for makes electric capacity, that is, the RTWO line should be seen identical impedance in the various piece of sequence) for low reflected energy stream.

The reorganization of energy

Heterogeneous frequency-dividing clock is inherently two-way and can transmits energy between J, K, L, M and RTWOA, RTWO B along any direction.What is interesting is that " far-end " of JKLM tap transmission line can be by using in the JKLM at another BWB place phase point is recombinated go back to the another location of RTWO line.Sequence numeral global synchronization and will switching for Mosfet is proofreaied and correct regularly to send signal from arbitrary JKLM to the RTWO line.(impedance matching and timing Consideration are used).

Another purposes of the J that this paper showed, K, L, M phase place scheme is to make it synchronous with the 1/2F loop of 4 mutually between the loop (Tw0 is wrapped in periphery--alternative method) in 2 phase F RTWO loops.(energy can flow betwixt and can make it is synchronous together).

Sweep test

(showed the sweep test block among Figure 1B/D1) at the BWB structural drawing.Standard jtag boundary scan shift register system can with the overall serial data interface compatibility of being advised, with allow scanning chain type logic share identical DAT go into/go out, as the SCLK bus of other BWB assemblies.

FLL frequency locking loop

For making RTWO wafer array and its all shake, bandwidth and regional issue with PLL synchronous, each VLSI wafer only needs an independent FLL controller.

How the passive type transmission line link that previous application case has been described between the wafer can make that the same frequency RTWO on it is synchronous together.

If the frequency difference of several rings is very little, the relevant link of weak (promptly＞＞Z ring) between the wafer is pulled in two plates together so.

--it is remaining subject under discussion that the original frequency difference is diminished.

Frequency locking is a good method

Use the frequency locking loop and---by very simply installing that last preface/following preface counter is made---maybe can use the high precision charge pump circuit.

REF CLK can be from external low frequency F reference---and F int can be from RTWO clock/N;

--phase place is unimportant, so edge rate etc. postpones unimportantly, and you need not to attempt control phase, only F;

--use switch capacitor or variable reactor to control the RTWO frequency;

--use INNERMOST (Fig. 1/D1 middle position is showed) RTWO to encircle (farthest) and measure and lock the RTWO frequency apart from the periphery at place, frequency locking junction.

This ring will be independent of the frequency effect on the nonsynchronous signal that injects described distal loop more or less.

--along with the innermost ring of many RTWO wafer moves with same frequency, therefore relative phase (it rotates after all) definitely preferably not for the external world is easy to make its phase place and intrusion signal synchronous---will be owing to rotation loss of energy till synchronous fully.

Approaching more synchronous, energy loss is few more---preventive measure

Unless there are many links in--weak link is subjected to the influence of slippage---, otherwise RTWO must be very firm.

Attention: above-mentioned only with a frequency job---definite by the wafer transmission line turn-off time.---be fixing described frequency, also can use outside RTWO ampere-type device to adjust those lines---but make Total tune become thorny.

The FLL system detail

(in many possibility methods) two kinds of methods:

(1)--dual charge pump--pumps into electric current, and another pumps it.--calibration--drives two pumps with identical clock, and adjusts till no-output--need multiplexer (mux);

(2)--go up preface/following preface counter.

Reference: " Phaselock Loops for DC Motor Speed Control " Dana.F.Geiger, Wiley, 1981 pp v, 77-92 page or leaf.

The charge pump frequency controller of method 1 shown in Fig. 9/D9.

Purpose:

With the frequency lock of RTWO several times of external reference frequency;

Compare the proportional control signal of difference between two frequencies and output and the described frequency, the variable reactor (or switch capacitor) that is applied to the RTWO line with control is with the modulation rotational time, and so modulating frequency.

Non-phase-lock loop

/ N counter is that to be used for the RTWO frequency partition be that lower frequency is to be used to mate low speed external reference F.If under low frequency, carry out frequency ratio with relax serve as at full speed with reference to the distribution of unmanageable reference clock.

Phase inverter: IA, I1, IB, I2-CMOS phase inverter (Pch/Nch)--by power vd D power supply, 0V

Function:--in each circulation of F1 frequency (its RTWO frequency or its/N version frequency), the electric charge that equals C1*VDD is pumped among the current mirror P1.

--in each circulation of F2 frequency (with reference to the frequency of clk), the electric charge that equals C2*VDD is pumped among the current mirror P2.

When frequency equated, the current value of above-mentioned two electric currents (electric charge * frequency) equated (because C1=C2).

In this case, transistor P1, the P2 of coupling will force zero current to flow to the P2 drain electrode, and sustaining voltage " VARACTORV " is stable.

Frequency mismatch causes the mismatch of P1, P2 electric current, and " VARACTORV " in one direction with the proportional swing amplitude of the mismatch of frequency.This adjusts the voltage of variable reactor, and therefore adjusts the RTWO frequency so that the RTWO frequency retrieval is the frequency times over the low speed reference clock.

This is the description on the principle, and it can be applicable to other known in this technology charge pump solution.

In foregoing circuit, may calibrate by using MUX that F1 and F2 input are sent to identical REF clock.With this understanding, should not drift about from the VARACTORV output of VDD/2 volt deviation point.CAL h and CAL l are the phase inverters with modified threshold value, and whether described phase inverter can read to determine frequency comparator accurate by state machine.Can realize the inching (self-trimming) of self by many methods, as, change C1 or C2 capacitor (binary weighting) by using known switch-capacitor apparatus--or by drift current able to programme is injected in P1 or the P2 drain current.

Can expect that 0.1% degree of accuracy and this are enough to allow rigid line phase locking in (describing to some extent) on the passive type link of RTWO in patent application case more early.

The digital counter system of method 2 shown in Figure 10/D10

Reference: " Phaselock Loops for DC Motor Speed Control " Dana.F.Geiger, Wiley, 1981 ppv, 77-92 page or leaf.

Above the practical methods that a kind of DC motor speed that uses numeral to go up preface/following preface counter comparison frequency is controlled is summarized in the reference of being quoted.Control has provided than the more stable loop of phase/frequency detector system with edge stability as the method for the frequency of main loop variable.Operation is flat-footed.Design a binary counter with UP and DOWN clock.The UP clock is supplied with by frequency F1, and the DOWN clock is supplied with by F2.When frequency matching, counter obtains the clean zero increment of its count value or decrement and changes around described identical value.

Being added into DAC and control loop (controlling for the variable reactor of RTWO frequency in this case) forces counter to be shaken near 0 value.

Use 8 digit counters of 2 ' s complement code symbol provide with DAC proportional+127 to-128 signals are in output current, directly or via analogue integrator to drive VARACTORV.

The variable reactor inching can reach+/-20% frequency change, but use switch capacitor can reach bigger tuning range (referring to Figure 16/D16).Being added into digital comparator block sum counter 2 can work alone at variable reactor and it is replenished when being not enough to reach frequency locking.The operation of counter 2 has been controlled and has been distributed in wafer switch capacitor array on every side--and its value is distributed in all BWB blocks of use shift register scheme.

The design of binary comparator makes no matter when error counter (counter 1) exports (out), and the increment of counter 2 or decrement are all respectively greater than 8 or-8 (selecting arbitrarily).Frequency is in the variable reactor fine setting but this selection is increased to the greater or lesser binary weighted capacitance of RTWO line controls in the scope in complete closed loop.

Figure 11/D11 shows the component detail (referring to following description) of related block in entire article widely to Figure 16/D16.

Listed files

TurboCad：

Hier0.tcw--main structure figure

Hier2.tcw--is used for digitally setting " opening " time of (nonadiabatic) clock generator and the mechanism of " pass " time (to supply to impact damper) arbitrarily

The X circuit:

The assembly of the adiabatic 4 phase generators of D7 adiab_l sch.ps--(also can referring to adiab l.sda)

Buffer block.ps--has the nonadiabatic cmos buffer device of independent input with the control crossing condition

D9 chargepump fcomp.ps--charge pump frequency comparative approach

Preface on the D10 counter fcomp.ps--frequency ratio numeral/following preface counter method

The method of D2, a D5 moving spot reg.ps--making " transfer point " register

The expansion of the basic transfer point element of D3 spotmove elem.ps--XA.ps

D11--switches size inverter module (digital controlled)

D12--strobe pulse unit (not having to be used for producing automatically strobe pulse under the situation of SCLK)

D13--shift register (one)

D14--latch unit (being used to keep having the shift register value of strobe pulse)

D15--is used for the full unit (back of the body-back of the body (back-back)) of digital size RTWO inverter module

D16--is used for the full unit of digital controlled switching RTWO capacitor

D17-switch capacitor (one)

Staroffice：

The 4 possible phase clock bursts that D7 adiab_l.sda--can produce adiabaticly

Fdiv_l.sda-/N counter block and the " pattern that moves

Though extremely described the present invention in detail with reference to some preferred version of the present invention, other version also is possible.Therefore, spirit of claims above and category should not be defined in the description of the preferred version that this paper is contained.

Claims (23)

1. the relevant clock that is used for distributing spreads all over a timing network with system of a plurality of modules, and described network comprises:

By being positioned at the rotary traveling wave oscillator that the plurality of interconnected loop that spreads all over described system provides, each loop of described rotary traveling wave oscillator provides a pair of opposite phasing clock at a tap position;

A frequency locking loop, it receives one from the stabilized frequency source of a reference clock input and the controlled output in loop of a described frequency that is used for tuning described rotary traveling wave oscillator is provided;

A main binary waveform block that is positioned at the about middle position of described system, described main binary waveform block have a pair of clock input that is connected to described rotary traveling wave oscillator and provide a pair of synchronous output and a local clock to one or more proximity modules; With

One or more less important binary waveform block, it spreads all over each position of described system, the less important binary waveform block of wherein each has a pair of synchronous input and the input of a pair of clock that is connected to described rotary traveling wave oscillator, the described synchronous input of at least one described less important binary waveform block is connected to the described synchronous output of described main binary waveform block, and described less important waveform block provides a pair of synchronous output and local clock to one or more proximity modules.

2. timing network according to claim 1, wherein said frequency locking loop is by using the described frequency of a described rotary traveling wave oscillator of varactor tuning.

3. timing network according to claim 1, wherein said frequency locking Hui Lu Tong Over uses the described frequency of the tuning described rotary traveling wave oscillator of a plurality of switch capacitors.

4. timing network according to claim 1,

Wherein has delivery time of a ripple on the described loop of foundation and fixed frequency at the described opposite phasing clock on the loop; And

Wherein said frequency locking loop comprises the charge pump and the described reference clock that receive a tap of described rotary traveling wave oscillator, and the proportional control signal of difference between the described frequency of the described frequency of and described oscillator and described reference clock is provided.

5. timing network according to claim 4, wherein said frequency locking loop comprise the variable reactor of the described frequency of a described rotary traveling wave oscillator of control, and described variable reactor comes tuning by described control signal.

6. timing network according to claim 1, wherein said frequency locking loop comprises:

Go up preface/following preface counter for one, it has second the importing an of tap that first input that is used for receiving described reference clock and are used for receiving described rotary traveling wave oscillator, and has a plurality of outputs of the proportional numerical frequency error signal of difference between the described frequency of described frequency that one and described oscillator are provided and described reference clock; With

A digital analog converter, it is used for converting described digital error signal to a simulating signal.

7. timing network according to claim 6, wherein said frequency locking loop comprise the variable reactor of the described frequency of a described rotary traveling wave oscillator of control, and described variable reactor comes tuning by described simulating signal.

8. timing network according to claim 7, wherein said frequency locking loop comprises:

A pair of comparer, when its described output that is used for detecting described frequency error counter is greater than or less than a predetermined constant;

Another has the last preface/following preface counter of a plurality of outputs, when the described output of preface on the described frequency error/following preface counter during greater than described predetermined constant, its binary value reduces, and when described output during less than described predetermined constant, its binary value increase; With

An array of capacitors that is used for tuning described rotary traveling wave oscillator, described array comprises that reception is connected to a plurality of switchs of described rotary traveling wave oscillator from the output of preface on other/following preface counter and with each capacitor, and described a plurality of outputs of other counters determine which capacitor of described array is connected to described rotary traveling wave oscillator.

9. timing network according to claim 1, wherein said less important binary waveform block only receives the synchronous input from four other less important binary waveform blocks.

10. timing network according to claim 1, wherein said binary waveform circuit comprises a counter divided by N.

11. timing network according to claim 1, wherein said binary waveform circuit comprise single transfer point sequencer that triggers.

12. timing network according to claim 1, one of them binary waveform circuit comprises an adiabatic frequency divider.

13. timing network according to claim 1, one of them binary waveform circuit comprise a single transfer point sequencer and the adiabatic frequency divider of triggering.

14. one kind is used to provide relevant clock and spreads all over a method with system of a plurality of modules, described method comprises:

Make a rotary traveling wave oscillator and a reference clock that comprises one or more interconnection loop synchronous;

Use described rotary traveling wave oscillator and binary waveform block to derive one or more local clock, so that each described module has at least one local clock; With

Make described binary waveform block synchronized with each other to force described local clock relevant each other.

15. the method that is used to provide relevant clock according to claim 14 is wherein carried out the synchronous of a reference clock and a rotary traveling wave oscillator by following steps:

The described frequency of more described rotary traveling wave oscillator and the described frequency of described reference clock,

Determine between described two frequencies difference and

Come tuning described rotary traveling wave oscillator based on described difference.

16. the method that is used to provide relevant clock according to claim 15 is wherein by using a charge pump to carry out the described frequency of described rotary traveling wave oscillator and the comparison of described frequency and the determining of described difference of described reference clock.

17. the method that is used to provide relevant clock according to claim 15 is wherein by using a last preface/following preface counter to carry out the described frequency of described rotary traveling wave oscillator and the comparison of described frequency and the determining of described difference of described reference clock.

18. the method that is used to provide relevant clock according to claim 14 is wherein carried out the tuning of described traveling wave oscillation device by controlling a variable reactor that is connected to described rotary traveling wave oscillator.

19. the method that is used to provide relevant clock according to claim 14 is wherein carried out the tuning of described traveling wave oscillation device by controlling a switch capacitor array that is connected to described rotary traveling wave oscillator.

20. the method that is used to provide relevant clock according to claim 14, thereby wherein by using one to synthesize the derivation that described local clock carries out one or more local clock divided by the N counter.

21. the method that is used to provide relevant clock according to claim 14, thereby wherein by using single transfer point sequencer that triggers to synthesize the derivation that described local clock carries out one or more local clock.

22. the method that is used to provide relevant clock according to claim 14, thereby wherein by using an adiabatic frequency divider to synthesize the derivation that described local clock carries out one or more local clock.

23. the method that is used to provide relevant clock according to claim 14, thereby wherein by using an adiabatic frequency divider and single transfer point sequencer that triggers to synthesize the derivation that described local clock carries out one or more local clock.

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