CN1804708A - Display device and pixel testing method thereof - Google Patents

Abstract

The display device has a display panel. The display panel comprises a plurality of IC pin terminals, a plurality of data lines, a selector, a plurality of switches and a test terminal. The IC pin terminal is coupled with a plurality of data lines through a selector. The data lines are electrically connected with a corresponding pixel circuit respectively. The plurality of IC pin terminals are respectively coupled to the testing terminal through the corresponding switches. The switches are sequentially turned on to sequentially transmit a voltage to the corresponding pixel circuits through the test terminal.

Description

Display device and pixel testing method thereof

technical field

The invention relates to a liquid crystal display device, in particular to a test structure of a liquid crystal display panel.

Background technique

Please refer to FIG. 1 , which is a schematic diagram of a test structure of a conventional liquid crystal display panel. The liquid crystal display panel 100 has a plurality of data lines DL(1)˜DL(N) and a plurality of pixel circuits P, where N is a positive integer. Corresponding to the number of data lines DL(1)-DL(N), the liquid crystal display panel 100 has a corresponding number of test pads TP(1)-TP(N) on the lower glass substrate 102 for testing multiple Pixel circuit P. For example, if there are 2048 data lines DL( 1 )˜DL( 2048 ), then the display panel 100 also has 2048 test terminals TP( 1 )˜TP( 2048 ). These test terminals TP(1)-TP(2048) are used in the manufacturing process of the liquid crystal display panel 100, for example, when the lower glass substrate 102 is manufactured but the liquid crystal has not yet been filled and the upper glass substrate has not been assembled (array section process ) for receiving the pixel voltage to test whether each pixel circuit P is normal. That is, the pixel voltage is sequentially transmitted to the corresponding pixel circuit P through the 2048 test terminals TP(1)~TP(2048) and the 2048 data lines DL(1)~DL(2048), and then through the 2048 test terminals The test terminals TP ( 1 )˜TP ( 2048 ) measure the voltage level stored in each pixel circuit P to detect whether the function of the pixel circuit P is normal.

However, although the above method can clearly detect whether the function of each pixel circuit P is normal, it has the problems of high cost and difficulty in manufacturing. In other words, these problems are that in the case of higher resolution, the number of test terminals TP corresponding to the data lines DL will increase significantly. A large number of test terminals TP will increase the manufacturing cost of the lower glass substrate 102, and because the density of the test terminals TP is very high, there will not be enough space for the test probes to be inserted into the test terminals or there is not enough space to configure such a large number The test terminal TP is on the lower glass substrate 102 .

Based on the considerations of cost and manufacturing difficulty mentioned above, in fact, the number of test terminals of a traditional display panel does not correspond to the number of data lines in a one-to-one manner, but a method in which some data lines share one test terminal. For example, three or six data lines share one test terminal, so as to reduce the number of test terminals configured on the liquid crystal display panel. However, this structure cannot accurately detect whether each pixel circuit is working normally when the lower glass substrate is fabricated (that is, the liquid crystal has not been poured and the upper glass substrate has not been assembled). Such a structure can only know that among the multiple data lines corresponding to a certain test terminal, at least one pixel circuit failure among the pixels coupled thereto is faulty.

Therefore, how to accurately detect the function of the pixel circuit when the under-glass substrate is manufactured and at the same time solve the problem of difficult testing or configuration caused by the high density of test terminals is a problem that the panel industry needs to solve at present.

Contents of the invention

In view of this, the purpose of the present invention is to provide a test structure of a display panel to solve the problems of cost, manufacturing difficulty and inability to accurately detect whether each pixel circuit is working normally.

According to the object of the present invention, a display device is proposed. The display device includes a plurality of first signal lines, a plurality of second signal lines, a first group of main thin film transistors, a second group of main thin film transistors, a test terminal, a first auxiliary thin film transistor and a second auxiliary thin film transistor. The multiple first signal lines are respectively electrically connected to a corresponding pixel circuit. The plurality of second signal lines are respectively electrically connected to a corresponding pixel circuit. The first group of main thin film transistors has a first main thin film transistor and a second main thin film transistor. The first main thin film transistor and the second main thin film transistor respectively have a first terminal, a second terminal and a control terminal. The second group of main thin film transistors has another first main thin film transistor and another second main thin film transistor. The other first main thin film transistor and the other second main thin film transistor also have a first terminal, a second terminal and a control terminal respectively. Wherein the first ends of the first main thin film transistors are electrically connected to the first signal lines, and the first ends of the second main thin film transistors are electrically connected to the second signal lines. The test terminal is used for receiving the power signal required to drive the pixel circuits, and outputting the voltage levels stored in the pixel circuits.

The first auxiliary thin film transistor has a first terminal, a second terminal and a control terminal. Wherein the first end of the first auxiliary thin film transistor is coupled to the second end of the first group of main thin film transistors. The second auxiliary thin film transistor has a first terminal, a second terminal and a control terminal. Wherein the first end of the second auxiliary thin film transistor is coupled to the second end of the second group of main thin film transistors. Both the second ends of the first auxiliary thin film transistor and the second auxiliary thin film transistor are coupled to the testing end, and the control ends of the first auxiliary thin film transistor and the second auxiliary thin film transistor respectively receive a corresponding auxiliary control signal. The control terminals of the first main TFTs all receive a main control signal, and the control terminals of the second main TFTs receive another main control signal. When the main control signal is enabled, the auxiliary control signals are enabled sequentially to turn on the first auxiliary thin film transistor and the second auxiliary thin film transistor sequentially. Similarly, when another main control signal is enabled, these auxiliary control signals are enabled sequentially to turn on the first auxiliary thin film transistor and the second auxiliary thin film transistor sequentially.

In order to make the above-mentioned purpose, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and is described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a test structure of a conventional liquid crystal display panel.

FIG. 2 is a schematic diagram of the test structure of the display device of the present invention.

FIG. 3 is a timing diagram of control signals of the main thin film transistor and the auxiliary thin film transistor.

FIG. 4 is a schematic diagram of another test structure of the display device of the present invention.

Description of reference symbols

100: display panel

102: Substrate under glass

DL: data line

P: pixel circuit

TP: test terminal

200: display device

202: Selector

204: Substrate under glass

P(1)～P(6): Pixels

L ₁ (1~4), L ₂ (1~4), L ₃ (1~4), L ₄ (1~4), L ₅ (1~4), L ₆ (1~4): signal line

TFT ₁ (1~4), TFT ₂ (1~4), TFT ₃ (1~4), TFT ₄ (1~4), TFT ₅ (1~4), TFT ₆ (1~4): main film transistor

S1, S2, S3, S4: Auxiliary thin film transistors

TP: test terminal

I(1), I(2), I(3), I(4): IC pin terminals

Detailed ways

The invention provides a test structure of a display panel. The test structure of the display panel can correctly detect whether the function of each pixel circuit is normal when the glass lower substrate is manufactured, and can also solve the problems of cost and difficulty of traditional manufacturing test structures.

Please refer to FIG. 2 , which is a schematic diagram of a test structure of the display device of the present invention. The display device 200 is, for example, a liquid crystal display, which has a liquid crystal display panel (not shown). The liquid crystal display panel includes, for example, six signal lines L, six pixel circuits P(1)-P(6), a selector 202, a test terminal TP, two IC pin terminals I(1) and I(2), A first auxiliary thin film transistor S ₁ , a second auxiliary thin film transistor S ₂ and a glass lower substrate 204 . The six signal lines L are two first signal lines L ₁ (1) and L ₁ (2), two second signal lines L ₂ (1) and L ₂ (2), two third signal lines L ₃ (1) and L ₃ (2). The selector 202 is composed of six switches, such as two first main thin film transistors TFT ₁ (1) and TFT ₁ (2), two second main thin film transistors TFT ₂ (1) and TFT ₂ (2) , two third main thin film transistors TFT ₃ (1) and TFT ₃ (2).

Each signal line L is a data line and is disposed on the lower glass substrate 204 . In FIG. 2 , each signal line L is shown as an example of being coupled to a pixel circuit P respectively. Each signal line L is coupled to the corresponding IC pin terminal I through a main thin film transistor TFT, so as to receive from the IC pin terminal I the pixel voltage VP output from the data driving integrated circuit (not shown), that is, the IC The pin terminals I( 1 ) and I( 2 ) are used to receive IC pins of the data-driven integrated circuit. As shown in FIG. 2, the two first signal lines L ₁ (1) and L ₁ (2) are respectively electrically connected to the first terminals X1 of the corresponding two first main thin film transistors TFT ₁ (1) and TFT ₁ (2). . The two second signal lines L ₂ (1) and L ₂ (2) are also electrically connected to the first terminals X1 of the corresponding two second main thin film transistors TFT ₂ ( 1 ) and TFT ₂ ( 2 ). The two third signal lines L ₃ (1) and L ₃ (2) are also electrically connected to the first terminals X1 of the corresponding two third main thin film transistors TFT ₃ ( 1 ) and TFT ₃ ( 2 ). The gates G of the two first main thin film transistors TFT ₁ (1) and TFT ₁ (2) both receive a first main control signal C(1). The gates G of the two second main thin film transistors TFT ₂ ( 1 ) and TFT ₂ ( 2 ) both receive a second main control signal C ( 2 ). The gates G of the two third main thin film transistors TFT ₃ ( 1 ) and TFT ₃ ( 2 ) both receive a third main control signal C ( 3 ). The second terminals X2 of the three main thin film transistors TFT ₁ (1), TFT ₂ (1) and TFT ₃ (1) are all coupled to a first IC pin terminal I (1), and the other three main thin film transistors The second terminals X2 of TFT ₁ (2), TFT ₂ (2) and TFT ₃ (2) are all coupled to a second IC pin terminal I(2).

The first terminal Y1 of the first auxiliary thin film transistor _S1 is coupled to the first IC pin terminal I(1). The second terminal Y2 of the first auxiliary thin film transistor _S1 is coupled to the testing terminal TP. The gate G of the first auxiliary thin film transistor _S1 receives an auxiliary control signal SWT(1). In contrast, the first terminal Y1 of the second auxiliary thin film transistor _S2 is coupled to the second IC pin terminal I(2). The second terminal Y2 of the second auxiliary thin film transistor _S2 is coupled to the testing terminal TP. The gate G of the second auxiliary thin film transistor _S2 receives an auxiliary control signal SWT(2).

It is further described how the present invention can correctly detect whether the function of each pixel circuit P is normal, and can also simultaneously solve the problems of cost and difficulty of manufacturing the test structure of the traditional liquid crystal display panel. Firstly, the selector 202 of the display device 200 can reduce the number of data driving units in the data driving integrated circuit, so as to effectively reduce the cost of the data driving integrated circuit. The display device 200 with the structure of the selector 202 will have a plurality of data lines L corresponding to one IC pin terminal I, for example, three signal lines L1(1), L2(1) and L3(1) are all coupled to the IC Pin terminal I(1). Therefore, if each IC pin terminal 1 corresponds to a test terminal in a one-to-one manner, the number of test terminals can indeed be reduced, but the number of test terminals disposed on the glass lower substrate 204 cannot be greatly reduced. Therefore, the present invention divides a plurality of IC output pads into arrays through another selector. For example, as shown in FIG. 2, the two IC pin terminals I(1) and I(2) are divided into one group, that is, the two IC pin terminals I(1) and I(2) are connected by two auxiliary thin film transistors S ₁ and _S2 are coupled to a test terminal TP. In this way, one test terminal TP can also be used to test the pixel circuits P on more data lines L, which can greatly reduce the number of test terminals TP disposed on the lower glass substrate 204 . For example, as shown in FIG. 2 , the test terminal TP can be used to test six pixel circuits P( 1 )˜P( 6 ) on six data lines.

Please refer to FIG. 3 , which is a timing diagram of control signals of the main thin film transistor and the auxiliary thin film transistor. When the six pixel circuits P(1)-P(6) in the same column receive the scan signal scan, the main control signals C(1), C(2) and C(3) are sequentially enabled to make the corresponding main control signals The thin film transistor TFT is turned on. When each main control signal C is enabled, the two auxiliary control signals SWT(1) and SWT(2) are sequentially enabled during each enable period of the main control signal C so that there is only one pixel at a time The circuit P receives the pixel voltage transmitted from the test terminal TP. Further, for example, in the period T0 during which the first main control signal C( 1 ) is enabled, the first auxiliary control signal SWT( 1 ) is enabled first. During the period T1 when the first auxiliary control signal SWT( 1 ) is enabled, the test terminal TP receives a pixel voltage VP through a probe, for example. The pixel voltage VP is transmitted to the first pixel circuit P(1) through the first auxiliary thin film transistor _S1 and the first main thin film transistor _TFT1 (1). Then, in the period T2 during which the first auxiliary control signal SWT(1) is disabled and the second auxiliary control signal SWT(2) is enabled, the pixel voltage VP received by the test terminal TP passes through The second auxiliary thin film transistor S ₂ and the first main thin film transistor TFT ₁ ( 2 ) are transmitted to the fourth pixel circuit P ( 4 ). Similarly, the manner of transmitting the pixel voltage VP to the pixel circuits P( 2 ), P( 3 ), P( 5 ) and P( 6 ) respectively will not be further described.

Next, when measuring the pixel voltage stored in each pixel circuit P(1)-P(6), the selector 202 and the two auxiliary thin film transistors _S1 and _S2 are also controlled according to the timing shown in FIG. 3 . After each pixel circuit P(1)-P(6) receives the pixel voltage VP, the voltage stored in each pixel circuit P(1)-P(6) must be measured through the test terminal TP. Is the level correct. Similarly, when each main control signal C is enabled, the two auxiliary control signals SWT(1) and SWT(2) are sequentially enabled during each enable cycle of the main control signal C so that only A pixel circuit P outputs its stored voltage level to the test terminal TP. For example, in the enabling period T3 of the second main control signal C(2), the two auxiliary control signals SWT(1) and SWT(2) are respectively enabled in a period T4 and a period T5. During the period T4, the test terminal TP receives the voltage level stored in the second pixel circuit P(2) through the turned-on second main thin film transistor _TFT2 (1) and the first auxiliary thin film transistor _S1 . Then in the period T5, the test terminal TP receives the voltage level stored in the fifth pixel circuit P(5) through the turned-on second main thin film transistor _TFT2 (2) and the second auxiliary thin film transistor _S2 . Similarly, the methods of measuring other pixel circuits P( 1 ), P( 3 ), P( 5 ) and P( 6 ) will not be described again. In this way, only the voltage level stored in one pixel circuit P is measured within a period of time.

To sum up, the test structure of the display panel disclosed in the above-mentioned embodiments of the present invention can correctly detect the Whether the function of each pixel circuit is normal. In other words, for the liquid crystal display production process, it is possible to screen out problematic pixel circuits in the front-stage process (array stage), which will definitely improve the production efficiency of the liquid crystal display. Moreover, the present invention can also greatly reduce the number of test terminals arranged on the glass lower substrate, so as to solve the problems of cost and difficulty in manufacturing test structures of traditional liquid crystal display panels.

In addition, the above-mentioned embodiment is an example where one IC pin corresponds to three data lines and two IC pins correspond to one test terminal TP, but one IC pin corresponds to six data lines and one test terminal TP Take four IC pin terminals as an example. Please refer to FIG. 4 , which is a schematic diagram of another test structure of the display device of the present invention. The lower glass substrate 204 forms twenty-four signal lines L, a selector 202, a test terminal TP, four IC pin terminals I(1), I(2), I(3) and I(4), a A first auxiliary thin film transistor S ₁ , a second auxiliary thin film transistor S ₂ , a third auxiliary thin film transistor S ₃ and a fourth auxiliary thin film transistor S ₄ . Wherein, when each of the above-mentioned main control signals C is enabled, the four auxiliary control signals SWT(1), SWT(2), SWT(3) and SWT(4) are in accordance with each enable period of the main control signal C. The sequence can be enabled so that only one pixel circuit is electrically connected to the test terminal TP at a time.

Wherein, when the upper display device 200 is in normal operation, the voltage level of the auxiliary control signal SWT turns off the auxiliary thin film transistors S, so that the data driving integrated circuit can normally drive the pixel circuit through the main thin film transistors.

In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the present invention. Movement and retouching, so the protection scope of the present invention shall be determined by the claims of the present invention.

Claims (14)

1. A display device, comprising: A plurality of first signal lines are respectively electrically connected to a corresponding pixel circuit; A plurality of second signal lines are respectively electrically connected to a corresponding pixel circuit; A first group of main thin film transistors has a first main thin film transistor and a second main thin film transistor, which respectively have a first terminal, a second terminal and a control terminal; A second group of main thin film transistors has another first main thin film transistor and another second main thin film transistor, which respectively have a first terminal, a second terminal and a control terminal, wherein the first main thin film transistor The first end of the second main thin film transistor is electrically connected to the first signal line, and the first end of the second main thin film transistor is electrically connected to the second signal line; a test terminal, used to receive the power signal required to drive the pixel circuit, and output the voltage level stored in the pixel circuit; a first auxiliary thin film transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first auxiliary thin film transistor is coupled to the second terminal of the first set of main thin film transistors; and A second auxiliary thin film transistor has a first end, a second end and a control end, wherein the first end of the second auxiliary thin film transistor is coupled to the second end of the second set of main thin film transistors, and the first end Second terminals of an auxiliary thin film transistor and the second auxiliary thin film transistor are both coupled to the test terminal, and control terminals of the first auxiliary thin film transistor and the second auxiliary thin film transistor respectively receive a corresponding auxiliary control signal. 2. The display device as claimed in claim 1, wherein the control terminals of the first main thin film transistors both receive a main control signal, and the control terminals of the second main thin film transistors receive another main control signal. 3. The display device according to claim 2, wherein the first main thin film transistor is turned on when the main control signal is enabled, and the second main thin film transistor is turned on when the other main control signal is enabled. Pass. 4. The display device as claimed in claim 2, wherein when the main control signal is enabled, the auxiliary control signals are enabled sequentially to turn on the first auxiliary thin film transistor and the second auxiliary thin film transistor sequentially. 5. The display device as claimed in claim 4, wherein when the other main control signal is enabled, the auxiliary control signals are sequentially enabled so that the first auxiliary thin film transistor and the second auxiliary thin film transistor are sequentially turned on. Pass. 6. The display device according to claim 1, further comprising a data driving integrated circuit, electrically connected to the second end of the first group of main thin film transistors and the second group of main thin film transistors, for driving the pixel circuit , wherein when the data driving integrated circuit drives the pixel circuit, the first auxiliary thin film transistor and the second auxiliary thin film transistor are turned off. 7. The display device according to claim 1, wherein the pixel circuit, the first signal line, the second signal line, the first group of main thin film transistors, the second group of main thin film transistors, the second An auxiliary thin film transistor, the second auxiliary thin film transistor and the test terminal are formed on a glass substrate. 8. A pixel testing method for a display panel, the display panel comprising a first group of main thin film transistors having a first main thin film transistor and a second main thin film transistor, and a first group of main thin film transistors having another first main thin film transistor A second group of main thin film transistors, a first auxiliary thin film transistor, a second auxiliary thin film transistor and a test terminal of another second main thin film transistor, the first end of the first main thin film transistor is respectively connected to a corresponding The first signal lines are electrically connected, the first ends of the second main thin film transistors are respectively electrically connected to a corresponding second signal line, and the first signal lines are respectively electrically connected to a corresponding first pixel circuit, the The second signal lines are respectively electrically connected to a corresponding second pixel circuit, the first end of the first auxiliary thin film transistor is coupled to the second end of the first group of main thin film transistors, and the first end of the second auxiliary thin film transistor The end is coupled to the second end of the second group of main thin film transistors, the second end of the first auxiliary thin film transistor and the second auxiliary thin film transistor are both coupled to the test end, and the pixel testing method includes: turning on the two first main thin film transistors at the same time; providing a first pixel voltage to the test terminal; sequentially turning on the first auxiliary thin film transistor and the second auxiliary thin film transistor to sequentially transmit the first pixel voltage to the corresponding first signal line; turning on the two second main thin film transistors at the same time; providing a second pixel voltage to the test terminal; and The first auxiliary thin film transistor and the second auxiliary thin film transistor are sequentially turned on to sequentially transmit the second pixel voltage to the corresponding second signal line. 9. The pixel testing method according to claim 8, further comprising separately transmitting the first pixel voltage to the corresponding first pixel circuit through the first signal line, and respectively transmitting the first pixel voltage to the corresponding first pixel circuit through the second signal line. ground and transmit the second pixel voltage to the corresponding second pixel circuit. 10. The pixel testing method according to claim 9, further comprising measuring voltage levels output by the first pixel circuit and the second pixel circuit on the test terminal. 11. The pixel testing method according to claim 10, wherein the step of measuring the voltage level output by the first pixel circuit on the testing terminal comprises: turning on the two first main thin film transistors at the same time; The first auxiliary thin film transistor and the second auxiliary thin film transistor are sequentially turned on, so as to respectively measure voltage levels stored in the first pixel circuit on the test terminal. 12. The pixel testing method according to claim 11, wherein the step of measuring the voltage level output by the second pixel circuit on the testing terminal comprises: turning on the two second main thin film transistors at the same time; The first auxiliary thin film transistor and the second auxiliary thin film transistor are sequentially turned on to respectively measure the voltage levels stored in the second pixel circuit on the test terminal. 13. The pixel testing method according to claim 9, further comprising providing a scan signal to the first pixel circuit and the second pixel circuit to receive the first pixel voltage and the second pixel voltage. 14. The pixel testing method according to claim 10, wherein the step of measuring the voltage levels output by the first pixel circuit and the second pixel circuit on the test terminal further comprises providing a scan signal to the the first pixel circuit and the second pixel circuit, so that the storage capacitors in the first pixel circuit and the second pixel circuit output their stored voltage levels.

Images