CN1762184A - Near-end crosstalk compensation at multi-stages - Google Patents

Abstract

A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes PCB substrates made of materials having different dielectric frequency characteristics.

Description

Multi-level near-end crosstalk compensation

This application claims priority to US Provisional Application No. 60/456,236, filed March 21, 2003, the entire contents of which are incorporated herein by reference.

Technical field

The present invention relates to near-end crosstalk (NEXT) compensation in communication connectors, and more particularly to techniques for eliminating or reducing NEXT using substrates such as printed circuit boards (PCBs) composed of different dielectric constant materials.

Background technique

Noise or signal interference between conductors in a connector is known as crosstalk. Crosstalk is a common problem in communication devices using connectors. In particular, in communication systems where an analog-to-digital plug, often used in computers, mates closely with an analog-to-digital jack, the conductive wires (conductors) inside the jack and/or plug cause near-end crosstalk (NEXT), i.e., in short distances Crosstalk on closely located conductive wires. A plug that can produce high or low crosstalk due to its construction or the way the cable terminates in the plug. Plugs with high crosstalk are referred to herein as high crosstalk plugs, while plugs with low crosstalk are referred to herein as low crosstalk plugs.

US Patent No. 5,997,358 to Adriaenssens et al. (hereinafter the "'358 patent") describes a secondary mode for compensating for this NEXT. The entire contents of the '358 patent are incorporated herein by reference. Further, the subject matter of US Patent Nos. 5,915,989; 6,042,427; 6,050,843; and 6,270,381 are also incorporated herein by reference.

The '358 patent generally reduces NEXT (initial crosstalk) between conductive wire pairs of an analog-to-digital plug by adding synthetic or artificial crosstalk in the jack in two stages, thus eliminating crosstalk or reducing the overall crosstalk of the plug-and-socket combination . The resulting crosstalk is referred to herein as compensating crosstalk. This method typically provides two levels of NEXT compensation by crossing the line of one conductor inside the connector twice with the line of the other conductor inside the connector. This mode is more efficient in reducing NEXT than the mode of adding compensation in a single stage, especially in the usual case where compensation cannot be introduced except after a certain delay.

Although effective, the NEXT compensation scheme of the '358 patent has a disadvantage, namely, the NEXT tolerance associated with the Telecommunications Industry Association (TIA) limit line at low frequencies (below about 100 MHz) when high crosstalk plugs are used for jacks. ) and worse at high frequencies (over about 250MHz) when low crosstalk plugs are used in jacks. More specifically, a plug-jack combination is considered undercompensated when the net compensated crosstalk in the secondary compensated jack is less than the initial crosstalk (i.e., when a high crosstalk plug is inserted into the jack), and The resulting NEXT frequency characteristic will peak at low frequencies before the null is set at a frequency determined by the interstage delay and the size of the compensation stage. In this case, the NEXT tolerance relative to the TIA limit line is worst at low frequencies. On the other hand, when the net compensated crosstalk in this jack is higher than the initial crosstalk (i.e., when a low crosstalk plug is inserted), the plug-socket combination is considered overcompensated, and the resulting NEXT frequency characteristic will not have zero bit, and the slope of the NEXT frequency characteristic will gradually increase towards 60dB/decade at very high frequencies, far exceeding the limit slope of 20dB/decade of TIA. In this case, the NEXT tolerance relative to the TIA limit line is worst at high frequencies.

Thus, while low frequency tolerance (low frequency characteristics of the connector) can be improved by increasing the level of compensation when high crosstalk plugs are used in jacks, this behavior causes further deterioration in high frequency tolerance when low crosstalk plugs are used in jacks. bad. Conversely, although high frequency tolerance can be improved by reducing the compensation level when low crosstalk plugs are used in jacks, this behavior leads to further degradation of low frequency tolerance when high crosstalk plugs are used in jacks.

Therefore, there is a need for a technology that can simultaneously reduce or eliminate high frequencies such as 250MHz or above when low crosstalk plugs are used, and low frequency frequencies such as 100MHz or below when high crosstalk plugs are used. NEXT on frequency.

Contents of Invention

The present invention overcomes the difficulties and limitations of the related art of reducing NEXT in connectors. Specifically, the present invention provides an apparatus and method for simultaneously improving NEXT high frequency performance when using low crosstalk plugs and using high NEXT low frequency performance with crosstalk plugs. Thus, the present invention improves both low frequency (eg, 1-100 MHz) and high frequency (eg, 250-500 MHz; or 500 MHz and higher) crosstalk performance of the analog-to-digital output and panel.

Description of drawings

Aspects of the invention will become apparent from the following detailed description of the embodiments of the invention with reference to the accompanying drawings, in which:

Fig. 1 (a) is the side view of the connector according to the first embodiment of the present invention;

Figure 1(b) is a top plan view of the printed circuit board and compensation capacitor of Figure 1(a) according to a first embodiment of the present invention;

2 is a top plan view of a printed circuit board and a compensation capacitor of a connector according to a second embodiment of the present invention;

Fig. 3 (a) is the side view of the printed circuit board of the connector according to the third embodiment of the present invention;

Figure 3(b) is a top plan view of the printed circuit board and compensation capacitor of Figure 3(a) according to a third embodiment of the present invention;

Fig. 4 (a) is the side view of the printed circuit board of the connector according to the 4th embodiment of the present invention;

Figure 4(b) is a top plan view of the printed circuit board and compensation capacitor of Figure 4(a) according to a fourth embodiment of the present invention; and

Fig. 5 is a side view of a connector according to a fifth embodiment of the present invention.

Detailed ways

The examples shown in the drawings will now be described in detail with reference to the preferred embodiments of the present invention. In this application, "level" refers to the location where the compensation occurs at the compensation delay point.

The present invention provides printed circuit boards (PCBs) of various configurations that can replace the printed circuit board of Figure 7A of the '358 patent. In some embodiments, the PCB of the present invention is constructed by laminating a plurality of substrates with different dielectric constants (DK).

According to the first embodiment of the present invention, FIG. 1( a ) is a side view of the connector, and FIG. 1( b ) is a top plan view of the printed circuit board and compensation capacitor of FIG. 1( a ).

Referring to Figures 1(a) and 1(b), the connector includes contacts 30 with jumpers 14 and a hybrid PCB 10 where the plug 20 is mated with the connector. Plug 20 may be a modular plug, such as the plug used on the end of a telephone line or patch cord that connects a personal computer to a wall outlet. The contacts 30 may be soldered or press fit into plated through holes in place on the PCB 10 and may be spring wire contacts. Furthermore, the contact 30 has a current-carrying portion 30b and a non-current-carrying portion 30a, the boundary BD between these portions 30a and 30b being indicated in FIG. 1(a). Contacts 30 and PCB 10 may be housed in a housing such as an analog-to-digital jack such that the electrical contacts on plug 20 mate via contacts 30 and electrical contacts on PCB 10 when plug 20 enters the jack.

The PCB 10 according to the first embodiment consists of five substrates (S1-S5) and six metallization layers (ML1-ML6) stacked alternately. More specifically, the substrate and metallization layers are stacked in the following order (from top to bottom): ML1, S1, ML2, S2, ML3, S3, ML4, S4, ML5, S5, and ML6. Half/part of the first substrate S1, the second substrate S2, and the third substrate S3 are made of a material having a low slope DK (ie, a low rate of decrease in dielectric constant with respect to frequency). Dielectric constant is a well-known term used to describe a material's ability to store electrostatic energy. The other half/part of the third substrate S3, the fourth substrate S4 and the fifth substrate S5 are made of a material having a high slope DK (ie, a high drop rate of the dielectric constant with respect to frequency). The use of two different DK materials for substrates S1-S5 is indicated by the presence and absence of hatching.

Metallization layers ML1-ML6 respectively represent conductive patterns of metallization formed on the surface of the substrate directly below the corresponding metallization layer. In FIG. 1( b ), contacts 30 having jumper lines 14 as shown in FIG. 1( a ) are represented as, for example, conductive line pairs 12 and are shown formed on the first metallization layer ML1 . Interdigital capacitors 40a and 40b as first stage compensation capacitors are formed on or as part of the fourth and fifth metallization layers ML4 and ML5, respectively. Interdigitated capacitors 42a and 42b as second stage compensation capacitors are formed on or as part of the second and third metallization layers ML2 and ML3, respectively. Interdigitated capacitors are capacitors having two coplanar arrays of intermeshing metal combs, each at a different potential, and are known.

In this embodiment, capacitors 40a and 40b are replicated on layers ML4 and ML5, and capacitors 42a and 42b are replicated on layers ML2 and ML3. In this application, "replication" in relation to compensation capacitors means identical replication on all specified metallization layers. In other words, capacitor 40a will have exactly the same shape and size as capacitor 40b, and be vertically aligned with capacitor 40b. Likewise, capacitor 42a will have exactly the same shape and size as capacitor 42b, and be vertically aligned with capacitor 42b. The reason for replicating interdigitated capacitors is to increase capacitance without having to increase footprint (surface coverage). Larger footprint interdigitated capacitors can also be used without such duplication. On the other hand, if the printed circuit board is constructed with more metallization layers, then the interdigitated capacitors can be replicated on more than two metallization layers, resulting in a smaller footprint if desired.

According to the present invention, the use of different DK materials for the substrate and the use of interdigitated capacitors for the metallization layers and the use of jumper conductive wire pairs can reduce the noise introduced by the plug 20 if the plug 20 is a low crosstalk plug at high frequency, and NEXT at low frequencies if plug 20 is a high crosstalk plug. How this works is explained below.

NEXT is attributed to two factors: capacitive coupling and inductive coupling. The close proximity of two conductive wires causes capacitive coupling, while the current flowing through these conductive wires causes inductive coupling. Thus, the plug 20 introduces both capacitive and inductive coupling as it mates closely with the contacts 30, and thus NEXT.

In order to reduce or compensate for NEXT caused by inductive coupling, the conductive wire pair 12 (contact 30 ) has a jumper 14 . This is already known and publicly disclosed in the '358 patent.

In order to reduce or compensate NEXT caused by capacitive coupling, PCB 10 includes two levels of capacitive compensation factors. In FIGS. 1( a ) and 1 ( b ), the first stage is at the point of minimum delay from initial crosstalk on the portion of the PCB 10 where the first stage The current carrying portion 30a is electrically connected directly to the contacts of the plug 20 where the contacts intercept the contacts 30 . The second stage is at some delay from the first stage on a portion of the PCB 10 that is removed from where the contacts of the plug 20 intercept the contacts 30 via the current carrying portion 30b of the contacts 30 .

In various embodiments of the invention, interdigitated or parallel plate capacitors are placed on the metallization layer of the first level bonded to the substrate made of high slope DK material. A parallel plate capacitor is a capacitor consisting of two parallel metal plates at different potentials and is known as a capacitor. In the second stage, interdigitated or parallel-plate capacitors are placed on metallization layers bonded to a substrate made of low-slope DK material. For example, in the first embodiment, since substrates S4 and S5 are made of high-slope DK material, interdigitated capacitors 40a and 40b are respectively placed on metallization layers ML4 and ML5 in the first level region. Also because substrates S1 and S2 are made of low slope DK material, interdigitated capacitors 42a and 42b are placed on metallization layers ML2 and ML3, respectively, in the second level region.

In the present invention, the magnitude of the first-stage capacitive coupling decreases with frequency by placing the first-stage interdigitated capacitors (or other types of capacitors) in the PCB substrate with a high DK slope. On the other hand, the second stage capacitive coupling is made relatively flat with frequency by placing the second stage interdigitated capacitors (or other types of capacitors) in the PCB substrate with a low DK slope. As a result, the net compensating crosstalk (composite crosstalk) of a connector consisting of the first level compensating crosstalk minus the second level compensating crosstalk decreases with frequency (ie, with increasing frequency). In other words, the net compensated crosstalk is variable depending on frequency such that the present invention provides low levels of compensated crosstalk at high frequencies to minimize overcompensation of crosstalk in the connector, and high levels of compensation at low frequencies. Crosstalk thereby minimizing insufficient crosstalk compensation in the connector. By providing low levels of compensating crosstalk at high frequencies, the present invention improves the high frequency tolerance of the connector when a low crosstalk plug is inserted into the jack. On the other hand, the present invention improves the low frequency tolerance of the connector when a high crosstalk plug is inserted into the jack by providing a high level of compensated crosstalk at low frequencies.

2 is a top plan view of the printed circuit board and compensating capacitor of FIG. 1(a) according to a second embodiment of the present invention. The second embodiment is identical to the first embodiment except that a different type of compensating capacitor is used. That is, the first stage of compensation capacitors is implemented using parallel plate capacitors 46a and 46b, and the second stage of compensation capacitors is implemented using parallel plate capacitors 48a and 48b. Parallel plate capacitors 46a and 46b are formed on metallization layers ML4 and ML5, respectively, of FIG. 1(a), and parallel plate capacitors 48a and 48b are formed on metallization layers ML2 and ML3, respectively. As a result, the second embodiment operates in the same manner as the first embodiment and obtains the same benefits described above.

According to a third embodiment of the present invention, FIG. 3(a) is a side view of the printed circuit board of the connector, and FIG. 3(b) is a top plan view of the printed circuit board and the compensation capacitor of FIG. 3(a). The third embodiment is similar to the first embodiment in that the connector includes contacts 30 and a PCB and receives a plug such as plug 20 . However, instead of using a hybrid PCB 10 made of high-slope and low-slope DK material as in the first embodiment, a homogenous PCB 50 is used in the second embodiment where all substrates of the PCB are made of high-slope DK material . Also, instead of integrating capacitors in the PCB by using interdigitated or parallel plate type capacitors, surface mount type capacitors may be used in the second level area.

Specifically, referring to FIG. 3( a ), the PCB 50 according to the third embodiment is composed of four substrates S1 - S4 and five metallization layers ML1 - ML5 stacked alternately. All four substrates S1-S4 are made of high DK material. Contacts 30 on the first metallization layer ML1 are not shown in FIG. 3( a ), but are shown in FIG. 3( b ) as conductive wire pairs 12 with jumper wires 14 .

Referring to FIG. 3(b), in the first stage, parallel plate type capacitors 60a and 60b are respectively formed on or as part of the second and third metallization layers ML2 and ML3, wherein the two plates 60a of each capacitor and 60b are parallel to each other. At the second level, surface mount capacitors 62a and 62b are mounted on the first metallization layer ML1 (or below the last metallization layer).

In this embodiment, the magnitude of the first stage capacitive coupling decreases with frequency because the first stage parallel-plate capacitors 60a and 60b are in the PCB 50 with a high DK slope. On the other hand, the second-stage capacitive coupling is relatively flat with frequency because the second-stage capacitance is implemented using discrete surface-mount capacitors. As a result, the net compensation crosstalk consisting of the first order compensation crosstalk minus the second order compensation crosstalk decreases with frequency. By providing low levels of compensated crosstalk at high frequencies, the present invention improves the high frequency tolerance of the connector when a low crosstalk plug is inserted into the jack. On the other hand, the present invention improves the low frequency tolerance of the connector when a high crosstalk plug is inserted into the jack by providing a high level of compensated crosstalk at low frequencies.

According to a fourth embodiment of the present invention, FIG. 4(a) is a side view of the printed circuit board of the connector, and FIG. 4(b) is a top plan view of the printed circuit board and the compensation capacitor of FIG. 4(a).

The fourth embodiment is similar to the first embodiment in that the connector includes contacts 30 and receives a plug such as plug 20 . However, instead of using a hybrid PCB 10 made of high and low DK materials as in the first embodiment, in a fourth embodiment two homogenous PCBs are provided in the connector, where all substrates of the first PCB are Made of high-slope DK material, all substrates of the second PCB are made of low-slope DK material.

Specifically, referring to FIG. 4( a ), in the fourth embodiment, the first PCB 70 is composed of four substrates S1 - S4 and five metallization layers ML1 - ML5 stacked alternately. All four substrates S1-S4 in the first PCB 70 are made of high slope DK material. The second PCB 72 is composed of four substrates S1-S4 and five metallization layers ML1-ML5 stacked alternately. All four substrates S1-S4 in the second PCB 72 are made of low slope DK material. Contacts 30 on the first metal layer ML1 are not shown in FIG. 4( a ), but are shown in FIG. 4( b ) as conductive wire pairs 12 with jumper wires 14 .

Referring to FIG. 4( b ), at the first stage, capacitors 80 a and 80 b are interdigitated capacitors formed on or as part of the second and third metallization layers ML2 and ML3 of the first PCB 70 , respectively. In the second stage, capacitors 82a and 82b are interdigitated capacitors formed on or as part of the second and third metallization layers ML2 and ML3, respectively, of the second PCB 72 .

In this embodiment, the magnitude of the first stage capacitive coupling decreases with frequency because the first stage interdigitated capacitors are in PCB 70 with a high DK slope. On the other hand, the second stage capacitive coupling is fairly flat with frequency because the second stage interdigitated capacitors are in PCB 72 with a low DK slope. As a result, the net compensation crosstalk consisting of the first order compensation crosstalk minus the second order compensation crosstalk decreases with frequency. By providing low levels of compensating crosstalk at high frequencies, the present invention improves the high frequency tolerance of the connector when a low crosstalk plug is inserted into the jack. On the other hand, the present invention improves the low frequency tolerance of the connector when a high crosstalk plug is inserted into the jack by providing a high level of compensated crosstalk at low frequencies.

Fig. 5 is a side view of a connector according to a fifth embodiment of the present invention. The fifth embodiment is similar to the first embodiment in that the connector includes contacts 30 and a PCB and receives a plug such as plug 20 . However, instead of having five substrates in the PCB, PCB 90 has four substrates in the fifth embodiment.

Specifically, referring to FIG. 5 , the hybrid PCB 90 is composed of four substrates S1 - S4 and five metallization layers ML1 - ML5 stacked alternately. The first and second substrates S1 and S2 are made of high-slope DK material, while the third and fourth substrates S3 and S4 are made of low-slope DK material. At the first stage, interdigitated capacitor 94a is formed on or as part of metallization layer ML2. In the second stage, an interdigitated capacitor 96a is formed on or as part of metallization layer ML4.

In this embodiment, the magnitude of the first stage capacitive coupling decreases with frequency because the first stage interdigitated capacitor is between substrates S1 and S2 with a high DK slope. On the other hand, the second-stage capacitive coupling does not drop significantly with frequency because the second-stage interdigitated capacitor is between substrates S3 and S4 with a low DK slope. As a result, the net crosstalk, which consists of first order compensation crosstalk minus second order compensation crosstalk, decreases with frequency. By providing low levels of compensated crosstalk at high frequencies, the present invention improves the high frequency tolerance of the connector when a low crosstalk plug is inserted into the jack. On the other hand, the present invention improves the low frequency tolerance of the connector when a high crosstalk plug is inserted into the jack by providing a high level of compensated crosstalk at low frequencies.

In various embodiments of the present invention, the high-slope DK material used for the PCB substrate preferably has a dielectric constant equal to or about 4.0 at 1 MHz, with a frequency per decade of the dielectric constant between 1 MHz and 1 GHz The rate of decline is 0.4. The low-slope DK material used for the PCB substrate preferably has a dielectric constant equal to or about 4.0, which should remain flat over the frequency range of 1 MHz and 1 GHz. As an example, materials such as FR-4 and/or Teflon may be used as the PCB substrate. Other commercially available high and low slope DK materials can be used. For example, Nelco N4000-7 is an example of a high slope DK material that can be used in the PCB substrate of the present invention, and Nelco N4000-13 SI is an example of a low DK slope material that can be used in the PCB substrate of the present invention. Nelco N4000-7 has a dielectric constant of 4.5 at 1 MHz and 3.9 at 1 GHz, while Nelco N4000-13SI has a dielectric constant of 3.6 at 1 MHz and 3.5 at 1 GHz. Also, the dielectric constant levels of these materials can be easily tuned by adjusting the footprint range of interdigitated or parallel plate capacitors, if desired. As such, materials having a dielectric constant in the range of approximately 3.0 to 5.0 at 1 MHz may be used. Obviously other materials can also be used.

In general, the dielectric constant (DK) of most PCB materials decreases with frequency. In conventional 2-stage compensation systems, the effect of this drop has been largely weakened due to the deployment of first and second compensation stages of opposite polarity on the same material substrate. This makes the first and second tiers have the same DK drop rate. The present invention intentionally uses a material with a very steep DK dip in the first stage and a very low DK dip in the second stage. This tends to result in capacitive coupling in such a way that as frequency increases the overall level of compensation is reduced, thus improving high frequency NEXT performance.

Although four or five PCB substrates are illustrated, it is quite obvious that any other number of PCB substrates and/or metallization layers could be used for the PCB. An important aspect is that there is a large difference in DK slope when comparing the materials used to fabricate low-slope DK substrates and high-slope DK substrates. The difference between the high DK slope and the low DK slope may be in the range of 0.15 to 0.45 per decade of frequency.

With materials having two different DK slopes, the connector designer has more flexibility in designing/increasing the capacitor value to better suppress the NEXT of the connector. Still further, stages of NEXT suppression can be placed on/between substrates with very different DK slopes. The resulting connector of the present invention can be combined with housings, insulation displacement connectors, socket spring contacts and the like.

Also, various structures and features of the above-described embodiments may be combined or replaced by other embodiments. For example, the parallel plate type capacitors 60a, 60b in FIG. 3(b) can be replaced with interdigitated type capacitors. The interdigitated capacitors 80a, 80b, 82a, 82b in FIG. 4(b) can be replaced with parallel plate capacitors. Wherever interdigitated capacitors are used, such capacitors can be duplicated relative to corresponding other interdigitated capacitors. In a connector, interdigitated capacitors can be implemented on a single metallization layer or on several metallization layers. Still further, as mentioned above, any number of metallization layers/substrates for one or more PCBs can be used; the location of high and/or low slope DK materials can be varied; or the use and location of low DK slope materials; and different types of capacitors (eg, parallel plate, interdigitated, surface mount, etc.) can be used.

Although the present invention has been described by the embodiments shown in the above drawings, it should be understood by those skilled in the art that the present invention is not limited to these embodiments, and without departing from the spirit of the present invention Various changes or modifications can be made thereto.

Claims (38)

1, a kind of printed circuit board (PCB) (PCB) structure can be used for reducing cross-talk in the connector, it is characterized in that, this PCB structure comprises:

At least one PCB, this PCB comprises a plurality of substrates and a plurality of metal layers between substrate, this substrate comprises at least one first substrate made by first material and at least one second substrate of being made by second material, first material has first dielectric constant, and second material has second dielectric constant that is lower than first dielectric constant on the rate of descent with frequency;

Be arranged on described at least one first on-chip at least one first capacitor in the first order zone of PCB structure; With

Be arranged on described at least one second on-chip at least one second capacitor in the zone, the second level of PCB structure.

2, PCB structure as claimed in claim 1 is characterized in that, wherein, first dielectric constant is approximately 4.0 at 1MHz, and the every decimal rate of descent of the frequency of this first dielectric constant is 0.4 between 1MHz and 1GHz.

3, PCB structure as claimed in claim 1 is characterized in that, wherein, second dielectric constant is approximately 4.0, remains unchanged in the frequency range of 1MHz and 1GHz.

4, PCB structure as claimed in claim 1 is characterized in that, wherein, the substrate of PCB is five mutual stacked substrates,

The part of first substrate, second substrate and the 3rd substrate make by second material and

The part of the 3rd substrate, the 4th substrate and the 5th substrate are made by first material.

5, PCB structure as claimed in claim 4 is characterized in that, wherein, described at least one first capacitor comprises the 4th and the 5th on-chip two first capacitor elements in the first order zone that is formed on the PCB structure.

6, PCB structure as claimed in claim 5 is characterized in that, wherein, and described two first capacitor boards that capacitor element is interdigital capacitor or parallel plate capacitors.

7, PCB structure as claimed in claim 4 is characterized in that, wherein, described at least one second capacitor comprises the second and the 3rd on-chip two second capacitor elements in the zone, the second level that is formed on the PCB structure.

8, PCB structure as claimed in claim 7 is characterized in that, wherein, and described two second capacitor boards that capacitor element is interdigital capacitor or parallel plate capacitors.

9, PCB structure as claimed in claim 1 is characterized in that, wherein, the substrate of PCB is four substrates that are laminated to each other,

First substrate and second substrate make by first material and

The 3rd substrate and the 4th substrate are made by second material.

10, PCB structure as claimed in claim 9 is characterized in that, wherein, described at least one first capacitor comprises second on-chip first capacitor in the first order zone that is formed on the PCB structure.

11, PCB structure as claimed in claim 9 is characterized in that, wherein, described at least one second capacitor comprises the 4th on-chip second capacitor in the zone, the second level that is formed on the PCB structure.

12, PCB structure as claimed in claim 1 is characterized in that, wherein, described at least one PCB comprises first and second PCB, and a PCB comprises the substrate of being made by first material, and the 2nd PCB comprises the substrate of being made by second material.

13, PCB structure as claimed in claim 12 is characterized in that, wherein, described at least one first capacitor comprises at least two on-chip two first capacitor elements of a PCB in the first order zone that is formed on the PCB structure.

14, PCB structure as claimed in claim 13 is characterized in that, wherein, two first capacitor elements are capacitor boards of interdigital capacitor or parallel plate capacitors.

15, PCB structure as claimed in claim 12 is characterized in that, wherein, described at least one second capacitor comprises at least two on-chip two second capacitor elements of the 2nd PCB in the zone, the second level that is formed on the PCB structure.

16, PCB structure as claimed in claim 15 is characterized in that, wherein, and described two second capacitor boards that capacitor element is interdigital capacitor or parallel plate capacitors.

17, a kind of printed circuit board (PCB) (PCB) structure can be used for reducing cross-talk in the connector, it is characterized in that, this PCB structure comprises:

Printed circuit board (PCB) (PCB) comprises stacked a plurality of substrates and a plurality of metal layers between substrate, and this substrate is made by the material that has the dielectric constant of high rate of descent with frequency;

Be arranged on one of them on-chip at least one first capacitor in the first order zone of PCB structure; With

Be arranged on one of them on-chip at least one second capacitor in the zone, the second level of PCB structure.

18, PCB structure as claimed in claim 17 is characterized in that, wherein, substrate material has about 4.0 dielectric constant at 1MHz, and the every decimal rate of descent of the frequency of this dielectric constant is 0.4 between 1MHz and 1GHz.

19, PCB structure as claimed in claim 17 is characterized in that, wherein, described at least one first capacitor comprises at least two on-chip two first capacitor elements in the first order zone that is formed on the PCB structure.

20, PCB structure as claimed in claim 19 is characterized in that, wherein, and described two first capacitor boards that capacitor element is interdigital capacitor or parallel plate capacitors.

21, PCB structure as claimed in claim 17 is characterized in that, wherein, described at least one second capacitor comprises on first substrate in the zone, the second level that is surface mounted in the PCB structure or the second independent discrete capacitor under last substrate.

22, a kind of connector that is used to reduce cross-talk is characterized in that, comprising:

At least one printed circuit board (PCB) (PCB), this PCB comprises a plurality of substrates and a plurality of metal layers between substrate, this substrate comprises at least one first substrate made by first material and at least one second substrate of being made by second material, first material has first dielectric constant, and second material has second dielectric constant that is lower than first dielectric constant on the rate of descent with frequency;

Be arranged on described at least one first on-chip at least one first capacitor in the first order zone of connector;

Be arranged on described at least one second on-chip at least one second capacitor in the zone, the second level of connector; With

Be arranged at least one conductive contact on the PCB.

23, connector as claimed in claim 22 is characterized in that, wherein, first dielectric constant is approximately 4.0 at 1MHz, and the every decimal rate of descent of the frequency of this dielectric constant is 0.4 between 1MHz and 1GHz.

24, connector as claimed in claim 22 is characterized in that, wherein, second dielectric constant is approximately 4.0, remains unchanged in the frequency range of 1MHz and 1GHz.

25, connector as claimed in claim 22 is characterized in that, wherein, the substrate of PCB is five mutual stacked substrates,

The part of first substrate, second substrate and the 3rd substrate make by second material and

The part of the 3rd substrate, the 4th substrate and the 5th substrate are made by first material.

26, connector as claimed in claim 25 is characterized in that, wherein, described at least one first capacitor comprises the 4th and the 5th on-chip two first capacitor elements in the first order zone that is formed on connector.

27, connector as claimed in claim 25 is characterized in that, wherein, described at least one second capacitor comprises the second and the 3rd on-chip two second capacitor elements in the zone, the second level that is formed on connector.

28, connector as claimed in claim 22 is characterized in that, wherein, the substrate of PCB is four mutual stacked substrates,

First substrate and second substrate make by first material and

The 3rd substrate and the 4th substrate are made by second material.

29, connector as claimed in claim 28 is characterized in that, wherein, described at least one first capacitor comprises second on-chip first capacitor in the first order zone that is formed on connector.

30, connector as claimed in claim 28 is characterized in that, wherein, described at least one second capacitor comprises the 4th on-chip second capacitor in the zone, the second level that is formed on connector.

31, connector as claimed in claim 22 is characterized in that, wherein, described at least one PCB comprises first and second PCB, and a PCB comprises the substrate of being made by first material, and the 2nd PCB comprises the substrate of being made by second material.

32, connector as claimed in claim 31 is characterized in that, wherein, described at least one first capacitor comprises at least two on-chip two first capacitor elements of a PCB in the first order zone that is formed on connector.

33, connector as claimed in claim 31 is characterized in that, wherein, described at least one second capacitor comprises at least two on-chip two second capacitor elements of the 2nd PCB in the zone, the second level that is formed on connector.

34, a kind of connector that is used to reduce cross-talk is characterized in that, comprising:

Printed circuit board (PCB) (PCB) comprises a plurality of stacked substrates and a plurality of metal layers between substrate, and this substrate is made by the material that has the dielectric constant of high rate of descent with frequency;

Be arranged on one of them on-chip at least one first capacitor in connector first order zone;

Be arranged on one of them on-chip at least one second capacitor in zone, the connector second level; With

Be arranged at least one conductive contact on the PCB.

35, connector as claimed in claim 34 is characterized in that, wherein, substrate material has about 4.0 dielectric constant at 1MHz, and the every decimal rate of descent of the frequency of this dielectric constant is 0.4 between 1MHz and 1GHz.

36, connector as claimed in claim 34 is characterized in that, wherein, described at least one first capacitor comprises at least two on-chip two first capacitor elements in the first order zone that is formed on connector.

37, connector as claimed in claim 36 is characterized in that, wherein, and described two first capacitor boards that capacitor element is interdigital capacitor or parallel plate capacitors.

38, connector as claimed in claim 34 is characterized in that, wherein, described at least one second capacitor comprises on first substrate in the zone, the second level that is surface mounted in connector or the second independent discrete capacitor under last substrate.

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