CN1744052A

CN1744052A - Storage unit on-board measuring method

Info

Publication number: CN1744052A
Application number: CN 02110992
Authority: CN
Inventors: 李颍悟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2002-03-11
Filing date: 2002-03-11
Publication date: 2006-03-08
Anticipated expiration: 2022-03-11
Also published as: CN100346309C

Abstract

Using boundary scan device circuit board owns, the method tests memory. The boundary scan device is connected to memory directly or indirectly. Through scanning chain, of the boundary scan device, the method writes data into/reads data from memory. The method is not dependent on normal operation of system, not need of expensive ICT testing devices and editing related test program so as to low cost for testing memory.

Description

Memory is at board measuring method

Technical field

The present invention relates to method for testing memory, the method for particularly utilizing circuit board coboundary scanning device that memory is tested.

Background technology

The test of memory is divided into two classes, and a class is called from board measuring method, namely utilizes the memory test instrument of door special to come testing memory before memory is not soldered on the PCB. Another kind of being called at board measuring method, namely be soldered to the upper afterwards testing memory of printed circuit board (PCB) (PCB) at memory.

, mainly contain the System self-test method and utilize on-line testing (ICT) apparatus testing method at board test for memory. In the System self-test method, the test program of memory is stored in BIOS or the flash memory (Flash). The operation test program was to carry out self check to memory, if discovery mistake, then reporting errors or demonstration mistake after system power-up started. Adopting the basic premise condition of System self-test method testing memory is that system itself can work, if system can't work, then can't judge the fault of other unit in the fault of memory or the system at all. And because different systems moves under different environment, so test program lacks versatility and portability, the memory test of each circuit board needs the special test program of special exploitation. In addition, because test program itself need to take certain storage space, so can't directly directly test the memory cell of depositing test program in the memory during System self-test. And if program moved carry out alternately testing, then increased again the design difficulty of program, reduced the reliability of system.

Fig. 1 shows another kind of at board measuring method, namely utilizes the method for ICT testing of equipment memory. As shown in Figure 1, the method control line, address wire and data wire that memory is all is connected on the probe of ICT equipment, by the ICT test program of writing in advance the test and excitation signal reclaimed test response signal to carry out storage defect analysis through probe actuation to memory and by probe. Adopt ICT testing of equipment memory need to use expensive equipment, and need the professional to develop special ICT test program, so the unable maintenance of domestic consumer and use, general was adopted in the production phase. In addition, probe is physical contact with contacting of memory, not only need to reserve test point when board design, but also may have the fault erroneous judgement that causes because of loose contact.

Summary of the invention

Problem for above-mentioned existence, purpose of the present invention just provides a kind of new memory at board measuring method, the method does not rely on the normal operation of system and need not to use expensive ICT testing equipment and write corresponding test program, therefore greatly reduces the memory test cost.

Comprise following steps according to method for testing memory of the present invention: (1) is installed in memory on the circuit board of band border scanning (BS) device, and the BS device comprises by test data input (TDI) port, a plurality of boundary scan cell that is connected in series of device inside and boundary scan link that test data output (TDO) port consists of of being positioned at; (2) any one in data wire, address wire or the control line of boundary scan cell and memory is connected; (3) data wire, address wire or the control line through linking to each other with boundary scan cell on the boundary scan link is with the data in test data write memory and/or the read memory; And (4) compare to determine whether memory exists the type of fault and fault with the data of the data that read and expectation.

According to memory of the present invention board measuring method utilize on the general circuit plate all with boundary scanning device, need not to increase again special testing equipment and test program, therefore reduced testing cost. Meanwhile, the method need not to finish under working state of system, can test as long as power on, and therefore is convenient to the isolation test system failure.

Description of drawings

By can further understanding target of the present invention, feature and advantage below in conjunction with accompanying drawing to the description of preferred embodiment of the present invention, wherein:

Fig. 1 shows the method for utilizing ICT testing of equipment memory;

Fig. 2 is the schematic diagram of boundary scanning device structure;

Fig. 3 is 16 state machine diagram of boundary scanning device;

Fig. 4 shows and utilizes circuit board coboundary scanning device at the system construction drawing of board test IC-components;

The boundary scan link that jtag interface and boundary scanning device connected and composed when Fig. 5 showed testing memory;

Fig. 6 is for adopting the flow chart of nine step checkerboard pattern method testing memory internal elements; And

Fig. 7 is for adopting the flow chart of nine step checkerboard pattern method testing memory internal elements.

The specific embodiment

Boundary scan (Boundary Scan, referred to as BS) technology by between the input and output pin of tested device and kernel circuitry, introducing boundary scan cell (BSC) thus by these boundary scan cells tested device and peripheral circuit thereof are tested, thereby improved controllability and the observability of device. Because boundary scan technique has solved the test problem that the modern electronic technology development brings, therefore be widely used, the circuit board of producing now general all with boundary scanning device to make things convenient for the test after device is assembled on the circuit board. The detailed description of relevant boundary scan technique can be referring to IEEE 1149.1 standards. Below by Fig. 2 and Fig. 3 the operation principle of boundary scanning device is described briefly.

As shown in Figure 2, boundary scanning device comprises boundary scan cell (BSC) and the corresponding control module that is connected between I/O pin and the kernel circuitry, and control module comprises test access port (TAP), command register (IR), data register bank (DR) and TAP controller etc. TAP is the interface that boundary scanning device is connected with external equipment, comprise test clock input (Test Clock Input, being designated hereinafter simply as TCI) end, test pattern select input (Test Mode Selector, be designated hereinafter simply as TMS) end, test data input (Test Data Input, be designated hereinafter simply as TDI) end, test reset input (Test Reset Input, be designated hereinafter simply as TRST) end and test data output (Test Data Output, be designated hereinafter simply as TDO) end, it is optional wherein inputting the TRST end. Below their do concise and to the point the description:

(1) test clock input (TCK) end

Be used for providing test clock signals, for keeping the independence of TCK frequency, it must not disturb mutually with any system clock. Effective at the rising edge of tck clock pulse from the data of TDI end shift-in, the data that shift out to the TDO end are effective at the trailing edge of tck clock pulse. Then carry out at the rising edge of TCK clock pulses from the system input data of packing into.

(2) test mode is selected input (TMS) end

Be used for providing test mode to select, control operation is explained and be used for to its logical signal that receives (0 or 1) by the TAP controller. When the TCK rising edge, tms signal is sampled, thus the sampled signal control signal that decoded generation chip internal needs in the TAP controller.

(3) test data input (TDI) end

Be used for serial mode test data being inputted kernel circuitry through boundary scan cell, according to the state verification data of TAP controller also selected input command register or data register. The data of serial input move into when the TCK rising edge.

(4) test data output (TDO) end

Be used for serial mode test data from kernel circuitry (through boundary scan cell) and command register or data register output, the TAP controller state has determined that data take from command register or the data register. The data of serial output shift out at the TCK trailing edge, and when not having data when TDO exports, the TDO end is set to high-impedance state usually.

(5) test reset input (TRST) end

Be used for to the test reset input of a logical zero of TRST pin input, the logic asynchronous pressure of TAP enters its reset mode. The TRST line is optional holding wire, and under any state, as long as TMS keeps the high level of 5 tck clocks, the boundary scan logic circuit just automatically resets.

The TAP controller is a sequence circuit, is used for the operation of control instruction register and data register. The TAP controller is selected (TMS) and test clock (TCK) signal driver by test pattern, and its operation can be described with the state diagram with IEEE 1149.1 standard definitions shown in Figure 3. In Fig. 3, all state conversions (representing with arrow) occur in the rising edge of test clock pulse TCK in the TAP controller, and the effect of the logic that is connected with TAP (register etc.) occurs in rising edge or the trailing edge of TCK. The value on arrow next door is the value of TMS when the TCK rising edge. The state that marks take shade among the figure is as main state, and unblanketed state is for not causing systemic effect but the secondary status of process control can be provided.

Fig. 4 shows and utilizes circuit board coboundary scanning device at the system construction drawing of board test IC-components. This test macro is comprised of computer, circuit board three parts that meet the jtag controller of IEEE 1149.1 standards and comprise measured device. Computer is installed the software that is used for boundary scan testing, and this software mainly is that circuit board is analyzed, and extracts circuit board information and device information, generates the test and excitation signal and sends jtag controller to according to certain testing algorithm. Jtag controller is connected between computer and the circuit board, the test and excitation signal arrangement of being responsible for receiving is JTAG signal (comprising TDI, TMS and tck signal) and is applied on the corresponding port of circuit board scanning device that meanwhile jtag controller is responsible for receiving test response signal and returning to computer for its analysis from the TDO port of circuit board scanning device.

The boundary scan link that jtag controller interface and boundary scanning device connected and composed when Fig. 5 showed testing memory. As shown in Figure 5, scanning device within it section's formation one is gone through the boundary scan link that TDI end, a plurality of boundary scan cell that is connected in series and TDO hold, the TDI end is connected with the test data input of JTAG controller with TDO and is connected with output, in addition, every control line, data wire or the address wire of memory is connected with a boundary scan cell, therefore can be by all memory cell of boundary scan cell reference to storage.

Below describe by 16 state machines shown in Figure 3 and to utilize boundary scanning device with the test data write memory with from the mode of memory read test data.

In the process with the test data write memory, jtag controller at first makes the BS device be in serial shift (shift-DR) state, under this state, the test and excitation signal is preset to the corresponding boundary scan cell in the serial shift mode from TDI end and TDO end, this test and excitation signal system draws according to memory feature and fault model thereof, represented assignment required to address wire, data wire and control line when setting the address and write setting data to memory, be described below and utilize the present invention how to carry out to describe in detail when the test of memory external interconnect and internal element are tested the data that obtain write memory according to memory feature and fault model. Jtag controller makes the BS device through entering renewal (Update-DR) state as main state behind a series of secondary status subsequently, under this state, pumping signal in the boundary scan cell is admitted to the memory cell of appointment by address wire, data wire or the control line that links to each other, and has realized that thus memory writes operation.

From the process of memory read test data, jtag controller at first makes the BS device be in serial shift (shift-DR) state, under this state, the test and excitation signal is preset to the corresponding boundary scan cell in the serial shift mode from TDI end and TDO end, when this test and excitation signal has represented and has read setting data from memory setting address to address wire and the required assignment of control line. Jtag controller makes the BS device through entering renewal (Update-DR) state as main state behind a series of secondary status subsequently, under this state, the pumping signal in the boundary scan cell is applied on continuous address wire and the control line to choose the selected address of memory. Then, boundary scanning device experiences a series of secondary status and enters (Capture-DR) state of catching as main state under the control of jtag controller, under this state with the signal leading on the memory data line in the boundary scan cell that links to each other. At last, the BS device enters the serial shift state, thereby in the serial shift mode data of catching is drawn the operation that the BS device is realized reading memory data.

Therefore, utilize the boundary scanning device that carries on the circuit board can realize easily reading and write operation of memory, therefore if finish the read-write operation of memory according to memory characteristics and fault model with certain rule, just can be by writing and relatively the fault of memory being analyzed of reading out data.

Below describe by selecting suitable test data to come the method for the various faults of analyzing stored device as an example of readable and writable memory and read-only storage (ROM) example.

For readable and writable memory, its test comprises external interconnect test and internal element test, external interconnect test is exactly that fault to data wire, address wire and the control line of memory detects, and the internal element test then is that the fault to the memory cell of memory detects. External testing has different fault models with close beta, and therefore reasonable is to adopt different testing algorithms for different tests. Below this is described in detail respectively:

A. memory external interconnect test

(1) fault model

It is the prerequisite of determining testing algorithm that thereby failure mechanism analysis is set up corresponding fault model. For the external interconnect test, what adopt here is stuck-at fault model. In fact, persistent fault also is the major failure of memory input/output line. Stuck-at fault model comprises fixed logic fault, stuck-open fault and bridge joint short trouble.

A, fixed logic fault (Stuck-at fault)

The fixed logic fault refers to because the state of the data wire that causes of physical imperfection or address wire is not subjected to input control and constant fault for logical zero or logical one state, comprise logic state constant be 1 S-A-1 (Stuck-at-1) fault and logic state constant be 0 S-A-0 (Stuck-at-0) fault. Persistent fault is called again dull fault.

B, stuck-open fault (Stuck-open fault)

Stuck-open fault refers to because the fault that open circuit causes. Externally in the interconnecting test, according to the circuit concrete structure, stuck-open fault often is equivalent to the fixed logic fault of S-A-0 or S-A-1.

C, bridge joint short trouble (Short fault)

The bridge joint short trouble refers to comprise 0-dominance short trouble (0-Dominant Short fault) and 1-dominance short trouble (1-Dominant Short fault) owing to the fault that short circuit causes between input and/or the output line more than 2 or 2.

(2) three step methods of testing

For said external interconnect fault model, the present inventor proposes a kind of algorithm that is called three step methods of testing, and this algorithm not only can be found the external interconnect fault, and can accurately locate fault. The process of three step methods of testing is described below in conjunction with table 1.

Table 1

Testing procedure	Operation	The address	Data	Note
Testing procedure	Operation	The address	Data	Note	The first step	Write	A	₀	0...000	A ₀And A₁Be two arbitrarily different addresses, compare in the time of reading and judge.
	Write	A ₁	1...111		The first step	Write	A	₀	0...000
	Write	A ₁	1...111	Read	A	₀	0...000
	Read	A	₁	Read	A	₀	0...000	1...111
	Read	A	₁	Second step a	Write	A	₀	1...111	0...001		A ₀、A ₁、...、A _nBe any group address, require the address different, suggestion is just adopted one group since 0 address that increases progressively, and data wire is used walking 1 algorithm.
	Write	A ₁	0...010	Second step a	Write	A	₀		0...001
	Write	A ₁	0...010	......	......	......
	Write	A _n	1...000	......	......	......
	Write	A _n	1...000	Read	A0		0...001
	Read	A	₁	Read	A0		0...001	0...010
	Read	A	₁	......	......	......		0...010
	Read	A _n	1...000	......	......	......
	Read	A _n	1...000	Second step b	Data wire is used walking 0 algorithm, repeat the process of second step a
The 3rd step a	Write	0...000	D ₀	Second step b					D ₀、D ₁、...D _nAny one group of differentiable data. Address wire is used walking 1 algorithm.
The 3rd step a	Write	0...000	D ₀		Write	0...001	D ₁
Write	......	......			Write	0...001	D ₁
Write	......	......	Write		1...000	D _n
Read	0...000	D ₀	Write		1...000	D _n
Read	0...000	D ₀	Read		0...001	D ₁
Read	......	......	Read		0...001	D ₁
Read	......	......	Read		1...000	D _n

The 3rd step b

Address wire is used walking 0 algorithm, repeat the process of the 3rd step a.

The test of the first step in the table 1 is by writing the data of full 0 and complete 1 and read data on these two addresses and detect data wire and whether have open fault in different address arbitrarily two of A0 and A1. Particularly, do not read full 0 if write full 0, just illustrate that there is the fault of S-A-1 in data wire, numerical value is that 1 data wire is exactly the fault wire position that S-A-1 occurs. Do not read entirely 1 if write complete 1, just illustrate that there is the fault of S-A-0 in data wire, numerical value is that 0 data wire is exactly the linear position data that the S-A-0 fault occurs.

Second step test is used for the test data line and whether has short trouble. As shown in table 1, at first pass through on data wire to n inequality address A₀、A ₁……A _nWrite correspondingly n the data D that generates according to walking 1 algorithm₀、D ₁……D _n(claiming again test vector) also reads data on the described n address, wherein primary data D by data wire₀Be 100 ... 0. The implication of walking 1 algorithm (Walk-1) is, the generating mode of test vector is a rear test vector by being that 1 position generates to same direction displacement with value in the last test vector. If for example test vector number n is 7, the initial testing vector is 1000000, then according to walking 1 algorithm, test vector can be successively: 1000000,0100000,0010000,0001000,0000100,0000010 and 0000001, if and the initial testing vector is 0000000, then according to walking 1 algorithm, test vector can be successively: 0000000,1000000,0100000,0010000,0001000,0000100 and 0000010.

Then pass through on data wire to a said n inequality address A₀、A ₁……A _nWrite correspondingly n the data D that generates according to walking 0 algorithm₀、D ₁……D _n(claiming again test vector) also reads data on the described n address, wherein primary data D by data wire₀Be 011 ... 1. Walking 0 algorithm (Walk-0) and walking 1 algorithm are complementary, and namely the generating mode of its test vector is a rear test vector by being that 0 position generates to same direction displacement with value in the last test vector. If for example test vector number n also is 7, the initial testing vector is 0111111, then test vector can be 0111111,1011111,1101111,1110111,1111011,1111101 and 1111110, if and the initial testing vector is 1111111, then test vector can be 1111111,0111111,1011111,1101111,1110111,1111011 and 1111101.

Can judge to linear position data and the short trouble type of short trouble that according to the second step test result how the below illustrates to diagnosing malfunction that as an example of a second step test result shown in the table 2 example the test data line here is b₃b ₂b ₁b ₀, test vector (namely giving the logical value of data wire) is r₀、r ₁…… r ₇, initial testing vector r wherein₀And r₄Be 1000 and 0111.

By as seen from Table 2, not only can determine the linear position data of fault that is short-circuited according to one group of test result of second step test, and can determine the type of short trouble, particularly can distinguish the short circuit of 1-dominance and the short circuit of 0-dominance.

Table 2

1	2	3	4	5	6	7	8
1	2	3	4	5	6	7	8		Desired value	The b2 S-A-0 that opens a way	B2 and b1 open circuit S-A-0	B2 and b1 short circuit 0-dominance	B2 and b1 open circuit S-A-1	B2 and b1 short circuit 1-dominance	B3 and b1 open circuit S-A-0 b2 and b1 short circuit 0-dominance
	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀		Desired value	The b2 S-A-0 that opens a way	B2 and b1 open circuit S-A-0	B2 and b1 short circuit 0-dominance	B2 and b1 open circuit S-A-1	B2 and b1 short circuit 1-dominance
	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	b ₃b ₂b ₁b ₀	r ₀	1000	1000	1000	1000	110	1000	0000
r ₁	0100	0000	0000	0000	010	0110	0000	r ₀	1000	1000	1000	1000	110	1000	0000
r ₁	0100	0000	0000	0000	010	0110	0000	r ₂	0010	0010	0000	0000	010	0110	0000
r ₃	0001	0001	0001	0001	011	0001	0000	r ₂	0010	0010	0000	0000	010	0110	0000
r ₃	0001	0001	0001	0001	011	0001	0000	r ₄	0111	0011	0001	0111	011	0111	0110
r ₅	1011	1011	1001	1001	111	1111	0000	r ₄	0111	0011	0001	0111	011	0111	0110
r ₅	1011	1011	1001	1001	111	1111	0000	r ₆	1101	1001	1001	1001	1111	1111	0000
r ₇	1110	1010	1000	1110	1110	1110	0110	r ₆	1101	1001	1001	1001	1111	1111	0000

After guaranteeing that data wire does not have fault, can carry out the 3rd pacing examination and whether have open circuit or short trouble with the test address line. At first pass through on data wire to n the address A ' that selectes successively according to walking 1 algorithm₀、A′ ₁……A′ _nWrite successively n inequality data D '₀、D′ ₁……D′ _nAnd read data on the described n address, wherein initial address A ' by data wire₀Be 000 ... 0. Pass through subsequently on data wire to n the address A ' that selectes successively according to walking 0 algorithm₀、A′ ₁……A′ _nWrite successively n inequality data D '₀、D′ ₁……D′ _nAnd read data on the described n address, wherein initial address A ' by data wire₀Be 111 ... 1.

The difference in second step and the 3rd step is, in the second step test, write any one group separably the data of location generate according to walking 1 algorithm or walking 0 algorithm, and in the 3rd pacing examination, any one group of differentiable data are write the address of selecting successively according to walking 1 algorithm or walking 0 algorithm, and initial address is full 0 or complete 1. Below as an example of the 3rd a pacing test result shown in the table 3 example the explanation how to diagnosing malfunction, the address wire a here₃a ₂a ₁a ₀Change according to walking 1 or walking 0 algorithm, initial address is 0000, and the number of addresses that therefore writes is 5, and the data D that writes₀、D ₁、D ₂、D ₃And D₄Different.

By as seen from Table 3, not only can determine the address wire position of fault that is short-circuited according to one group of test result of the 3rd pacing examination, and can determine the type of short trouble, particularly can distinguish the short circuit of 1-dominance and the short circuit of 0-dominance.

Table 3

1	2	3	4	5	6	7	8
1	2	3	4	5	6	7	8	The address	Desired value	The a2 S-A-0 that opens a way	A2 and a1 open circuit S-A-0	A2 and a1 short circuit 0-dominance	A2 and a1 open circuit S-A-1	A2 and a1 short circuit 1-dominance	A3 and a0 open circuit S-A-0 a2 and a1 short circuit 0-dominance
a ₃a ₂a ₁a ₀								The address	Desired value	The a2 S-A-0 that opens a way	A2 and a1 open circuit S-A-0	A2 and a1 short circuit 0-dominance	A2 and a1 open circuit S-A-1	A2 and a1 short circuit 1-dominance
a ₃a ₂a ₁a ₀								0000	D ₀	D ₃	D ₃	D ₃	D ₃	D ₀	D ₄
0001	D ₁	D ₁	D ₁	D ₁	D ₁	D ₁	D ₄	0000	D ₀	D ₃	D ₃	D ₃	D ₃	D ₀	D ₄
0001	D ₁	D ₁	D ₁	D ₁	D ₁	D ₁	D ₄	0010	D ₂	D ₂	D ₃	D ₃	D ₃	D ₃	D ₄
0100	D ₃	D ₃	D ₃	D ₃	D ₃	D ₃	D ₄	0010	D ₂	D ₂	D ₃	D ₃	D ₃	D ₃	D ₄
0100	D ₃	D ₃	D ₃	D ₃	D ₃	D ₃	D ₄	1000	D ₄	D ₄	D ₄	D ₄	D ₄	D ₄	D ₄
1111	D ₀	D ₃	D ₃	D ₀	D ₃	D ₃	D ₄	1000	D ₄	D ₄	D ₄	D ₄	D ₄	D ₄	D ₄
1111	D ₀	D ₃	D ₃	D ₀	D ₃	D ₃	D ₄	1110	D ₁	D ₁	D ₁	D ₁	D ₁	D ₁	D ₄
1101	D ₂	D ₂	D ₃	D ₃	D ₃	D ₃	D ₃	1110	D ₁	D ₁	D ₁	D ₁	D ₁	D ₁	D ₄
1101	D ₂	D ₂	D ₃	D ₃	D ₃	D ₃	D ₃	1011	D ₃	D ₃	D ₃	D ₃	D ₃	D ₃	D ₃
0111	D ₄	D ₄	D ₄	D ₄	D ₄	D ₄	D ₄	1011	D ₃	D ₃	D ₃	D ₃	D ₃	D ₃	D ₃

B. memory inside unit testing

(1) fault model

Memory mainly by decoder, write drive circuit, read amplifying circuit, memory cell array and input/output section form. Its fault is divided into memory cell array fault, address decoding circuitry fault and read-write logic fault according to the occurrence positions difference, wherein:

Fault in the memory cell array comprises with Types Below:

1. fixed logic fault (Stuck-at fault): the logical value of a unit does not change with any behavior of unit, be not subjected to the impact of remaining element yet, claim again dull fault, it comprises and is fixed as 1 or be fixed as 0 two kinds of situations (S-A-0 or S-A-1);

2. stuck-open fault (Stuck-open fault): the fault that open circuit causes;

3. state translation exception (Transition fault): 0 → 1 or 1 → 0 state is converted to rare one and is not executed correctly;

4. data keep fault (Data-maintaining fault): memory cell can't keep a logical value to continue the regular hour;

5. state coupling fault (Coupling fault): and if only if unit j is in some particular state y (y χ 0, in the time of 1}), unit i be always some determined value x (x χ 0,1}), then claim unit i to be coupled in unit j. Coupled relation not necessarily has symmetry, also just says that unit i is coupled in unit j, might not also be coupled in unit I by unit j.

6. multiple Write fault (multiple access fault): to unit i write x (x χ 0,1}) cause unit j also to write x, then claim unit i that multiple Write fault is arranged. Multiple Write fault not necessarily has symmetry.

Fault in the address decoding circuitry comprises with Types Below:

1. do not choose arbitrary memory cell;

2. choose selected cell, and chosen other unit.

Fault in the decoder can equivalence be the fault in the memory cell array, and for example 1. fault is equivalent to stuck-open fault, and 2. fault is equivalent to multiple Write fault.

Fault in the read-write logic comprises with Types Below:

1. input, one or more fixed logic faults in the output lead;

2. one or more stuck-open faults in buffer or the latch;

3. the state coupling fault between any two in buffer or the latch.

The fault of read-write in the logic circuit also can equivalence be the fault in the memory cell array, and for example 1. fault is equivalent to the fixed logic fault, and 2. fault is equivalent to stuck-open fault, and 3. fault is equivalent to the state coupling fault.

(2) nine step checkerboard pattern methods

For above-mentioned memory inside cell fault model, the present inventor proposes a kind of algorithm that is called nine step checkerboard pattern methods, this algorithm need to be finished nine times to all memory cell of memory and read and write operation, so be called " nine steps ", staggered complementary because of the data that write consecutive storage unit again, be similar to chessboard, so be called " checkerboard pattern ", be collectively referred to as " nine step checkerboard pattern methods ". Nine step checkerboard pattern methods can be carried out full test to memory cell, decoding circuit and the read-write logic of memory, and it specifically carries out flow process shown in Fig. 6 and 7.

In Fig. 6 and Fig. 7, comprised 5 cyclic processes, below described in order:

Cyclic process 1

Address pointer points to the lowest address position, namely 0000 ... 00, this moment is through boundary scan cell, write the binary data 0101 of

n position

0 and 1 alternative arrangement to this address by the data wire of memory ... 01, then next contiguous high address of pointed, namely 0000 ... 01, write identical n bit binary data 0101 to this address ... 01, this process lasts till that address pointer travels through till all addresses from the low level to a high position. Here n is the figure place of memory data line.

Cyclic process 2

Then make address pointer again point to the lowest address position, then through boundary scan cell, data wire by memory read from this address the aforementioned data that write and with n bit binary data 0101 ... 01 relatively, if do not meet, shows that then the memory inside unit breaks down; Then write the binary data 1010 of

n position

1 and 0 alternative arrangement to this address ... 10. Next contiguous high address of pointed subsequently, namely 0000 ... 01, repeat in this address above-mentionedly to read, comparison and write operation. This process extends to address pointer always and points to till the highest addresses.

Cyclic process 3

Then make address pointer again point to the lowest address position, then through boundary scan cell, data wire by memory read from this address the aforementioned data that write and with n bit binary data 1010 ... 10 relatively, if do not meet, shows that then the memory inside unit breaks down; Then write the binary data 0101 of

n position

0 and 1 alternative arrangement to this address ... 01. Next contiguous high address of pointed subsequently, namely 0000 ... 01, repeat in this address above-mentionedly to read, comparison and write operation. This process extends to address pointer always and points to till the highest addresses.

Cyclic process 4

Obviously, when flow process shown in Figure 7 begins, address pointer points to highest address bit, namely 1111 ... 11, this moment is through boundary scan cell, data wire by memory read from this address the aforementioned data that write and with n bit binary data 0101 ... 01 relatively, if do not meet, shows that then the memory inside unit breaks down; Then write the binary data 1010 of

n position

1 and 0 alternative arrangement to this address ... 10. Next contiguous low order address of pointed subsequently, namely 1111 ... 10, repeat in this address above-mentionedly to read, comparison and write operation. This process extends to address pointer always and points to till the lowest order address.

Cyclic process 5

Then make address pointer again point to highest address bit, with by boundary scan cell, data wire by memory read from this address the aforementioned data that write and with n bit binary data 1010 ... 10 relatively, if do not meet, shows that then the memory inside unit breaks down; Then write the binary data 0101 of

n position

0 and 1 alternative arrangement to this address ... 01. Next contiguous low order address of pointed subsequently repeats in this address above-mentionedly to read, comparison and write operation. This process extends to address pointer always and points to till the lowest order address.

Therefore the operation result of cyclic process 1 is to write

logical value

0 or 1 to the high address to the memory cell that all addresses are pointed to from low order address. The operation result of cyclic process 2 is to read logical value and be that 0 memory cell writes logical value 1 and is that 1 memory cell writes logical value 0 to originally writing logical value to originally writing logical value from the memory cell that low order address points to all addresses to the high address. The operation result of cyclic process 3 is to read logical value and be that 1 memory cell writes logical value 0 and is that 0 memory cell writes logical value 1 to originally writing logical value to originally writing logical value from the memory cell that low order address points to all addresses to the high address. Can determine that by above-mentioned three cyclic processes fixed logic fault, stuck-open fault, 0 → 1 and 1 → 0 state translation exception and data keep fault. The operation result of cyclic process 4 is that the memory cell pointed to all addresses to low order address from the high address reads logical value and is that 0 memory cell writes logical value 1 and is that 1 memory cell writes logical value 0 to originally writing logical value to originally writing logical value. The operation result of cyclic process 5 is that the memory cell pointed to all addresses to low order address from the high address reads logical value and is that 0 memory cell writes logical value 1 and is that 1 memory cell writes logical value 0 to originally writing logical value to originally writing logical value. Can determine state coupling fault and multiple Write fault fully by above-mentioned 5 cyclic processes. In sum, nine step checkerboard pattern methods shown in Fig. 6 and 7 all are complete as testing algorithm to the test of all memory cell failure in the above-mentioned memory inside cell fault model (comprising fixed logic fault, stuck-open fault, state translation exception, state coupling fault and multiple Write fault).

C. read-only storage (ROM) internal element test

For ROM, owing to can't resemble the readable and writable memory to the internal element data writing, therefore need to adopt other method to test.

Fairly simple efficiently method is to compare with the verification of ROM with desired value, if conform to, judges that then the function of ROM is normal, otherwise judges that the data of ROM preservation are wrong.

Another method of testing is to compare according to sequence of addresses data being read out one by one with desired value from ROM, if the data that read conform to the data of expectation, judges that then the function of ROM is normal, otherwise judges that the data of ROM preservation are wrong. When comparing when testing completely ROM, needs should adopt the method.

Claims

1. a memory is characterized in that comprising following steps at board measuring method:

(1) memory is installed on the circuit board of band border scanning (BS) device, described boundary scanning device comprises by test data input (TDI) port, a plurality of boundary scan cell that is connected in series of device inside and boundary scan link that test data output (TDO) port consists of of being positioned at;

(2) each bar data wire, address wire or the control line with memory is connected with a described boundary scan cell;

(3) data wire, address wire or the control line through linking to each other with described boundary scan cell on described boundary scan link is with the data in test data write memory and/or the read memory; And

(4) data with the data that read and expectation compare to determine whether memory exists the type of fault and fault.

2. the method for claim 1, it is characterized in that described step (3) in the mode that comprises the following step with the data in test data write memory and the read memory:

I) by on the data wire to two arbitrarily different address write the data of full 0 and complete 1 and read data on these two addresses by data wire;

Ii) pass through on data wire to n inequality address A₀、A ₁……A _nWrite correspondingly n the data D that generates according to walking 1 algorithm₀、D ₁……D _nAnd read data on the described n address, wherein primary data D by data wire₀Be 100 ... 0;

Iii) pass through on data wire to a said n inequality address A₀、A ₁……A _nWrite correspondingly n the data D that generates according to walking 0 algorithm₀、D ₁……D _nReading said data line through the n-th addresses The data, wherein the initial data D₀To 011 ...... 1;

iv) in the data line to walking one algorithm according to the selected n-th order addresses A '₀、A′ ₁……A′ _nFollowed by writing n mutually different data D '₀、D′ ₁……D′ _nReading said data line through the n-number of address According to which the initial address A '₀To 000 ...... 0; and

v) in the data line in order to follow the selected algorithm carrying n 0 address A '₀、A′ ₁……A′ _nFollowed by writing n mutually different data D '₀、D′ ₁……D′ _nReading said data line through the n-number of address According to which the initial address A '₀111 ...... 1.

3 as claimed in claim 1, characterized in that said step (3) to include the steps of Way the test data written to memory and read data in memory:

i) through the data line is written to each of the n address bits 0 and 1 are alternately arranged in the binary data 0101 ...... 01, which is written sequentially from address to address high-low, n is the number of bits of data lines;

ii) through the data line data is read from each address is written to the n bits 1 and 0 are alternately arranged two 1010 ...... 10 binary data, which reads and writes sequentially from address to address low high;

iii) through the data line data is read from each address is written to the n bits 0 and 1 are alternately arranged in two 0101 ...... 01 binary data, which reads and writes sequentially from address to address low high;

iv) through the data line data is read from each address is written to the n bits 1 and 0 are alternately arranged two 1010 ...... 10 binary data, which reads and writes sequentially from address to address high-low; and

v) through the data line data is read from each address is written to the n bits 0 and 1 are alternately arranged in a binary System Data 0101 ...... 01, which reads and writes sequentially from address to address high-low.

4 as claimed in claim 1, characterized in that said memory is a read only memory (ROM), said step (3) the test data will be written into the memory and / or reading of data within the memory of the square Type of data lines in accordance with the sequence of addresses through all the addresses read from the ROM all data.

5 as claimed in claim any one of claims 1-4, characterized in that the boundary scan device accord Co IEEE 1149.1 standard.