CN1737801A - Data storage structure and method - Google Patents
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- CN1737801A CN1737801A CN 200510103650 CN200510103650A CN1737801A CN 1737801 A CN1737801 A CN 1737801A CN 200510103650 CN200510103650 CN 200510103650 CN 200510103650 A CN200510103650 A CN 200510103650A CN 1737801 A CN1737801 A CN 1737801A
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Abstract
The invention relates to a data storage structure for improving data access efficiency and a data storage method for improving data error coverage rate, wherein the data storage structure comprises: a plurality of groups of data sector bytes which are respectively stored in a plurality of groups of storage positions in a flash memory; and a plurality of groups of data correction bytes which are respectively calculated and generated by the plurality of groups of data section bytes and are respectively stored in another plurality of groups of storage positions separated by the plurality of groups of storage positions in an interleaving storage mode, and form a basic access data page together with the plurality of groups of data section bytes. Such a data storage structure can save data access time without increasing any cost. The data storage method respectively generates a data correction byte containing at least two groups of data correction codes according to any group of data sector bytes, thereby improving the error coverage rate.
Description
Technical field
The present invention relates to a kind of data storing structure and method, the particularly a kind of data access the improved usefulness in the flash memory (flashmemory) and the data storing structure and method of wrong coverage rate of being applied to.
Background technology
Now flash memory is widely used in the trend of consumption electronic products, already more and more obvious.But, because of being subject to the sequential access project organization of flash memory, unless flash memory itself can provide part to read (partial read) and write (partial write) function to improve access usefulness with part, otherwise, all can't significant effective improve access efficiency with the memory structure and the access method of data in the present known access flash memory.This situation more and more stressing the epoch that high-speed data is handled, obviously still has sizable room for improvement.
The data access of flash memory, normally with a basic access data page (page) as basic data access unit.Wherein, consider the amount of capacity difference of flash memory, the access data content of basic access data page promptly can be and then different.For example, at the flash memory of low capacity, the access data content of its basic access data page (being called for short 512pages) can be: (512bytes+16bytes); Wherein, 512bytes refers to the total bytes of all data segments bytes, and 16bytes then is used as the usefulness that storage data is proofreaied and correct byte.Certainly, producing the normal use-pattern of adjustment of data byte at present, is the content according to the data segments byte, and (Error Correction Code, ECC), but actual embodiment should be not limited thereto to calculate bug patch code by algorithm.As for the flash memory of high power capacity, the access data content of its basic access data page (abbreviating 2kpages as) then can be: (2k bytes+64bytes); Wherein, 2k bytes refers to the total bytes of all data segments bytes, and 64bytes then is used as the usefulness that storage data is proofreaied and correct byte.
See also Fig. 1, it is the memory structure synoptic diagram of data in the known access flash memory.That is to say, Figure 1 shows that the memory structure synoptic diagram of a basic access data page P1 who includes four group data area section byte S11～S14 and four groups of adjustment of data byte E11～E14.Wherein, described four group data area section byte S11～S14 are in order to four groups of storage datas of expression flash memory.In addition, stored contents according to described four group data area section byte S11～S14, with by producing bug patch code, or other can or store wrong algorithm (it is all a known technology) in order to detection or corrigendum data transmission, and produces corresponding described four groups of adjustment of data byte E11～E14 respectively.Therefore, as the basic access data page with 2k pages form is example, the storage volume of the arbitrary group data area section byte among then described four group data area section byte S11～S14, promptly should be respectively 512bytes, and the storage volume of arbitrary group of adjustment of data byte among described four groups of adjustment of data byte E11～E14 then should be respectively 16bytes.In addition, Fig. 1 does not illustrate, and also includes a data access impact damper, for reading out data or desire to write data to flash memory the time in flash memory, provides the pooling feature of data when carrying out access.But factor can be general known buffer according to the concrete enforcement structure of access buffer, so no longer given unnecessary details at this.
The shortcoming of memory structure shown in Figure 1 is, because of described four group data area section byte S11～S14 and described four groups of adjustment of data byte E11～E14, is arranged to be stored in the different storage location in left and right both sides in order.Thus, when the data of certain partial data section byte read in desiring only at this basic access data page P1, be subject to the sequential access project organization of flash memory, and suppose that the end of flash memory own can provide part to read to write function with part, then obviously still needs unnecessary data section byte or adjustment of data byte are continued to read in this data access impact damper.For example, suppose that a microprocessor (not shown) is in certain work event (event), when only needing to use this second group data area section byte S12, because of the storage location of its corresponding this second group of adjustment of data byte E12 is arranged at the storage location of the 3rd, the 4th group data area section byte S13, S14 and the storage location rear of this first group of adjustment of data byte E11.Therefore, when this microprocessor according to the data sequential access characteristic of flash memory after in order this first, second group data area section byte S11, S12 being read in this data access impact damper, in order to want to obtain this second group of adjustment of data byte E12, verify whether this second group data area section byte S12 the error in data phenomenon once took place in the data access process or between the storage life, obviously after need waiting until that promptly the 3rd, the 4th group data area section byte S13, S14 and this first group of adjustment of data byte E11 are read in the lump, can obtain this second group of adjustment of data byte E12.Thus, carry out access action with the known memory structure of Fig. 1 and will certainly waste some extra access times, and the storage area of this data access impact damper also will prepare to hold the storage area of all total amount of bytes of this basic access data page P1 at least, and the side is enough to deal with extreme practical application example.
Although, when known memory structure collocation shown in Figure 1 is had part and reads to write the flash memory of function with part, discuss with above-mentioned example, still need to move at least a position indicator pointer (pointer) (it is in order to the storage location of unlabeled data) twice, can finish the access action of access this second group data area section byte S12 and this second group of adjustment of data byte E12 in regular turn.
On the other hand, because of described four groups of adjustment of data byte E11～E14 are calculated in order to the algorithm that produces bug patch code (ECC) through one separately by described four group data area section byte S11～S14 respectively, and because of bug patch code can only detect a bit-errors usually, this obviously also can make the wrong coverage rate (Error Coverage Rate) of known memory structure effectively promote.Though existing at present comparatively complicated bug patch code produces algorithm and is suggested to wish to improve wrong coverage rate,, use the required cost of paying of this comparatively complicated algorithm, promptly be the processing time that need significantly increase data.This result obviously also disagrees with the requirement of present high-speed data processing.
Therefore, propose fundamental purpose of the present invention, promptly be desirable to provide a kind of not increasing under the condition of cost, effectively improve the data storing structure and the method for data access usefulness.
Propose another object of the present invention, promptly be desirable to provide and a kind ofly can under the situation that increases data processing time not significantly, effectively improve the data storing structure and the method for error in data coverage rate.
Summary of the invention
The present invention relates to a kind of data storing structure, comprise: multi-group data section byte is stored in respectively in the many groups storage location in the flash memory; Wherein, the space distribution each interval one suitable distance of described wantonly two groups of storage locations; And multi-group data is proofreaied and correct byte, calculate generation by described multi-group data section byte respectively, and be stored in another many group storage locations of coming out by described many group storage locations institute interval respectively with staggered storing mode, with described multi-group data section byte formation one basic access data page jointly.
According to data storing structure of the present invention, wherein arbitrary group data area section byte comprises 512 groups of bytes, and arbitrary group of adjustment of data byte comprises 16 groups of bytes, or arbitrary group data area section byte comprises 256 groups of bytes, and arbitrary group of adjustment of data byte comprises 8 groups of bytes.
According to data storing structure of the present invention, wherein arbitrary group of adjustment of data byte comprises at least two group adjustment of data sign indicating numbers, by the generation that partial bytes is calculated in its corresponding certain data blocks byte, and described at least two group adjustment of data sign indicating numbers are all a bug patch code with respectively.
According to data storing structure of the present invention, wherein provide the storage area of the employed data access impact damper of this flash memory, for the gulp of single data segments byte and single adjustment of data byte is counted summation.
Another preferable way of the present invention, be about a kind of in order to improve the data storage method of data access usefulness, comprise the following step: store in one first group data area section byte to a flash memory; Storage corresponds to one first group of adjustment of data byte of this first group data area section byte; Wherein, the storage location of the storage location of this first group of adjustment of data byte and this first group data area section byte is right after adjacent; Store one second group data area section byte; Wherein, the storage location of the storage location of this second group data area section byte and this first group of adjustment of data byte is right after adjacent; Storage corresponds to one second group of adjustment of data byte of this second group data area section byte; Wherein, the storage location of the storage location of this second group of adjustment of data byte and this second group data area section byte is right after adjacent; And repeat the above-mentioned adjacent staggered storing mode that is right after, store other group data area section byte and corresponding adjustment of data byte respectively, until forming a basic access data page.
According to of the present invention in order to improve the data storage method of data access usefulness, wherein arbitrary group of adjustment of data byte comprises at least two group adjustment of data sign indicating numbers, by the generation that partial bytes is calculated in its corresponding certain data blocks byte, and described at least two group adjustment of data sign indicating numbers are all a bug patch code with respectively.
Another preferable way of the present invention, be about a kind of in order to improve the data storing structure of error in data coverage rate, comprise: multi-group data section byte is stored in respectively in the many groups storage location in the flash memory; And multi-group data correction byte, calculate generation by described multi-group data section byte respectively, and be stored in another many group storage locations respectively; Wherein, arbitrary group of adjustment of data byte comprises at least two group adjustment of data sign indicating numbers, and described multi-group data is proofreaied and correct byte and described multi-group data is proofreaied and correct the common basic access data page that forms of byte.
According to of the present invention in order to improve the data storing structure of error in data coverage rate, wherein arbitrary group data area section byte comprises 512 groups of bytes, and arbitrary group of adjustment of data byte comprises 16 groups of bytes, or arbitrary group data area section byte comprises 256 groups of bytes, and arbitrary group of adjustment of data byte comprises 8 groups of bytes.
According to of the present invention in order to improve the data storing structure of error in data coverage rate, the storage location of wherein arbitrary group data area section byte is right after the storage location adjacent at least one group of adjustment of data byte, forms a staggered storing mode between the byte each other so that described multi-group data section byte and described multi-group data are proofreaied and correct.
Wherein provide the storage area of the employed data access impact damper of this flash memory according to of the present invention in order to improve the data storing structure of error in data coverage rate, for the gulp of single data segments byte and single adjustment of data byte is counted summation.
Description of drawings
Fig. 1 is the memory structure synoptic diagram of data in the known access flash memory.
Fig. 2 (a) is of the present invention one first preferable enforcement topology example figure.
Fig. 2 (b) is of the present invention one second preferable enforcement topology example figure.
Fig. 3 is of the present invention one the 3rd preferable enforcement topology example figure.
Fig. 4 is the step synoptic diagram of a preferable implementation method of the present invention.
Wherein, description of reference numerals is as follows:
Fig. 1:
Basic access data page P1
Data segments byte S11～S14
Adjustment of data byte E11～E14
Fig. 2 (a), Fig. 2 (b)～Fig. 4:
Basic access data page P2, P3
Data segments byte S21～S24, S31～S34
Adjustment of data byte E21～E24, E31～E34
Partial data section byte S21a～S24b, S31a～S34b
Partial data is proofreaied and correct byte E21a～E24b, E31a～E34b
Embodiment
For solving the on business restriction of primary data memory structure, cause when the access flash memory, taking place the not remarkable phenomenon of data access usefulness, the present invention proposes a kind of new data storing structure.See also Fig. 2 (a), it is the of the present invention first preferable enforcement topology example figure.Basic access data page P2 shown in Fig. 2 (a) includes four group data area section byte S21～S24 and four groups of adjustment of data byte E21～E24.As the basic access data page with basic access data page (abbreviating 2k pages as) form is that example is done an explanation, the storage volume of the arbitrary group data area section byte among then described four group data area section byte S21～S24 should be respectively 512bytes, and the storage volume of arbitrary group of adjustment of data byte among described four groups of adjustment of data byte E21～E24 then is respectively 16bytes.
From Fig. 2 (a) the storage location arrangement of relevant data promptly as can be known, described four group data area section byte S21～S24 and described four groups of adjustment of data byte E21～E24 store with interlace mode.That is, described four group data area section byte S21～S24 are stored in the flash memory four groups respectively to each other in the storage location of a suitable distance.In addition, described four groups of adjustment of data byte E21～E24 be stored in respectively by the storage location of described four group data area section byte S21～S24 another many group storage locations of coming out at interval.With Fig. 2 (a) is example, and the storage location of arbitrary group of adjustment of data byte can be right after the storage location adjacent at least one group data area section byte.
The benefit of memory structure is shown in Fig. 2 (a), when a microprocessor (not shown) in certain work event, when only needing to use certain single certain data blocks byte, because of being right after adjacent each other with the corresponding adjustment of data byte of this single certain data blocks byte, this microprocessor obviously can be finished data access work fast under the situation that needn't read in these data segments bytes that do not use and adjustment of data byte.For example, when supposing that this microprocessor only needs to use this second group data area section byte S22 in certain work event, because of the storage location of its corresponding this adjustment of data byte E22 is arranged at the storage location rear that is right after adjacent to this second group data area section byte S22.So, after this microprocessor reads in this data access impact damper with this first group data area section byte S21 and this first group of adjustment of data byte E21 in order according to the data sequential access characteristic of flash memory, can obtain this second group data area section byte S22 and this adjustment of data byte E22 corresponding with it at once.Thus, getting final product the 3rd, the 4th group data area section byte S23, S24 and this third and fourth group adjustment of data byte E23, the E24 that will not use that needn't lose time reads in the lump.Thereby this first preferable enforcement structure can more be saved data time than known memory structure shown in Figure 1 needn't increasing under any condition of cost.Certainly, if this first preferable enforcement structure applications is read and part when writing the flash memory of function in having part, compare with known memory structure shown in Figure 1, obviously only need to move the work that this position indicator pointer can be finished access this second group data area section byte S22 and this adjustment of data byte E22 for 1 time faster.In brief, when this first preferable enforcement structure collocation is had part and reads to write the flash memory of function with part, also can save data time effectively.
In addition, in order further to save the required storage area of this data access impact damper, then cooperating this first preferable enforcement structure when carrying out the data access of this basic access data page P2, obviously only the storage area of total amount of byte that needs to prepare to hold single data segments byte adjustment of data byte corresponding with it is promptly enough, and needn't prepare to hold the storage area of all total amount of bytes of this basic access data page P2.Easy speech, when utilizing this first preferable enforcement structure proposed by the invention to carry out data access, also can save the implementation cost of data in the access flash memory in the lump.
Moreover for improving the shortcoming that known memory structure can't effectively improve the error in data coverage rate, the second preferable enforcement structure that the present invention now proposes shown in Fig. 2 (b) solves this problem.That is, the inventive concept of this first preferable enforcement structure shown in the extension bitmap 2 (a), four group data area section byte S21～S24 described in Fig. 2 (a) are distinguished respectively again becomes 8 group data area section byte S21a～S24b, and in described 8 group data area section byte S21a～S24b, can produce bug patch code thus respectively, or other can be in order to detect or corrigendum data transmission or the wrong algorithm of storage, to produce corresponding 8 groups of adjustment of data byte E21a～E24b separately.Certainly, in this second preferable enforcement structure, produce these adjustment of data bytes with the algorithm that can produce bug patch code, but in actual implementation process, be not limited to this.
Then, this basic access data page P1, the P2 shown in Fig. 1 and Fig. 2 (b) further is discussed again.When both all for example are the basic access data page of 2k pages form, according to operation principles in order to the algorithm that produces bug patch code, the storage volume of arbitrary group of adjustment of data byte needs to have at least among Fig. 1: (9+3) * 2=24bits (equaling 3 bytes), the side is enough to contain the bit-errors that arbitrary group data area section byte is taken place.Because the maximum storage capacity of four groups of adjustment of data byte F11～E14 can reach 16bytes respectively described in Fig. 1, obvious arbitrary group of adjustment of data byte all is enough to contain the bit-errors that corresponding data segments byte is taken place.This measure means that also arbitrary group data area section byte is all only used the usefulness of one group of adjustment of data byte as the detecting position mistake.
Otherwise,, be 8 group data area section byte S21a～S24b because of described four group data area section byte S21～S24 are distinguished into respectively with the memory structure shown in Fig. 2 (b).Thereby the storage volume of described 8 group data area section byte S21a～S24b should be reduced to 256bytes respectively.Simultaneously; storage volume in order to 8 groups of corresponding adjustment of data byte E21a～E24b of the described 8 group data area section byte S21a～S24b of corresponding protection; at least need to have: (8+3) * 2=22bits (promptly; should need at least to store with 3 bytes), the side is enough to contain respectively the bit-errors that described 8 group data area section byte S21a～S24b are taken place.Because the maximum storage capacity of four groups of adjustment of data byte E21～E24 is respectively 16bytes described in Fig. 2 (b), the maximum storage capacity of then described 8 groups of corresponding adjustment of data byte E21a～E24b promptly is respectively 8bytes.Thus, described 8 groups of corresponding adjustment of data byte E21a～E24b also should be enough to contain respectively the bit-errors that described 8 group data area section byte S21a～S24b are taken place.In brief, described four group data area section byte S21～S24 obviously come the generation of detecting position mistake with two groups of adjustment of data bytes (E21a, E21b)～(E24a, E24b) all separately.These ways, the wrong coverage rate that can make memory structure shown in Fig. 2 (b) improves more than 1 times at least than the wrong coverage rate of known memory structure shown in Figure 1.
Certainly, about another preferable way of the present invention, also the enforcement notion shown in Fig. 2 (b) can be combined with known memory structure shown in Figure 1, to obtain one the 3rd preferable enforcement topology example figure as shown in Figure 3.That is, in known memory structure shown in Figure 1, when improving wrong coverage rate as desire, obviously must be shown in Fig. 2 (b), in including the basic access data page P3 of four group data area section byte S31～S34 and four groups of adjustment of data byte E31～E34, described four group data area section byte S31～S34 are distinguished respectively again becomes 8 group data area section byte S31a～S34b, and calculate respectively and produce corresponding 8 groups of adjustment of data bit code E31a～E34b, with the wrong coverage rate of effective raising known memory structure shown in Figure 1.
Now, be organized into detailed step synoptic diagram as shown in Figure 4, illustrated and realize notion of the present invention with another angle again with the relevant of the present invention first preferable implementation method:
Step 41: beginning;
Step 42: store this first group data area section byte S21 to this flash memory;
Step 43: store this first group of adjustment of data byte E21 that corresponds to this first group data area section byte S21; Wherein, the storage location of the storage location of this first group of adjustment of data byte E21 and this first group data area section byte S21 is right after adjacent;
Step 44: store this second group data area section byte S22; Wherein, the storage location of this second group data area section byte S22 and the storage location of this first group of adjustment of data byte E21 are right after adjacent;
Step 45: store this second group of adjustment of data byte E22 that corresponds to this second group data area section byte S22; Wherein, the storage location of the storage location of this second group of adjustment of data byte E22 and this second group data area section byte S22 is right after adjacent;
Step 46: repeat the above-mentioned adjacent staggered storing mode that is right after, store other group data area section byte S23, S24 and corresponding adjustment of data byte E23, E24 respectively, until forming this basic access data page P2; And
Step 47: finish.
In sum, by way of the present invention, obviously can reach the purpose of improving data access usefulness and wrong coverage rate easily increasing not significantly under processing time and the condition of cost.
The present invention can carry out various modifications by those of ordinary skill in the art, but the scope that neither disengaging claims are protected.
Claims (10)
1, a kind of data storing structure comprises:
Multi-group data section byte is stored in respectively in the many groups storage location in the flash memory; And
Multi-group data is proofreaied and correct byte, calculate generation by described multi-group data section byte respectively, and be stored in another many group storage locations of coming out by described many group storage locations institute interval respectively with staggered storing mode, with described multi-group data section byte formation one basic access data page jointly.
2, data storing structure as claimed in claim 1, it is characterized in that arbitrary group data area section byte comprises 512 groups of bytes, and arbitrary group of adjustment of data byte comprises 16 groups of bytes, or arbitrary group data area section byte comprises 256 groups of bytes, and arbitrary group of adjustment of data byte comprises 8 groups of bytes.
3, data storing structure as claimed in claim 1, it is characterized in that, arbitrary group of adjustment of data byte comprises at least two group adjustment of data sign indicating numbers, by the generation that partial bytes is calculated in its corresponding certain data blocks byte, and described at least two group adjustment of data sign indicating numbers are all a bug patch code with respectively.
4, data storing structure as claimed in claim 1 is characterized in that, the storage area of the employed data access impact damper of this flash memory is provided, for the gulp of single data segments byte and single adjustment of data byte is counted summation.
5, a kind of in order to improve the data storage method of data access usefulness, comprise the following step:
Store in one first group data area section byte to a flash memory;
Storage corresponds to one first group of adjustment of data byte of this first group data area section byte; Wherein, the storage location of the storage location of this first group of adjustment of data byte and this first group data area section byte is right after adjacent; And
Repeat above-mentioned steps, store other group data area section byte and corresponding adjustment of data byte respectively, until forming a basic access data page.
6, as claimed in claim 5 in order to improve the data storage method of data access usefulness, it is characterized in that, arbitrary group of adjustment of data byte comprises at least two group adjustment of data sign indicating numbers, by the generation that partial bytes is calculated in its corresponding certain data blocks byte, and described at least two group adjustment of data sign indicating numbers are all a bug patch code with respectively.
7, a kind of in order to improve the data storing structure of error in data coverage rate, comprise:
Multi-group data section byte is stored in respectively in the many groups storage location in the flash memory; And
Multi-group data is proofreaied and correct byte, calculates generation by described multi-group data section byte respectively, and is stored in another many group storage locations respectively; Wherein, arbitrary group of adjustment of data byte comprises at least two group adjustment of data sign indicating numbers, and described multi-group data is proofreaied and correct byte and described multi-group data is proofreaied and correct the common basic access data page that forms of byte.
8, as claimed in claim 7 in order to improve the data storing structure of error in data coverage rate, it is characterized in that, arbitrary group data area section byte comprises 512 groups of bytes, and arbitrary group of adjustment of data byte comprises 16 groups of bytes, or arbitrary group data area section byte comprises 256 groups of bytes, and arbitrary group of adjustment of data byte comprises 8 groups of bytes.
9, as claimed in claim 7 in order to improve the data storing structure of error in data coverage rate, it is characterized in that, the storage location of arbitrary group data area section byte is right after the storage location adjacent at least one group of adjustment of data byte, forms a staggered storing mode between the byte each other so that described multi-group data section byte and described multi-group data are proofreaied and correct.
10, as claimed in claim 7 in order to improve the data storing structure of error in data coverage rate, it is characterized in that, provide the storage area of the employed data access impact damper of this flash memory, for the gulp of single data segments byte and single adjustment of data byte is counted summation.
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| CN102024497A (en) * | 2009-09-22 | 2011-04-20 | 成都市华为赛门铁克科技有限公司 | Method for storing data and storage device |
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| CN102024497A (en) * | 2009-09-22 | 2011-04-20 | 成都市华为赛门铁克科技有限公司 | Method for storing data and storage device |
| CN102024497B (en) * | 2009-09-22 | 2013-10-02 | 成都市华为赛门铁克科技有限公司 | Method for storing data and storage device |
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