CN1731357A - Computer system and booting method thereof - Google Patents

Abstract

The invention provides a computer system and a starting method thereof. The computer system comprises a storage device for storing a starting system and a multitask core; and a microprocessor, coupled to the storage device, for loading the multitask core to execute the boot system.

Description

Computer system and booting method thereof

technical field

The present invention relates to a computer system and its booting method, in particular to a computer system and booting method which utilizes a multi-task core architecture to multi-task processing scalable firmware interface events.

Background technique

For existing computer systems, it includes a basic input/output system (basic input/output system, BIOS) to handle the boot process, that is, before the computer system loads and executes an operating system (operating system, OS), the basic The input/output system is responsible for the initialization of computer hardware, for example, the basic input/output system will check whether the hardware devices used by the computer system are connected normally and so on. For a long time, the basic input/output system is compiled by a low-level programming language (such as: assembly language). As is well known in the industry, the basic input/output system is generally stored in a read-only system on the motherboard of the computer system. In the read-only memory (ROM), the biggest advantage of doing this is that it can ensure that the contents of the basic input/output system will not be modified by other programs and affect the execution of the boot program. Yet existing basic input/output system has many shortcoming at present, for example, itself has no way to support computer system to provide the function of plug and play, but still needs the driver and input/output (Input/Output) of hardware. Output, IO) resources are adjusted.

In order to improve the defects of the existing BIOS, those skilled in the art have proposed an extensible firmware interface (EFI), intending to replace the current BIOS. The base of the scalable firmware interface is still the basic input/output system, and the link between the hardware and software related to the computer system is further standardized to give greater expansion in function. The scalable firmware interface is written in a high-level programming language (for example: C language), which is like a simplified operating system, between the hardware device of the computer system itself and the operating system. In addition, compared with the current There is a text interface of the basic input/output system, and the expandable firmware interface also provides a graphical operation interface, and the display mode provided by it is more understandable and practical for users. The function and operation of the XFI are described as follows.

During the boot process of the computer system, the workflow of the extensible firmware interface can be roughly summarized into the following steps: (1) startup; (2) initialization of the standard firmware platform; (3) loading of the extensible firmware interface and (4) select the operating system to be entered in the boot menu of the extensible firmware interface, and propose the boot code to the extensible firmware interface. Afterwards, the selected operating system will be loaded and executed to complete the boot process of the entire computer system.

However, in the booting process of the computer system, neither the existing BIOS nor the above-mentioned XFI can support the function of multi-tasking. Therefore, for the XFI In other words, when a microprocessor of a computer system, such as a central processing unit (CPU), receives a relatively high-priority event (event), it cannot immediately interrupt a relatively low-priority currently executing event. Priority events, but you must wait until the currently executing event is completed before you can execute the corresponding higher priority event. That is to say, because there is no multi-tasking mechanism, the application range of the scalable firmware interface is limited.

Contents of the invention

In view of this, one of the objectives of the present invention is to provide a computer system and a booting method that utilizes a multi-tasking core architecture to multi-task processing XFI events, so as to solve the above-mentioned problems.

According to the above purpose, the present invention provides a computer system capable of multi-tasking processing of extensible firmware interface events. The computer system includes: a storage device, used to store a boot system and a multi-tasking kernel (multi-tasking kernel); and a microprocessor (micro-processor), coupled to the storage device, used to load the A multitasking core to execute the boot system.

In addition, the present invention also provides a booting method capable of multitasking processing the event of the extensible firmware interface. The booting method includes: providing a multitasking kernel; and loading the multitasking kernel to execute the booting system.

Description of drawings

FIG. 1 is a functional block diagram of the computer system of the present invention.

FIG. 2 is a schematic diagram of multiple queues in the memory shown in FIG. 1 .

3 to 6 are schematic diagrams of different operating states of the memory shown in FIG. 2 .

FIG. 7 is a schematic diagram of the operation state of the memory shown in FIG. 2 when the microprocessor activates a masking mechanism.

FIG. 8 is another schematic diagram of multiple queues in the memory shown in FIG. 1 .

FIG. 9 is a schematic diagram of the operation state of the memory shown in FIG. 8 when the microprocessor activates a masking mechanism.

Description of reference symbols

10 Computer System 12 Hard Disk

14 Memory 16 Microprocessor

18a, 18b Hardware device 20 Operating system

22a, 22b, 22c Firmware 24 Expandable firmware interface

26 cores 40, 41, 42, 43 queues

50-56, 60, 71-77 events

Detailed ways

Please refer to FIG. 1 , which is a functional block diagram of a computer system 10 of the present invention. The computer system 10 includes a hard disk 12, a memory 14, a microprocessor (such as a central processing unit) 16 and a plurality of other hardware devices (such as an optical drive and a graphics card, etc.) 18a, 18b. For ease of illustration and simplification of illustration, only two other hardware devices 18a, 18b are shown in FIG. 1 . The hard disk 12 and the memory 14 are used as storage devices for the computer system 10, wherein the hard disk 12 stores an operating system (operating system, OS) 20, an extensible firmware interface (extensible firmware interface, EFI) 24, a firmware 22 and a real-time The operating system (μC/OS-II) kernel (kernel) 26; and the memory 14 is used to provide a storage space for temporarily storing data. The microprocessor 16 is coupled to the hard disk 12, the memory 14, and the hardware devices 18a, 18b. When the computer system 10 executes the boot program, the microprocessor 16 reads the core 26 and the extensible firmware interface 24 from the hard disk 12, and loads them into the memory 14; then, the microprocessor 16 reads and executes them from the memory 14. Core 26 and Extensible Firmware Interface 24 . In the latter part of the boot procedure, the microprocessor 16 will read the operating system 20 from the hard disk 12, and load it in the memory 14; finally, the microprocessor 16 will read and execute the operating system 20 from the memory 14, to Complete the entire boot procedure. Please note that, as mentioned above, the extensible firmware interface 24 is a single-tasking boot system used as the operating system 20 and the firmware 22a, 22b, 22c of the hard disk 12 and other hardware devices 18a, 18b communication medium between. As for the core 26, because it complies with the μC/OS-II architecture, in the disclosed embodiment of the present invention, the core 26 is a multi-tasking core. Please note that the scalable firmware interface 24 and the core 26 conforming to the μC/OS-II architecture are only preferred embodiments of the present invention, and any computer architecture that uses a multi-tasking core to perform a simplex boot system belongs to the scope of the present invention .

During the booting process, when the microprocessor 16 executes the XFI 24, it will generate a plurality of events that need to be processed and have different priorities, and each event corresponds to a specific priority. In this embodiment, four levels of priority are defined, which are: TPL_HIGH_LEVEL, TPL_NOTIFY, TPL_CALLBACK, and TPL_APPLICATION, and the priority levels decrease from TPL_HIGH_LEVEL to TPL_APPLICATION.

Please refer to FIG. 2 , which is a schematic diagram of multiple queues 40 , 41 , 42 , 43 in the memory 14 shown in FIG. 1 . As mentioned above, the core 26 has the function of multitasking, and conforms to the μC/OS-II architecture, and according to the μC/OS-II architecture, the microprocessor 16 will generate sixty-four in the memory 14 after executing the core 26. There are tasks T ₁ -T ₆₄ , which correspond to sixty-four different priority levels. Among them, tasks T ₃₀ , T ₃₁ , T ₃₂ , and T 33 point to four queues (queues) 40, 41, 42, _{and 43} respectively, and queue 40 is used to store events 50 corresponding to the highest priority TPL_HIGH_LEVEL; queue 41 is used to Store the events 51 and 52 corresponding to the second highest priority TPL_NOTIFY; the queue 42 is used to store the events corresponding to the second lowest priority TPL_CALLBACK, but in Figure 2, the queue 42 currently does not store any events; the queue 43 is used to store the corresponding lowest priority Events 53, 54, 55 of TPL_APPLICATION.

Compared with directly using the sixty-four tasks to store events, this embodiment only uses the four queues 40, 41, 42, and 43 respectively pointed to by tasks T ₃₀ , T ₃₁ , T ₃₂ , and T ₃₃ to store events. Such a design can increase the number of temporarily stored events and make the use of space more flexible. In addition, because the queue 42 does not store any events at present, it will be suspended (suspend), until the microprocessor 16 receives an event that cannot be executed immediately and the corresponding priority is the second lowest priority TPL_CALLBACK, then the queue 42 will be restarted. Enable (resume), and this event is then stored in the queue 42. Please note that there are many ways to indicate that a queue is suspended, one of which is that the microprocessor 16 sets a corresponding label S for each queue 40, 41, 42, 43, so that the microprocessor 16, it can be judged whether the queues 40, 41, 42, 43 are suspended or not from the values recorded in the respective volume labels S of the queues 40, 41, 42, 43. For example, the microprocessor 16 first presets the values of the respective labels S of the queues 40, 41, 42, and 43 to 0, and when the queue 42 is suspended due to not storing any events, the microprocessor 16 resets the queues to The value of the tag S of 42 is set to 1, and when the follow-up microprocessor 16 executes the events stored in the queue, the value 1 recorded by the tag S of the queue 42 can be used to know that the queue 42 does not store any events at present. Event, in a paused state.

Because queues 40, 41, 42, and 43 utilize the mechanism of First In First Out (First In First Out), so for the same queue, such as queue 43, when microprocessor 16 stores events 53 sequentially in execution queue 43 . The sequence of the queue 43 is the same, that is, the event 53 is executed first, then the event 54 is executed, and finally the event 55 is executed. As for the execution order of events of different priorities, the microprocessor 16 executes the events in the four queues 40, 41, 42, and 43 in order according to the priority from high to low. After the events in the queue are executed, the microprocessor 16 proceeds to execute the events in the queue with the next priority. Therefore, for events 50, 51, 52, 53, 54, 55 shown in FIG. Event 52, Event 53, Event 54, Event 55.

Next, with reference to FIG. 2 to FIG. 6 , the processing procedure when the microprocessor 16 receives an insertion event while executing an event will be described. 3 to 6 are schematic diagrams of different operating states of the memory 14 shown in FIG. 2 . After the microprocessor 16 executes the event 50 and puts the queue 40 in a suspended state, the microprocessor 16 then reads and executes the event 51 corresponding to the next highest priority TPL_NOTIFY. When the microprocessor 16 receives an insertion event such as 60 during the execution of the event 51, if the event 60 is a relatively low priority (such as TPL_APPLICATION) compared to the event 51, the event 60 will be stored in a relatively low priority. In the queue 43 of priority TPL_APPLICATION, and the execution order will be after the previously stored event 55 , at this time, the operation state of the memory 14 will be as shown in FIG. 3 . If event 60 is relatively a lower priority (such as TPL_CALLBACK) than event 51, but because the original queue 42 is in a suspended state because no event is stored, at this moment, queue 42 will be re-enabled, and The event 60 is stored in the queue 42, and the operation state of the memory 14 is shown in FIG. 4 . If the priority corresponding to the event 60 is the second highest priority TPL_NOTIFY, which is the same as the relative priority of the event 51, then the event 60 will be stored in the queue 41, and the execution sequence will be after the previously stored event 52, at this time , the operating state of the memory 14 is shown in FIG. 5 . If the priority corresponding to the event 60 is its highest priority TPL_HIGH_LEVEL, and its relative priority is higher than the second highest priority TPL_NOTIFY corresponding to the event 51, then the microprocessor 16 interrupts the event 51 in execution and executes the event 60 immediately, the above-mentioned The interrupted event 51 and its breakpoint BP are temporarily stored in a storage location TL in the memory 14 , and the operation state of the memory 14 at this time is shown in FIG. 6 . Subsequently, after the microprocessor 16 finishes executing the event 60, it will read the data of the event 51 and its breakpoint BP from the location TL of the memory 14, and continue to execute the event 51 from the breakpoint BP. task processing.

When the microprocessor 16 continues to receive and execute multiple events of relatively higher priority, or continues to execute events stored in relatively higher priority queues, it may not be executed for a period of time to relatively lower priority events. level events, in order to solve the above problems, the present invention also discloses a mask mechanism, which is used to provide an operation that is equivalent to temporarily increasing the priority of lower priority events, allowing the microprocessor 16 to adjust The execution order of the events, that is to say, when the microprocessor 16 starts the masking mechanism, after executing the currently executing events, it will skip the events of the second priority and execute the events of the third priority first. Event (Herein, the second priority is higher than the third priority.). Next, an example will be given to illustrate the detailed operation of the masking mechanism.

Please refer to FIG. 2 and FIG. 7 at the same time. FIG. 7 is a schematic diagram of the operation state of the memory 14 shown in FIG. 2 when the microprocessor 16 activates a masking mechanism. As shown in Figure 2, when the microprocessor 16 reads and executes the event 50 from the queue 40, if there is no event in the queue 40, and under the situation of not receiving and executing a new event, the microprocessor 16 will sequentially Execute event51, event52, event53, event54, event55. However, it is now desired that the microprocessor 16 executes the event 53 immediately after the current event 50 is executed. Therefore, it is necessary to start the masking mechanism to mask (mask) all other pending events that are higher than the lowest priority TPL_APPLICATION corresponding to the event 53. Events, that is, the events 51 and 52 stored in the shadow queue 41 , the operation state of the memory 14 at this time is shown in FIG. 7 . As for the queues 40, 42, they are suspended because they have not stored any events, so in this embodiment, the microprocessor 16 does not need to cover the queues 40, 42. Please note that there are many ways to mask a queue, one of which is that the microprocessor 16 sets a corresponding tag M for each queue 40, 41, 42, 43, and the microprocessor 16 can read from the tag The value of M determines whether it is shaded. For example, the microprocessor 16 first presets the values of the labels M of the queues 40, 41, 42, and 43 to 0, and when the queue 41 is blocked, the microprocessor 16 will set the value of the label M of the queue 41 to 0. The value is set to 1. In this way, after the microprocessor 16 executes the event 50, the value of the tag M of the queue 41 is 1 to know that the queue 41 is blocked, and the microprocessor 16 will jump directly. The event 53 is executed directly through the events 51 and 52 stored in the queue 41 . For further illustration, when the value of the tag S of the queue 40 is 1, the value of the tag M of the queue 41 is 1, and the value of the tag S of the queue 42 is 1, the microprocessor 16 can thus know its There is no need to read the queues 40, 41, 42, and the event 53 can be read directly from the queue 43 for execution.

Please refer to FIG. 8 and FIG. 9 at the same time. FIG. 8 is another schematic diagram of a plurality of queues 40, 41, 42, 43 in the memory 14 shown in FIG. A schematic diagram of the operating state of the device 16 when a masking mechanism is enabled. In FIG. 8 , queue 40 is suspended because no events are stored, queue 41 stores events 71 , 72 , queue 42 stores events 73 , 74 , and queue 43 stores events 75 , 76 , 77 . The microprocessor 16 reads and executes the event 71 from the queue 41. Then, if the microprocessor 16 does not receive and execute a new event, the microprocessor 16 would originally execute the events 72, 73, 74, 75, 76,77, yet, now hope that microprocessor 16 executes event 75 immediately after carrying out current event 71, therefore, promptly need cover all other pending events higher than the lowest priority level TPL_APPLICATION corresponding to event 75, also It is the events 72, 73, 74 stored in the shadow queues 41, 42, and the operating state of the memory 14 at this time will be as shown in FIG. 9 .

As mentioned above, the computer system and its booting method of the present invention can enable a multi-tasking mechanism to handle multiple events with different priorities when the booting program is executed, that is, when the microprocessor of the computer system receives a When a relatively higher priority event is executed, a relatively lower priority event in execution may be interrupted immediately to proceed with a relatively higher priority event. Compared with the prior art, the computer system and the boot method of the present invention can handle more events because of the use of queues; in addition, the computer system and the boot method of the present invention also provide a mask mechanism, which can temporarily improve the original Corresponds to the priority of lower priority events, so that the event can be executed earlier.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (18)

1. A computer system comprising: a storage device for storing a boot system and a multitasking kernel; and A microprocessor, coupled to the storage device, is used to load the multitasking core to execute the boot system. 2. The computer system as claimed in claim 1, wherein the microprocessor generates a plurality of queues corresponding to different priorities in the storage device for storing a plurality of events. 3. The computer system of claim 2, wherein the microprocessor removes an executed event corresponding to a priority from a queue storing the event. 4. The computer system of claim 2, wherein the microprocessor suspends a queue that does not store any event among the plurality of queues. 5. The computer system as claimed in claim 2, wherein if an interrupt event is received while the microprocessor is executing an event, and the priority corresponding to the interrupt event is higher than the priority corresponding to the event, the The microprocessor interrupts execution of the event to execute the insertion event immediately. 6. The computer system of claim 2, wherein the microprocessor activates a masking mechanism to mask an event with a relatively high priority and execute an event with a relatively low priority. 7. The computer system of claim 6, wherein if the microprocessor is executing an event in progress, the microprocessor executes the event with a relatively lower priority after the event in progress is completed. 8. The computer system as claimed in claim 2, wherein the multitasking core conforms to the core architecture of μC/OS-II, and the multiple queues correspond to a plurality of events in the core architecture, and the multiple events correspond to different priorities respectively. class. 9. The computer system as claimed in claim 1, wherein the boot system is an extensible firmware interface. 10. A booting method for a computer system, the computer system comprising a booting system, the booting method comprising the following steps: providing a multitasking core; and The multitasking kernel is loaded to execute the boot system. 11. The starting method according to claim 10, further comprising the steps of: Generate multiple queues corresponding to different priorities to store multiple events. 12. The starting method according to claim 11, further comprising the following steps: An executed event corresponding to a priority is removed from a queue storing the event. 13. The starting method according to claim 11, further comprising the steps of: Suspend a queue that does not hold any event among the plurality of queues. 14. The starting method according to claim 11, further comprising the following steps: If an insertion event is received while an event is being executed, and the priority corresponding to the insertion event is higher than the priority corresponding to the event, the execution of the event is interrupted to execute the insertion event immediately. 15. The starting method according to claim 11, further comprising the steps of: A masking mechanism is activated so that an event with a relatively high priority is masked and an event with a relatively low priority is executed. 16. The starting method according to claim 15, further comprising the steps of: If an executing event is being executed, the event with a relatively lower priority is executed after the executing event is completed. 17. The booting method according to claim 11, wherein the multitasking core conforms to the core architecture of μC/OS-II, and the multiple queues correspond to a plurality of events in the core architecture, and the multiple events correspond to different priorities respectively. class. 18. The booting method as claimed in claim 10, wherein the booting system is an extensible firmware interface.

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