CN1725511A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN1725511A CN1725511A CN200510079257.1A CN200510079257A CN1725511A CN 1725511 A CN1725511 A CN 1725511A CN 200510079257 A CN200510079257 A CN 200510079257A CN 1725511 A CN1725511 A CN 1725511A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 177
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 458
- 239000000758 substrate Substances 0.000 claims abstract description 125
- 239000011229 interlayer Substances 0.000 claims abstract description 122
- 230000007797 corrosion Effects 0.000 claims abstract description 118
- 238000005260 corrosion Methods 0.000 claims abstract description 118
- 238000000034 method Methods 0.000 claims abstract description 100
- 239000002184 metal Substances 0.000 claims abstract description 91
- 238000001312 dry etching Methods 0.000 claims description 193
- 238000001039 wet etching Methods 0.000 claims description 146
- 229920002120 photoresistant polymer Polymers 0.000 claims description 63
- 238000002161 passivation Methods 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 26
- 239000010409 thin film Substances 0.000 claims description 19
- 238000000992 sputter etching Methods 0.000 claims description 11
- 239000003989 dielectric material Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims 6
- 238000009413 insulation Methods 0.000 abstract description 96
- 238000001035 drying Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 description 71
- 239000000463 material Substances 0.000 description 50
- 239000011248 coating agent Substances 0.000 description 46
- 238000000576 coating method Methods 0.000 description 46
- 229910021417 amorphous silicon Inorganic materials 0.000 description 32
- 239000000203 mixture Substances 0.000 description 26
- 229920000642 polymer Polymers 0.000 description 23
- 239000012535 impurity Substances 0.000 description 22
- 239000000243 solution Substances 0.000 description 22
- 238000002425 crystallisation Methods 0.000 description 15
- 230000008025 crystallization Effects 0.000 description 15
- 239000011521 glass Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 12
- 229920003023 plastic Polymers 0.000 description 11
- 239000004033 plastic Substances 0.000 description 11
- 230000003628 erosive effect Effects 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
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- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
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- 150000004767 nitrides Chemical class 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 230000018044 dehydration Effects 0.000 description 4
- 238000006297 dehydration reaction Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- -1 gate electrode Substances 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
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Abstract
The present invention relates to a semiconductor device and a manufacturing method thereof. When a contact hole of a semiconductor layer and a source and drain electrode, a through-hole of a positive electrode and the source and drain electrode, a through-hole between connecting metal lines or a contact hole of the through-holes, are formed, at least one type of dry-process corrosion of high corrosion rate and high selectivity is used for dry-process corrosion; wet-process corrosion is adopted in the final corrosion treatment, so as to form the contact holes, the through-holes or the contact holes of the through-holes, which are provided with various conical angles and a plurality of contours; residues that are produced by corrosion can be completely eliminated in the wet-process and dry-process treatment; therefore, the contact holes, the through-holes or the contact holes of the through-holes have excellent contact characteristics. The semiconductor device comprises a substrate, a film transistor that is formed on the substrate and is provided with a semiconductor layer, a grid insulation layer, a grid electrode and a interlayer dielectric, and contact holes that penetrates the grid insulation layer and the interlayer dielectric, is exposed on the surface of the semiconductor layer and is provided with a plurality of contours. The upper part of the contact holes is provided with a contour for the wet-process corrosion; and the lower part has at least one of the contours for the wet-process corrosion and the dry-process corrosion.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, more specifically, relate to a kind of semiconductor device and manufacture method thereof, this manufacture method comprises: when the contact hole that forms semiconductor layer and source and drain electrode, the through hole of positive electrode and source and drain electrode, through hole between the metal interconnecting wires, or during the through hole contact hole, use at least a dry etching in high corrosion rate dry etching and the high selectivity dry etching and in final corrosion process, carry out wet etching, so that contact hole, through hole or through hole contact hole can be formed the multiple profile with different coning angles, and when carrying out the wet method dry process, just can remove the etching residue that produces because of corrosion fully, just can make contact hole thus, through hole and through hole contact hole have good contact performance.
Background technology
Usually, silicon thin film transistor (TFT) is applied to large-area integrated circuit (IC), for example flat-panel monitor, imageing sensor, photocopier, printer, scanner or the like.
The example of flat-panel monitor comprises LCD (LCD), organic electroluminescent (EL) device etc., and the typical technology of flat-panel monitor is an organic EL device, it mainly is divided into active matrix organic EL device and passive matrix organic EL device, wherein by active device for example thin-film transistor control each pixel in the active matrix organic EL device, so that it is being better than the passive matrix organic EL device aspect speed, visual angle and the contrast, just can realize having very high-resolution screen thus.
The major reason that silicon TFT is used for organic EL device is: can handle under 400 ℃ or lower low temperature, the stability of device property can be very good, and can easily implement integrated on large-area glass substrate.
Figure 1A and 1B are the profiles that illustrates according to the manufacture method of the contact hole of the TFT of prior art.
At first, Figure 1A shows the process profile that forms resilient coating, semiconductor layer, gate insulation layer, gate electrode and interlayer dielectric on substrate.Shown in Figure 1A, resilient coating 12 by dielectric substrate 11 for example plastics or silicon oxide layer or silicon nitride layer on glass form, form amorphous silicon layer then.Make the amorphous silicon layer crystallization, to form polysilicon layer, this polysilicon layer of composition is to form semiconductor layer 13 then.Then, form gate insulation layer 14 on the whole surface of substrate, deposit thereon is used to form the material of gate electrode, and this material of composition is to form gate electrode 15 then.Subsequently, on the whole surface of substrate, be formed for the interlayer dielectric 16 of protecting following element or making following element insulating by silicon oxide layer or silicon nitride layer.
Then, Figure 1B shows the process profile that adopts the photoresist figure and form contact hole on substrate.Shown in Figure 1B, be formed for covering substrate whole surface photoresist and be used for the photoresist figure 17 of opening being carried out in the zone to be formed of contact hole by exposure process, and use this photoresist figure dry etching photoresist, to form contact hole 18.Then, remove the photoresist figure, use the electric conducting material filling contact hole, formation source and drain electrode (not shown) on interlayer dielectric.
Yet, in the method for above-mentioned formation contact hole, as shown in Figure 2, dry etching can be below contact hole 18 formation polymer 21, contact hole 18 has penetrated interlayer dielectric 17 and gate insulation layer 14 and has exposed the surface of semiconductor layer 13, so that needs specific polymer removal solution to remove polymer, causes increasing the operation of removing polymer, and, thereby make contact resistance inhomogeneous because of excessive erosion 22 will damage the surface of semiconductor layer.
Summary of the invention
Therefore, the present invention has just solved the problems referred to above relevant with conventional device by a kind of semiconductor device and manufacture method thereof are provided, when the contact hole that forms semiconductor layer and source and drain electrode, the through hole of positive electrode and source and drain electrode, through hole between metal interconnecting wires, or during the through hole contact hole, use at least a dry etching in high corrosion rate dry etching and the high selectivity dry etching and in final corrosion treatment, carry out wet etching, so that can form the contact hole of multiple profile with different angle of taper, through hole or through hole contact hole, and when carrying out the wet method dry process, just can remove the etching residue that produces because of corrosion fully, just can make contact hole thus, through hole and through hole contact hole have good contact performance.
In one exemplary embodiment of the present invention, semiconductor device comprises: substrate; On substrate, form and have the thin-film transistor of semiconductor layer, gate insulation layer, gate electrode and interlayer dielectric; And penetrate the surface of gate insulation layer and interlayer dielectric and exposed semiconductor layer and have the contact hole of multiple profile, wherein the top of contact hole has wet etching profile and lower part and has at least a erosion profile in wet etching profile and the dry etching profile.
In another exemplary embodiment of the present invention, the manufacture method of semiconductor device comprises: form semiconductor layer, gate insulation layer, gate electrode and interlayer dielectric on substrate; On part interlayer dielectric and gate insulation layer, carry out at least once at least a processing in dry etching processing and the wet etching processing, to form the contact hole of desired depth; And wet etching has the contact hole of desired depth to finish contact hole, so that the etching residue that produces is also removed on the surface of exposed semiconductor layer simultaneously during corrosion treatment.
In another exemplary embodiment of the present invention, semiconductor device comprises: substrate; On substrate, form and have the thin-film transistor (TFT) of source and drain electrode; Passivation layer that on TFT, forms and planarization layer; And penetrate passivation layer and planarization layer and source of exposure and drain electrode and have the through hole of multiple profile, wherein the top of through hole has wet etching profile and lower part and has at least a erosion profile in wet etching profile and the dry etching profile.
In another exemplary embodiment of the present invention, the manufacture method of semiconductor device comprises: form the thin-film transistor (TFT) that comprises source and drain electrode on substrate; On TFT, form passivation layer and planarization layer; On part passivation layer and planarization layer, carry out at least once at least a processing in dry etching processing and the wet etching processing, to form the through hole of desired depth; And wet etching has the through hole of desired depth to finish this through hole, so that source of exposure and drain electrode are also removed the etching residue that produces simultaneously during corrosion treatment.
In another exemplary embodiment of the present invention, semiconductor device comprises: substrate; Metal interconnecting wires that on substrate, forms and interlayer dielectric; And penetrate interlayer dielectric and exposing metal interconnection line and have the through hole of multiple profile, wherein the top of through hole has wet etching profile and lower part and has at least a erosion profile in wet etching profile and the dry etching profile.
In another exemplary embodiment of the present invention, the manufacture method of semiconductor device comprises: form metal interconnecting wires and interlayer dielectric on substrate; On the part interlayer dielectric, carry out at least once at least a processing in dry etching processing and the wet etching processing, to form the through hole of desired depth; And wet etching has the through hole of desired depth to finish this through hole, so that the exposing metal interconnection line is also removed the etching residue that produces simultaneously during corrosion treatment.
In another exemplary embodiment of the present invention, semiconductor device comprises: substrate; The semiconductor layer that on substrate, forms, gate insulation layer and gate electrode; The planarization layer that on substrate, forms; And penetrate planarization layer and gate insulation layer and exposed semiconductor layer and have the through hole contact hole of multiple profile, wherein the top of through hole contact hole has wet etching profile and lower part and has at least a erosion profile in wet etching profile and the dry etching profile.
In another exemplary embodiment of the present invention, the manufacture method of semiconductor device comprises: form semiconductor layer, gate insulation layer and gate electrode on substrate; On substrate, form planarization layer; On part gate insulation layer and planarization layer, carry out at least once at least a processing in dry etching processing and the wet etching processing, to form the through hole contact hole of desired depth; And wet etching has the through hole contact hole of desired depth to finish this through hole contact hole, so that exposed semiconductor layer is also removed the etching residue that produces simultaneously during corrosion treatment.
In another exemplary embodiment of the present invention, semiconductor device comprises: substrate; The semiconductor layer that on substrate, forms, gate insulation layer, gate electrode and interlayer dielectric; Thin-film transistor (TFT) district that comprises contact hole, this contact hole penetrates the surface of gate insulation layer and interlayer dielectric, exposed semiconductor layer and has multiple profile, and wherein the top of contact hole has wet etching profile and lower part and has at least a erosion profile in wet etching profile and the dry etching profile; On substrate, form and separate out the metal interconnecting wires and the insulating barrier of a predetermined space with TFT; And the metal interconnected district that comprises through hole, this through hole penetrates insulating barrier and has multiple profile, and wherein the top of through hole has wet etching profile and lower part and has at least a erosion profile in wet etching profile and the dry etching profile.
In another exemplary embodiment of the present invention, the manufacture method of semiconductor device comprises: form semiconductor layer, gate insulation layer and gate electrode in thin-film transistor (TFT) district of substrate, and form metal interconnecting wires separating out in the metal interconnecting wires district of a predetermined space with TFT; In the TFT district, form interlayer dielectric, and in the metal interconnecting wires district, form insulating barrier; Carry out at least once at least a processing in dry etching processing and the wet etching processing on the part of the insulating barrier in the metal interconnecting wires district and interlayer dielectric in the TFT district and gate insulation layer, to form each contact hole that all has desired depth and through hole; And wet etching each all have the contact hole and the through hole of desired depth, thereby so that finish metal interconnecting wires in contact hole and the through hole exposing metal interconnection line district and the semiconductor layer in the TFT district and remove the etching residue that during corrosion treatment, produces simultaneously.
Description of drawings
With reference to the accompanying drawings and with reference to the exemplary embodiment of determining above-mentioned and further feature of the present invention is described, wherein:
Figure 1A and 1B are the profiles that illustrates according to the formation method of the contact hole of the TFT of prior art;
Fig. 2 is the profile that illustrates according to the problem of the formed contact hole of prior art;
Fig. 3 A-3E is the profile that contact hole formation method according to an embodiment of the invention is shown and uses the operation of this contact hole;
Fig. 4 A-4G is the profile that illustrates according to the contact hole formation method of other embodiments of the invention, and profile and the cross sectional photograph of using the operation of contact hole;
Fig. 5 A-5E illustrates according to through hole formation method of other embodiments of the invention and the profile that uses the operation of through hole;
Fig. 6 A-6E is the profile that through hole formation method according to still a further embodiment is shown and uses the operation of through hole;
Fig. 7 A-7E is the profile that through hole formation method according to still a further embodiment is shown and uses the operation of through hole;
Fig. 8 A-8E is the profile that through hole formation method according to still a further embodiment is shown and uses the operation of through hole;
Fig. 9 A-9E is the profile that through hole contact hole formation method according to still a further embodiment is shown and uses the operation of through hole contact hole;
Figure 10 A-10E is the profile that through hole contact hole formation method according to still a further embodiment is shown and uses the operation of through hole contact hole;
Figure 11 forms contact hole and the method for through hole and the profile that uses the semiconductor device of this contact hole and through hole when illustrating according to still a further embodiment; And
Figure 12 forms contact hole and the method for through hole and the profile that uses the operation of this contact hole and through hole when illustrating according to still a further embodiment.
Embodiment
By following detailed description with reference to accompanying drawing, the details of above-mentioned purpose of the present invention, its technical conceive and its operating effect will become obviously, represent exemplary embodiment of the present invention in the accompanying drawing.
(first embodiment)
Fig. 3 A-3E illustrates contact hole formation method according to an embodiment of the invention and uses this to contact the profile of lonely L from the spoon operation.
At first, Fig. 3 A is the process profile that forms resilient coating, semiconductor layer, gate insulation layer, gate electrode and interlayer dielectric on substrate.As shown in Figure 3A, at dielectric substrate 101 for example plastics or formation resilient coating 102 on glass.Resilient coating 102 plays and prevents to produce from insulating the steam of substrate or the effect of diffusion of impurities, perhaps plays when carrying out crystallization and just easily carries out the effect of the crystallization of semiconductor layer by adjusting heat conduction velocity.
Then, on resilient coating 102, form amorphous silicon layer, make this amorphous silicon layer crystallization become polysilicon layer or monocrystalline silicon layer then, it is carried out composition to form semiconductor layer 103.In the case, can use chemical vapor deposition (CVD) method or physical vapor deposition (PVD) method to amorphous silicon layer.In addition, when forming amorphous silicon layer or after forming amorphous silicon layer, can implement to make the amorphous silicon layer dehydration to reduce the operation of hydrogen concentration.
Then, be formed with therein on the whole surface of substrate of semiconductor layer and formed gate insulation layer 104, on gate insulation layer, be formed for forming the material of gate electrode, and this material of composition has been to have formed gate electrode 105.After forming gate electrode 105, can adopt gate electrode as mask, implement the operation of implanting impurity ion, carry out the operation of the source that in semiconductor layer, limits and drain region and channel region thus.
Then, form interlayer dielectric on the whole surface of substrate, this interlayer dielectric plays the effect that protection is formed on following element or these elements are electrically insulated from each other.
In the case, resilient coating, gate insulation layer and interlayer dielectric by oxide skin(coating) for example silicon oxide layer or nitride layer for example silicon nitride layer form.
Then, Fig. 3 B is the profile that the formation step of the photoresist figure that is used to form the contact hole on the substrate is described.Shown in Fig. 3 B, formed thereon on the substrate of resilient coating, semiconductor layer, gate insulation layer and gate electrode, be formed for forming the photoresist figure 107 of contact hole.
Photoresist figure 107 forms in one way, that is, adopt spin coating method or spraying method that it at first is coated on the substrate, and implement exposure and development treatment subsequently.
Then, thus Fig. 3 C is explanation forms the step of the contact hole with desired depth by a part of utilizing photoresist figure dry etching interlayer dielectric and gate insulation layer a profile.Shown in Fig. 3 C, adopt photoresist figure 107 dry etching interlayer dielectrics 106 and gate insulation layer 104, form contact hole 108 thus with desired depth.
In the case, as shown in the regional A and B of Fig. 3 C, can use to penetrate interlayer dielectric and only corrode the method for part gate insulation layer and only corrode dielectric method between part layer.Selectively, can use to penetrate interlayer dielectric but do not corrode gate insulation layer forming the method for contact hole, yet in same not shown the method.In other words, contact hole can be handled to form by dry etching has desired depth, this is can not damage the semiconductor layer that it forms down in order to handle by dry etching, for example polymer is attached to it with residue to prevent to be exposed semiconductor layer under it, and forms the profile (profile) of contact hole according to required form.
In addition, when implementing dry etching, can corrode interlayer dielectric and gate insulation layer with high corrosion rate, so that can adjust the coning angle (taper angle) of contact hole and the degree of depth of contact hole, and just contact hole can be corroded become to have almost perpendicular to cambial angle by dry etching of the present invention.In the case, the contact hole coning angle 109 that forms by dry etching just can be at 60 °-90 ° tolerance interval, preferably 75 °-90 ° scope.
In the case, for dry etching, can use ion etching to handle for example ion beam etching processing and radio frequency (RF) sputtering etching processing or for example reactive ion etching processing of reaction corrosion treatment.
Then, Fig. 3 D is that the explanation wet etching forms the profile of the contact hole of desired depth with the step on exposed semiconductor layer surface, finishes this contact hole thus.Shown in Fig. 3 D, finish the contact hole that is etched into desired depth by dry etching, with surface by wet etching exposed semiconductor layer 130.
In the case, as shown in the regional A of Fig. 3 D, can not remove the photoresist figure, the contact hole that can wet etching forms by dry etching, exposing the surface of semiconductor layer, and can form little contact hole coning angle 11O, perhaps as shown in the area B of Fig. 3 D by the isotropism wet etching, can remove the photoresist figure, and can form little contact hole coning angle by the isotropism wet etching.When implementing wet etching after removing the photoresist figure, thereby the surface of interlayer dielectric is corroded and trends towards reducing the thickness of interlayer dielectric, yet, just can not have problems when forming interlayer dielectric when considering above-mentioned state.
In the case, the coning angle (taper angle) of the contact hole that forms by wet etching just has 5 °-60 ° scope, preferred 5 °-45 ° scope.In addition, implement wet etching, so that adopt the etchant solution that has a high selectivity for interlayer dielectric or gate insulation layer to come the wet etching semiconductor layer, thereby even described semiconductor layer is not damaged by wet etching solution when exposing semiconductor layer surface, and can remove some polymer residues that produce on it.
Therefore, formed the contact hole 114 with two kinds of profiles, so that the top of contact hole has the profile 111 that forms by wet etching, and the lower part of contact hole has the profile 112 that forms by dry etching.
Fig. 3 E is the profile of formation operation that adopts the TFT of the contact hole with above-mentioned two kinds of profiles.Shown in Fig. 3 E, on the whole surface of the substrate of the contact hole that has formed two kinds of profiles, deposit is used to form the material of source and drain electrode, and this material of composition with formation source and drain electrode 113, is finished TFT thus then.The result, contact hole between source and drain electrode and the semiconductor layer is formed by two kinds of profile contact holes 114, make the top of contact hole 114 have the wet etching profile and make its underpart have the dry etching profile, so that remove polymer residue fully, just can not have the contact resistance that causes because of residue, and can not corrode the surface of semiconductor layer, so that the surface of semiconductor layer can not be damaged, and two kinds of profiles of contact hole are easy to fill this contact hole with the formation material of source and drain electrode.
(second embodiment)
Fig. 4 A-4G shows the profile of contact hole formation method according to another embodiment of the invention, and profile and the cross sectional photograph of using the operation of this contact hole.
At first, Fig. 4 A is explanation forms the step of resilient coating, semiconductor layer, gate insulation layer, gate electrode and interlayer dielectric on substrate a profile.Shown in Fig. 4 A, at dielectric substrate 151 for example plastics or formation resilient coating 152 on glass.Resilient coating 152 plays and prevents to produce from insulating the steam of substrate or the effect of diffusion of impurities, perhaps plays when carrying out crystallization and just easily carries out the effect of the crystallization of semiconductor layer by adjusting heat conduction velocity.
Then, on resilient coating 152, form amorphous silicon layer, make this amorphous silicon layer crystallization then, forming polysilicon layer or monocrystalline silicon layer, and it is carried out composition, to form semiconductor layer 153.In the case, can use CVD method or PVD method to amorphous silicon layer.In addition, when forming amorphous silicon layer or after forming amorphous silicon layer, can implement to make the amorphous silicon layer dehydration to reduce the operation of hydrogen concentration.
Then, be formed with therein on the whole surface of substrate of semiconductor layer and formed gate insulation layer 154, on gate insulation layer 154, be formed for forming the material of gate electrode, and this material of composition, to form gate electrode 155.After forming gate electrode 155, can adopt the operation of gate electrode 155 as mask enforcement implanting impurity ion, carry out the operation of the source that in semiconductor layer, limits and drain region and channel region thus.
Then, form interlayer dielectric 156 on the whole surface of substrate, this interlayer dielectric 156 is to the effect of protecting its element that descends to form or making the element electrically insulated from one another.
In the case, resilient coating 152, gate insulation layer 154 and interlayer dielectric 155 by oxide skin(coating) for example silicon oxide layer or nitride layer for example silicon nitride layer form.
Under necessary situation, resilient coating 152 will be formed, so that when not needing resilient coating 152, then it can be do not formed.
Then, Fig. 4 B is the profile that the formation step of the photoresist figure that is used to form the contact hole on the substrate is described.Shown in Fig. 4 B, formed thereon on the substrate of resilient coating, semiconductor layer, gate insulation layer and gate electrode, be formed for forming the photoresist figure 157 of contact hole.
Following formation photoresist figure 157 at first adopts spin coating method or spraying method that it is coated on the substrate, and implements exposure and development treatment subsequently.
Then, Fig. 4 C is explanation with the part of high corrosion rate dry etching interlayer dielectric and the gate insulation layer profile with step with first degree of depth.Shown in Fig. 4 C, adopt photoresist figure 157, with high corrosion rate dry etching interlayer dielectric 156 and gate insulation layer 154, form first contact hole 158 thus with first degree of depth.
In the case, as shown in the regional A and B of Fig. 4 C, can use to penetrate interlayer dielectric and only corrode the method for part gate insulation layer and only corrode dielectric method between part layer.Selectively, can use to penetrate interlayer dielectric but do not corrode gate insulation layer forming the method for contact hole, yet in same not shown the method.In other words, can form contact hole by the dry etching of high corrosion rate with desired depth, this is can not damage the semiconductor layer that it forms down in order to handle by dry etching, prevent that semiconductor layer under it is exposed and can the residual polymer that for example adheres on it, and form the profile of contact hole according to required form.
In addition, because high corrosion rate, dry etching interlayer dielectric and gate insulation layer apace.In the case, the coning angle 159 of first contact hole with first degree of depth that forms by dry etching just can be at 30 °-70 ° tolerance interval, preferably 30 °-50 ° scope.
In the case, dry etching for high corrosion rate, can use ion etching to handle for example ion beam etching processing and radio frequency (RF) sputtering etching processing, or for example reactive ion etching processing and inductively coupled plasma etching processing of reaction corrosion treatment.
Then, Fig. 4 D illustrates that being corroded according to the mode dry etching that has high selectivity for semiconductor layer is the gate insulation layer of first degree of depth and the profile that interlayer dielectric has the step of second degree of depth thus.Shown in Fig. 4 D, corrode by high selectivity, corrosion has been etched into the gate insulation layer and the interlayer dielectric of first contact hole with first degree of depth according to the dry etching mode of high corrosion rate, so that semiconductor layer has the high selectivity for gate insulation layer and interlayer dielectric, forms second contact hole 160 with second degree of depth thus.In the case, keep the profile of first contact hole in the lower part of second contact hole, this comes from the following fact, and promptly the low while of the corrosion rate under the high selectivity forms of corrosion is for the corrosion selectivity height of gate insulation layer or interlayer dielectric.
In the case, the dry etching of high selectivity means for the corrosion rate of gate insulation layer and interlayer dielectric high and low for the corrosion rate of semiconductor layer, so that corrode gate insulation layer and interlayer dielectric and corrode semiconductor layer hardly by the high selectivity dry etching, and because why the petty photoresist figure that makes does not cave in, so the coning angle 161 of second contact hole with second degree of depth that forms by the high selectivity dry etching has almost perpendicular to the profile of adjacent layer, this coning angle is greater than the coning angle of first contact hole with first degree of depth.In other words, the coning angle of second contact hole with second degree of depth that forms by the high selectivity dry etching is 60 °-90 ° scope.In the case, preferably this coning angle 70 °-90 ° scope.
As shown in the regional A of Fig. 4 D, second contact hole with second degree of depth can be formed the degree of depth that does not expose semiconductor layer, perhaps as shown in the area B of Fig. 4 D, second contact hole with second degree of depth can be formed the degree of depth that exposes semiconductor layer.This is possible, because only corrode gate insulation layer and interlayer dielectric and corrode semiconductor layer hardly by the high selectivity dry etching, so that even damages the surface of semiconductor layer hardly when exposed semiconductor layer as shown in the area B of Fig. 4 D.Yet the high selectivity dry etching also can influence semiconductor layer as the case may be, so that the semiconductor layer corrosion can be the degree of depth that does not expose semiconductor layer shown in the regional A, has just primitively avoided its damaged or excessive erosion thus.
In the case, for the processing of high selectivity dry etching, for example the dry etching of high corrosion rate is handled, for example RF sputtering etching processing is handled in ion etching or for example reactive ion etching processing and inductively coupled plasma etching processing of reaction corrosion treatment can to use the ion beam etching processing.In addition, specifically do not limit in the present invention, yet suppose that the dry etching of high corrosion rate and high selectivity dry etching use ion etching to handle or the reaction corrosion treatment, and under the situation of high corrosion rate dry etching, adopt CF
4/ O
2Or SF
6/ O
2Gas adopts the C with high CF ratio under the situation of high selectivity dry etching
4F
8, CHF
3Or C
2HF
5Gas.
Then, Fig. 4 E is explanation to the regional wet etching that corrodes into the second degree of depth profile with the step that forms the 3rd contact hole.Shown in Fig. 4 E, first and second contact holes that the dry etching of wet etching by high corrosion rate dry etching and high selectivity forms to form the 3rd contact hole 162, are finished this contact hole like this.Wet etching can preferably adopt hydrofluoric acid (DHF) that wet etching solution for example dilutes or the hydrofluoric acid (BHF) that contains buffer, and this wet etching solution can not corrode semiconductor layer fully.Adopt this etchant solution to corrode the surface of semiconductor layer and the side of contact hole,, on semiconductor layer, just do not have impurity thus to remove impurity or the polymer residue on it.
In the case, as shown in the regional A of Fig. 4 E, can not remove the photoresist figure, can wet etching first and second contact holes that form of dry etching by high corrosion rate dry etching and high selectivity, with the surface that exposes semiconductor layer (perhaps, when exposing this surface, just increase each width of first and second contact holes), can form the coning angle 143 of the 3rd little contact hole by the isotropism wet etching, perhaps as shown in the area B of Fig. 4 E, the photoresist figure can be removed, and the coning angle of the 3rd little contact hole can be formed by the isotropism wet etching.When implementing wet etching after having removed the photoresist figure, thereby the surface of interlayer dielectric is corroded and trends towards reducing the thickness of interlayer dielectric, yet, when considering that above-mentioned state will form interlayer dielectric, just can not have problems.
In the case, the coning angle of the 3rd contact hole that forms by wet etching has 5 °-50 ° scope, preferably has 5 °-35 ° scope.In addition, implement wet etching, the etchant solution that has a high selectivity with respect to interlayer dielectric or gate insulation layer comes the wet etching semiconductor layer to apply, thus even when exposing or having exposed semiconductor layer surperficial, can not damage semiconductor layer fully by this wet etching solution, and can remove some polymer residues that produce on it yet.
The result, three kinds of profile contact holes that contain first, second and the 3rd contact hole have just been finished, like this, form with regard to the top that makes three kinds of profile contact holes have the wet etching profile, dry etching profile that dry etching profile that its middle body forms the high selectivity with big coning angle and its lower part form the high corrosion rate with roundlet cone angle.
Then, Fig. 4 F adopts the contact hole of above-mentioned three kinds of profiles to form the profile of the operation of TFT.Shown in Fig. 4 F, on the whole surface of the substrate that has formed the contact hole with above-mentioned three kinds of profiles, deposit is used to form the material of source and drain electrode, and this material of composition with formation source and drain electrode 164, is finished TFT thus then.The result, just will form three kinds of profile contact holes 165 at the contact hole between source and drain electrode and the semiconductor layer with high corrosion rate dry etching profile, wherein the top of three kinds of profile contact holes has the wet etching profile, its middle body has the dry etching profile of the high selectivity of big coning angle, and its lower part has the dry etching profile of the high corrosion rate of roundlet cone angle, so that can there be contact resistance because removed polymer residue fully, can not corrode the surface of semiconductor layer, the surface of semiconductor layer does not just have damage thus, and three kinds of profiles of contact hole are easy to fill this contact hole with the material of formation source and drain electrode, just remove the natural oxide layer that is easy to produce during the reason herein by wet etching, so just can reduce the contact resistance that causes by the natural oxide layer.
Then, Fig. 4 G adopts the contact hole of above-mentioned three kinds of profiles and the source that forms and the cross sectional photograph of drain electrode.Fig. 4 G is the enlarged photograph of the regional A of Fig. 4 F, and first resilient coating 172 and second resilient coating 173 form by oxide skin(coating) on the glass substrate 171 or nitride layer, as shown in same figure, forms semiconductor layer 174 on second resilient coating 173.
Then, on semiconductor layer 174, form gate insulation layer 175, be formed on unshowned gate electrode in the photo, and form interlayer dielectric 176.
By at high corrosion rate dry etching, high selectivity dry etching and the wet etching described in the first embodiment of the present invention, corrosion interlayer dielectric 176 and gate insulation layer 175 form contact hole 177 and source and the drain electrode 178 with three kinds of profiles thus.In the case, the shape of three kinds of profiles is expressed as dotted line 179.
Then, on the whole surface of substrate, form passivation layer 180, and implement subsequent handling, thereby form TFT, can use this TFT to form display device.
In the case, as shown in photo, because the source that forms in the contact hole of three kinds of profiles and drain electrode have the first contact hole 177a with high corrosion rate dry etching profile, have the second contact hole 177b of high selectivity dry etching profile and have the 3rd contact hole 177c of wet etching profile, just can find out, by having three kinds of profile contact holes that gradual step covers, just form source and drain electrode gradually.In addition, can adjust first degree of depth 181a of first contact hole in three kinds of profile contact holes, second degree of depth 181b of second contact hole and the 3rd degree of depth 181c of the 3rd contact hole, to be convenient to adjust the step covering of three kinds of profile contact holes.Yet, the 3rd degree of depth 181c is not described in above-mentioned specification, it equals to deduct from the degree of depth of contact hole the degree of depth of first and second degree of depth.
(the 3rd embodiment)
Fig. 5 A-5E shows the formation method of through hole according to another embodiment of the invention and the profile that uses the operation of this through hole.
At first, Fig. 5 A is the profile that forms the step of resilient coating, semiconductor layer, gate insulation layer, gate electrode, interlayer dielectric and source and drain electrode on substrate.Shown in Fig. 5 A, at dielectric substrate 201 for example plastics or formation resilient coating 202 on glass.
Then, on resilient coating 202, form amorphous silicon layer, make this amorphous silicon layer crystallization become polysilicon layer or monocrystalline silicon layer then, and it is carried out composition, to form semiconductor layer 203.In the case, can use CVD method or PVD method to amorphous silicon layer.
Then, be formed with therein on the whole surface of substrate of semiconductor layer and formed gate insulation layer 204, on gate insulation layer 204, be formed for forming the material of gate electrode, and this material of composition, to form gate electrode 205.After forming gate electrode 205, can adopt the operation of gate electrode 205 as mask enforcement implanting impurity ion, carry out the operation of the source that in semiconductor layer, limits and drain region and channel region thus.
Then, on the whole surface of substrate, form interlayer dielectric 206.In the case, resilient coating 202, gate insulation layer 204 and interlayer dielectric 206 by oxide skin(coating) for example silicon oxide layer or nitride layer for example silicon nitride layer form.
Then, in interlayer dielectric 206 and gate insulation layer 204, form and adopt the described method of first embodiment to have the contact hole of two kinds of profiles, form source and drain electrode 207 thus, perhaps adopt typical process to form contact hole, form source and drain electrode 207 thus, this has just formed TFT.
Then, Fig. 5 B is explanation forms the step of passivation layer and planarization layer on TFT a profile.Shown in Fig. 5 B, formed thereon on the substrate of TFT, order forms passivation layer 208 and planarization layer 209.
On planarization layer 209, form photoresist,, be formed for forming the photoresist figure 210 of through hole by exposure and development treatment.
Then, Fig. 5 C is that explanation is by a part of utilizing photoresist figure 21O, dry etching passivation layer 208 and planarization layer 209, the profile that forms the step of the through hole with desired depth.Shown in Fig. 5 C, adopt photoresist figure 210, this part with high corrosion rate dry etching passivation layer 208 and planarization layer 209 forms through hole 211 thus.In the case, can in planarization layer 209 and passivation layer 208, form a degree of depth of through hole, as shown in Fig. 5 C, penetrate the part of planarization layer 209 and corrosion and passivation layer 208 by this degree of depth, perhaps described in first embodiment, can also form through hole, so that only corrode the part of planarization layer 209 or corrosion planarization layer 209.In addition, handle, implement this dry etching by dry etching with low selectivity and high corrosion rate.
The coning angle of the through hole that will form by dry etching forms almost perpendicular to adjacent layer, and coning angle can accept in 60 °-90 ° scope, preferably 75 °-90 ° scope.In the case, for dry etching, can use with first embodiment in the identical ion etching implemented handle or the reaction corrosion treatment.
Then, Fig. 5 D is the through hole of explanation wet etching with desired depth with source of exposure and drain electrode, finishes the profile of the step of this through hole thus.Shown in Fig. 5 D, wet etching has corroded into the through hole of desired depth by dry etching, to expose the surface of source and drain electrode 207.In the case, the coning angle of the through hole that will form by wet etching forms the coning angle less than the through hole that forms by dry etching.Coning angle is formed 5 °-60 ° scope, preferred 5 °-45 ° scope.In the case, identical with the description among first embodiment, can after removing the photoresist figure, implement wet etching and handle.
In addition, identical with the description among first embodiment, use with respect to the high selectivity of following source and drain electrode and come wet etching planarization layer and passivation layer, so that can source of corrosion and the surface of drain electrode and only corrosion and passivation layer and planarization layer.And, just removed for example impurity of polymer fully by the wet etching processing, this has just initially been avoided for example producing causing the problem that contact resistance increases by impurity.
The result, the through hole 211 that forms by order dry etching and wet etching just becomes through hole 214 with two kinds of profiles, it penetrates passivation layer and planarization layer with source of exposure and drain electrode, and its top has wet etching profile 212 and its lower part has dry etching profile 213 thus.
Next, Fig. 5 E is the profile of formation operation that adopts the display device of above-mentioned through hole.Shown in Fig. 5 E, on substrate, formed for example TFT of a kind of device, when forming through hole so that when exposing the source of TFT and drain electrode 207, just use through hole 214 to come source of exposure and drain electrode, and the formation transparency electrode is a positive electrode 215 on the whole surface of substrate with two kinds of profiles of the present invention.The not shown step that forms luminescent layer and negative electrode subsequently, yet, form luminescent layer and negative electrode and just formed for example organic EL device of display device thus.
When the transparency electrode that will form on the planarization layer that has formed conventional through hole therein as positive electrode, just can form deposit transparency electrode on the planarization layer of through hole therein with two kinds of profiles of the present invention, pattern is still less changed, thereby be formed uniformly transparency electrode, the coning angle that consequently just can overcome through hole is too big so that can not be formed uniformly the problem of transparency electrode.
(the 4th embodiment)
Fig. 6 A-6E shows the formation method of through hole according to still a further embodiment and the profile that uses the operation of this through hole.
At first, Fig. 6 A is explanation forms the step of resilient coating, semiconductor layer, gate insulation layer, gate electrode, interlayer dielectric, source and drain electrode, passivation layer and planarization layer on substrate a profile.As shown in Figure 6A, at dielectric substrate 251 for example plastics or formation resilient coating 252 on glass.In the case, passivation layer can also play the effect of planarization layer except its self function, thereby if do not need, just can omit planarization layer.
Then, on resilient coating 252, form amorphous silicon layer, make this amorphous silicon layer crystallization become polysilicon layer or monocrystalline silicon layer then, and it is carried out composition, to form semiconductor layer 253.In the case, can use CVD method or PVD method to amorphous silicon layer.
Then, be formed with therein on the whole surface of substrate of semiconductor layer and form gate insulation layer 254, on gate insulation layer 254, be formed for forming the material of gate electrode, and this material of composition, to form gate electrode 255.After forming gate electrode 255, can adopt gate electrode 255 as mask, implement the operation of implanting impurity ion, carry out the operation of the source that in semiconductor layer, limits and drain region and channel region thus.In addition, if do not need, just can omit resilient coating 252.
Then, on the whole surface of substrate, form interlayer dielectric 256.In the case, resilient coating 252, gate insulation layer 254 and interlayer dielectric 256 by oxide skin(coating) for example silicon oxide layer or nitride layer for example silicon nitride layer form.
Then, adopt described in a second embodiment method, can use interlayer dielectric 256 and gate insulation layer 254, the contact hole that has three kinds of profiles with formation, form source and drain electrode 257 thus, perhaps can implement typical process and form contact hole and formation source and drain electrode 257, just form TFT according to order like this.
Then, river pagination deposit passivation layer 258 and planarization layer 259 have been formed on the substrate of TFT therein.
Then, on planarization layer, apply photoresist,, be formed for forming the photoresist figure 260 of through hole by exposure and development treatment.
Then, Fig. 6 B is that explanation adopts the photoresist figure with the part of high corrosion rate dry etching passivation layer and the planarization layer profile with the step of the through hole that forms first degree of depth.Shown in Fig. 6 B, adopt photoresist figure 260, this part with high corrosion rate dry etching passivation layer 258 and planarization layer 259 forms first through hole 261 thus.In the case, can in planarization layer and passivation layer, form first degree of depth of first through hole 261, shown in Fig. 6 B, penetrate the part of planarization layer and corrosion and passivation layer by this degree of depth, perhaps described in second embodiment, can also form through hole so that only corrode planarization layer or the part of corrosion planarization layer.In addition, handle, implement the dry etching of this high corrosion rate by dry etching with low selectivity and high corrosion rate.
Come corrosion and passivation layer or planarization layer with high corrosion rate, thereby form the coning angle 262 of first through hole that forms by high corrosion rate dry etching, and this coning angle can be at 30 °-70.Permissible range, preferably 30 °-50 ° scope.In the case, for dry etching, can use with second embodiment in the identical ion etching implemented handle or the reaction corrosion treatment.
Then, Fig. 6 C first through hole that to be explanation have first degree of depth with the high selectivity dry etching is with the profile of the step that forms second through hole.Shown in Fig. 6 C, by using with respect to the high selectivity corrosion planarization layer of source and drain electrode and the high selectivity dry etching of passivation layer, further corrosion utilizes dry etching to corrode into first through hole of first degree of depth, with the same described in second embodiment, form second through hole 263 that allows to expose or do not allow source of exposure and drain electrode surface thus with second degree of depth.In the case, just can will be applied to this situation, so that can expose the surface of source and drain electrode with same cause the same described in second embodiment.
In the case, the high selectivity dry etching can make for the corrosion rate height of planarization layer and passivation layer and make for the corrosion rate of source and drain electrode low.The result, corroded planarization layer and passivation layer and corroded semiconductor layer hardly by the high selectivity dry etching, the coning angle 264 of second through hole with second degree of depth that forms by the high selectivity dry etching also can become greater than the coning angle of first through hole with first degree of depth.In other words, the coning angle of second through hole with second degree of depth that forms by the high selectivity dry etching just has 60 °-90 ° scope, preferred 70 °-90 ° scope.
Then, Fig. 6 D is that the explanation wet etching has corroded into the profile of the zone of second degree of depth with the step of formation third through-hole.Shown in Fig. 6 D, wet etching forms third through-hole 265 by first and second contact holes that high corrosion rate dry etching and high selectivity dry etching form, and finishes through hole thus.
In the case, shown in Fig. 6 D, can not remove the photoresist figure, but first and second through holes that wet etching forms by high corrosion rate dry etching and high selectivity dry etching, surface (perhaps when having exposed this surface, will increase each width of first and second through holes) with source of exposure and drain electrode, and can form the coning angle 266 of little third through-hole by the isotropism wet etching, perhaps can remove the photoresist figure, by with the isotropic etch described in second embodiment, can form the coning angle of little third through-hole, yet this does not illustrate in Fig. 6 D.
The preferred wet etching solution of source of corrosion and drain electrode that adopts is fully not implemented this wet etching.Adopt etchant solution, so that can not keep natural oxide layer, impurity or polymer residue on the surface of source and drain electrode or on the sidewall at contact hole, so that do not have impurity to residue in the surface of semiconductor layer.
In the case, the coning angle of the third through-hole that forms by wet etching just can be 5 °-50 ° scope, preferred 5 °-35 ° scope.In addition, adopt wet etching solution to implement this wet etching, the wet etching solution that has a high selectivity with respect to source and drain electrode comes wet etching planarization layer and passivation layer to apply, thereby wherein expose or source of exposure and this source on drain electrode surface and this surface of drain electrode can not damaged fully by wet etching solution, also can remove some polymer residues of generation it on.
The result, finished three kinds of profile through holes that contain first, second and third through-hole, it just can make the top of three kinds of profile through holes form the wet etching profile, its middle body forms high selectivity dry etching profile and its lower part with big coning angle and forms the high corrosion rate dry etching profile with roundlet cone angle.
Fig. 6 E is the profile of formation operation that adopts the display device of above-mentioned three kinds of profile through holes.Shown in Fig. 6 E, on substrate, just formed for example TFT of a kind of device, when forming through hole so that when exposing the source of TFT and drain electrode 257, just use through hole 267 to come source of exposure and drain electrode, and the formation transparency electrode is a pixel electrode 268 on the whole surface of substrate with three kinds of profiles of the present invention.In the case, in through hole, just formed and be used for source and drain electrode are electrically connected to contacting of pixel electrode.
The step that forms luminescent layer and negative electrode subsequently is not shown, yet, form luminescent layer and negative electrode and just formed for example organic EL device of display device thus.When the transparency electrode that will form on the planarization layer that has been formed with conventional through hole therein as positive electrode, just can be formed with deposit transparency electrode on the planarization layer of through hole of three kinds of profiles of the present invention therein, pattern is still less changed, thereby be formed uniformly transparency electrode, so that the coning angle that just can overcome through hole is too big so that can not be formed uniformly the problem of transparency electrode, and can remove for example polymer residue of impurity fully, just can produce wherein free can source of damage and the organic EL device on the surface of drain electrode.
(the 5th embodiment)
Fig. 7 A-7E shows the formation method of through hole according to still a further embodiment and the profile that uses the operation of this through hole.
At first, Fig. 7 A is explanation forms the step of metal interconnecting wires and interlayer dielectric on substrate a profile.Shown in Fig. 7 A, at dielectric substrate 301 for example plastics or formation metal interconnecting wires 302 on glass and interlayer dielectric 303.In the case, on substrate, maybe can form the various devices that contain TFT with regard to having formed.In addition, metal interconnecting wires 302 is that a kind of conveying is used for for example metal interconnecting wires of the signal of telecommunication of organic EL device of driving display spare.Interlayer dielectric 303 can be formed by one deck silicon oxide layer, one deck silicon nitride layer or their lamination, can form interlayer dielectric 303 by single operation, and perhaps it can be formed by the insulating barrier that forms by several operations.
Then, Fig. 7 B is the profile that the formation step of the photoresist figure that is used to form the through hole on the substrate is described.Shown in Fig. 7 B, formed therein on the substrate of interlayer dielectric, apply the photoresist that is used to form through hole, and form photoresist figure 304 by exposure and development treatment.
Then, Fig. 7 C is that explanation adopts the photoresist figure to come the profile of the part of dry etching interlayer dielectric with the step of the through hole of formation desired depth.Shown in Fig. 7 C, adopt photoresist figure 304, the part of dry etching interlayer dielectric 303 forms through hole 305 thus.In the case, with high corrosion rate dry etching interlayer dielectric, so that make the coning angle of through hole almost perpendicular to adjacent layer.In other words, the coning angle of the through hole that forms by dry etching can have 60 °-90 ° scope, preferred 75 °-90 ° scope.
Then, Fig. 7 D is the through hole of explanation wet etching with desired depth to expose metal interconnecting wires, to finish the profile of the step of this through hole thus.Shown in Fig. 7 D, use the etchant solution that has a high selectivity with respect to metal interconnecting wires to come the dry etching interlayer dielectric, finish through hole thus with desired depth.In the case, through hole just becomes the through hole 308 with two kinds of profiles, so that the top of through hole has wet etching profile 306 and its lower part has dry etching profile 307.Selectively, can before handling, remove wet etching the photoresist figure.
In the case, the coning angle of the through hole that forms by wet etching is just less than the coning angle of the through hole by dry etching formation.This coning angle has 5 °-60 ° scope, preferred 5 °-45 ° scope.
In addition, utilize wet etching,, use to have high selectivity with respect to following metal interconnecting wires and corrode interlayer dielectric, so that do not corrode the surface of metal interconnecting wires and only corrode interlayer dielectric with the same described in first embodiment.And, handle by wet etching, just removed for example polymer of impurity fully, so that just can initially avoid causing the problem that contact resistance increases because of impurity.
The result, the through hole that dry etching and wet etching form that uses in order just penetrates interlayer dielectric and exposes metal interconnecting wires, so that it just becomes the through hole with two kinds of profiles, makes its top have the wet etching profile and its lower part has the dry etching profile.
Then, Fig. 7 E is the profile of formation operation that adopts the display device of above-mentioned through hole.Shown in Fig. 7 E, on substrate 301, form metal interconnecting wires 302, on metal interconnecting wires 302, form interlayer dielectric 303.Order is implemented dry etching and wet etching, formation has the through hole 308 of two kinds of profiles, so that its top has the wet etching profile and its lower part has the dry etching profile, and depositing conductive material thereon, forms new metal interconnecting wires 309 thus.In addition, if necessary, shown in the dotted line 31O of Fig. 7 E, can form new metal interconnecting wires with uniform thickness.
(the 6th embodiment)
Fig. 8 A-8E is the profile that through hole formation method according to still a further embodiment is shown and uses the operation of this through hole.
At first, Fig. 8 A is that explanation is at the profile that forms metal interconnecting wires and interlayer dielectric on the substrate and be formed for the technology of the photoresist figure of formation through hole on interlayer dielectric.Shown in Fig. 8 A, dielectric substrate 313 for example plastics or order on glass form metal interconnecting wires 352 and interlayer dielectric 353, and on interlayer dielectric 353, be formed for forming the photoresist figure 354 of through hole.
In the case, at first on substrate, apply photoresist, and implement exposure and development treatment in proper order, form the photoresist figure thus to form through hole.
Then, Fig. 8 B is that explanation adopts the photoresist figure to come with the part of the high corrosion rate dry etching interlayer dielectric profile with the step of first through hole that forms first degree of depth.Shown in Fig. 8 B, adopt photoresist figure 354, with the part of high corrosion rate dry etching interlayer dielectric 353, form first through hole 355 thus with first degree of depth.In the case, handle, implement this dry etching by dry etching with low selectivity and high corrosion rate.
The coning angle 356 of first through hole that forms by high corrosion rate dry etching can be accepted as 30 °-70 ° scope, preferred 30 °-50 ° scope.In the case, for high corrosion rate dry etching, can use with second embodiment in the identical ion etching implemented handle or the reaction corrosion treatment.
Then, to be explanation come first through hole that dry etching has first degree of depth profile with the step that forms second through hole with high selectivity to Fig. 8 C.Shown in Fig. 8 C, by the high selectivity dry etching, to utilize dry etching to corrode to become first through hole of first degree of depth further to corrode into second degree of depth, identical with the description among second embodiment, owing to have the dielectric high selectivity dry etching between corrosion layer that is used for that has high selectivity with respect to metal interconnecting wires, this second degree of depth just allows or does not allow the surface of metal interconnecting wires to expose, and forms second through hole 357 thus.In the case, the high selectivity dry etching just can make for the corrosion rate of interlayer dielectric high and make for the corrosion rate of metal interconnecting wires low.As a result, just corroded interlayer dielectric by the high selectivity dry etching, corroding metal interconnection line hardly simultaneously, and the coning angle 358 of second through hole with second degree of depth that forms by the high selectivity dry etching also can be greater than the coning angle of first through hole.In other words, the coning angle of second through hole that forms by the high selectivity dry etching has 60 °-90 ° scope, preferred 70 °-90 ° scope.
Then, Fig. 8 D is that the explanation wet etching has corroded into the profile of the zone of second degree of depth with the step of formation third through-hole.Shown in Fig. 8 D, wet etching forms third through-hole 359 by first and second through holes that high corrosion rate dry etching and high selectivity dry etching form, and finishes this through hole thus.
In the case, can not remove the photoresist figure, and but wet etching is by first and second through holes of high corrosion rate dry etching and the formation of high selectivity dry etching, the surface that exposes first electric conducting material (perhaps, when having exposed this surface, just increase each width of first and second through holes), and can form the coning angle 360 of little third through-hole by the isotropism wet etching, perhaps, described in second embodiment, can remove the coning angle that the photoresist figure also can form little third through-hole by the isotropism wet etching, yet, not shown this situation among Fig. 8 D.
Preferably implement wet etching with the wet etching solution of the erosion metal interconnecting wires that is stale-proof fully.Adopt this etchant solution, so that at not residual natural oxide skin(coating), impurity or polymer residue on the surface of metal interconnecting wires or on the sidewall at through hole, so that the surface of metal interconnecting wires just can not residual impurity.
In the case, the coning angle of the third through-hole that forms by wet etching can have 5 °-50 ° scope, yet it can preferably have 5 °-35 ° scope.In addition, implement wet etching, so that use the wet etching solution that has a high selectivity with respect to metal interconnecting wires to come the wet etching interlayer dielectric, so that the source that exposes or exposed and the surface of drain electrode are not damaged by this wet etching solution fully, and can remove some polymer residues that produce on it.
The result, three kinds of profile through holes that contain first, second and third through-hole have just been finished, the high corrosion rate dry etching profile that the top of these three kinds of profile through holes is formed have the wet etching profile, its middle body forms high selectivity dry etching profile with big coning angle and the formation of its lower part has the roundlet cone angle.
Fig. 8 E is the profile of formation operation that adopts the display device of above-mentioned three kinds of profile through holes.Shown in Fig. 8 E, order forms metal interconnecting wires and interlayer dielectric on substrate, and adopt through hole 351 that metal interconnecting wires is exposed when exposing metal interconnecting wires, and forming metal interconnecting wires 362 on the whole surface of substrate with three kinds of profiles of the present invention when forming through hole.As a result, just in through hole, formed the contact that is used for metal interconnecting wires is electrically connected to metal interconnecting wires.
In the case, can implement high corrosion rate dry etching, high selectivity dry etching and wet etching in proper order, formation has the through hole of three kinds of profiles, wherein its top has the wet etching profile and its lower part has the dry etching profile, and this has just formed the last metal interconnecting wires shown in Fig. 8 E.In addition, if necessary, shown in the dotted line of Fig. 8 E, can form last metal interconnecting wires with uniform thickness.
(the 7th embodiment)
Fig. 9 A-9E shows the formation method of through hole contact hole according to still a further embodiment and the profile that uses the operation of this through hole contact hole.
At first, Fig. 9 A is the profile that forms the step of resilient coating, semiconductor layer, gate insulation layer and gate electrode on substrate.Shown in Fig. 9 A, at dielectric substrate 401 for example plastics or formation resilient coating 402 on glass.Resilient coating 402 plays the effect that prevents steam or produce the diffusion of impurities in the substrate that insulate, and perhaps plays when carrying out crystallization and just easily carries out the effect of the crystallization of semiconductor layer by adjusting heat conduction velocity.
Then, on resilient coating 402, form amorphous silicon layer, make this amorphous silicon layer crystallization become polysilicon layer or monocrystalline silicon layer then, and it is carried out composition, to form semiconductor layer 403.In the case, can use CVD method or PVD method to amorphous silicon layer.In addition, when forming amorphous silicon layer or after forming amorphous silicon layer, can implement to make the amorphous silicon layer dehydration to reduce the operation of hydrogen concentration.
Then, be formed with therein on the whole surface of substrate of semiconductor layer 403, formed gate insulation layer 404, on gate insulation layer 404, be formed for forming the material of gate electrode, and this material of composition, gate electrode 405 formed.After forming gate electrode 405, can adopt gate electrode as mask, implement the operation of implanting impurity ion, carry out the operation of the source that in semiconductor layer 403, limits and drain region and channel region thus.
Then, Fig. 9 B is explanation forms the step of planarization layer and photoresist figure on substrate a profile.As shown in the regional A of Fig. 9 B, on substrate, form planarization layer 406, and on planarization layer 406, be formed for forming the photoresist figure 407 of through hole contact hole.Contrast, as shown in the area B of Fig. 9 B, before forming planarization layer 406 and photoresist figure 407, can at first on substrate, form interlayer dielectric.In other words, if necessary, just can form interlayer dielectric.
For example silicon oxide layer or silicon nitride layer form by insulating barrier for interlayer dielectric or planarization layer 406.
Form photoresist figure 407, so that it is coated on the substrate by spin coating method or spraying method at first, and implements exposure and development treatment subsequently.
Then, Fig. 9 C is the profile of the step of the part of explanation dry etching gate insulation layer and the planarization layer through hole contact hole that has desired depth with formation.Shown in Fig. 9 C, in company with the planarization layer among the regional A or gate insulation layer together, perhaps in company with the planarization layer in the area B, interlayer dielectric or gate insulation layer together, dry etching photoresist figure 407 forms the through hole contact hole 409 with desired depth thus.
In the case, in regional A, can use the method for only corroding the part planarization layer, penetrate the method that planarization layer does not corrode the method for gate insulation layer simultaneously or gate insulation layer corroded into the degree of depth of part gate insulation layer, and in area B, can adopt with regional A in the same procedure that adopted, planarization layer, interlayer dielectric or gate insulation layer are corroded into the required degree of depth, form the through hole contact hole thus.
In other words, by corroding into the dry etching of required corrosion depth, just formed the through hole contact hole.In addition, corrodible planarization layer of this dry etching or gate insulation layer, perhaps can high corrosion rate corrode planarization layer, interlayer dielectric or gate insulation layer, so that just can adjust the coning angle of through hole contact hole and the degree of depth of through hole contact hole, and just have almost angle perpendicular to adjacent layer by the through hole contact hole that dry etching of the present invention corrodes.In the case, the coning angle 410 of this contact hole that forms by this dry etching just can be accepted as 60 °-90 ° scope, preferably 75 °-90 ° scope.
In the case, for dry etching, can use ion etching to handle or the reaction corrosion treatment.
Then, Fig. 9 D is that the explanation wet etching has the through hole contact hole of desired depth so that the surface of semiconductor layer exposes, finishes thus the profile of the step of this through hole contact hole.Shown in Fig. 9 D, wet etching has corroded into the contact hole of desired depth by dry etching, finishes this contact hole, so that expose the surface of semiconductor layer 430.
In the case, as shown in the regional A of Fig. 9 D, can remove the photoresist figure, the through hole contact hole that can wet etching forms by dry etching exposes the surface of semiconductor layer, and by the isotropism wet etching, the coning angle 411 of little through hole contact hole can be formed, perhaps as shown in the area B of Fig. 9 D, the photoresist figure can be do not removed, and, can form the coning angle of little through hole contact hole by the isotropism wet etching.
In the case, the coning angle of the through hole contact hole that utilizes wet etching to form can be formed and have 5 °-60 ° scope, preferred 5 °-45 ° scope.In addition, implement wet etching, so that use with respect to planarization layer and gate insulation layer or with respect to the etchant solution that planarization layer, interlayer dielectric and gate insulation layer have a high selectivity and come the wet etching semiconductor layer, so that even when exposing semiconductor layer surperficial, also can not damage semiconductor layer fully, and can remove some polymer residues of generation on it by this wet etching solution.
As a result, the through hole contact hole has just become the through hole contact hole 414 with two kinds of profiles, and its top has wet etching profile 412 and its lower part has dry etching profile 413 thus.
Then, Fig. 9 E is the profile that adopts the formation operation of the display device of the above-mentioned through hole with two kinds of profiles or TFT.Shown in Fig. 9 E, formed therein on the whole surface of substrate of through hole contact hole with two kinds of profiles, can be formed for forming the material of positive electrode, and can be with its composition, to form the positive electrode 415 that it directly contacts with semiconductor layer 403.Although among Fig. 9 E not shown in, can form luminescent layer and negative electrode, form for example organic EL device of display device thus.
In addition, as shown in the area B of Fig. 9 E, on the whole surface of substrate, can be formed for forming the material of metal interconnecting wires, but this material of composition to be forming metal interconnecting wires 416, so that can produce that through hole contact hole wherein directly is connected to metal interconnecting wires with semiconductor layer and the TFT that do not need source and drain electrode.
The result, the through hole contact hole just contacts with two kinds of profile contact holes 411, and the top of contact hole 411 has the wet etching profile and its lower part has the dry etching profile, so that removed polymer residue fully, thereby just can not have the contact resistance that causes because of residue, and can not corrode the surface of semiconductor layer, thereby for just not damage of semiconductor layer, and two kinds of profiles of through hole contact hole just are easy to come the filling vias contact hole with the material that forms positive electrode or with the material that forms metal interconnecting wires.
(the 8th embodiment)
Figure 10 A-10E shows the formation method of through hole contact hole according to still a further embodiment and the profile that uses the operation of this through hole contact hole.
At first, Figure 10 A is the profile that forms the step of resilient coating, semiconductor layer, gate insulation layer, gate electrode, interlayer dielectric and photoresist figure on substrate.Shown in Figure 10 A, at dielectric substrate 451 for example plastics or formation resilient coating 452 on glass.Resilient coating 452 plays the effect that prevents steam or produce the diffusion of impurities in the substrate that insulate, and perhaps plays when carrying out crystallization and just easily carries out the effect of the crystallization of semiconductor layer by adjusting heat conduction velocity.
Then, on resilient coating 452, form amorphous silicon layer, make this amorphous silicon layer crystallization become polysilicon layer or monocrystalline silicon layer then, and it is carried out composition to form semiconductor layer 453.In the case, can use CVD method or PVD method to amorphous silicon layer.In addition, when forming amorphous silicon layer or after forming amorphous silicon layer, can implement to make the amorphous silicon layer dehydration to reduce the operation of hydrogen concentration.
Then, be formed with therein on the whole surface of substrate of semiconductor layer 453 and form gate insulation layer 454, then on gate insulation layer 454, be formed for forming the material of gate electrode, and this material of composition, formation gate electrode 455.After forming gate electrode 455, can adopt gate electrode 455 as mask, implement the operation of implanting impurity ion, carry out the operation of the source that in semiconductor layer 453, limits and drain region and channel region thus.
Then, as shown in the regional A of Figure 10 A, on substrate, form planarization layer 456, and be formed on planarization layer 456, forming the photoresist figure 457 of through hole contact hole.Contrast, as shown in the area B of Figure 10 A, before forming planarization layer 456 and photoresist figure 457, can at first on substrate, form interlayer dielectric 458.In other words, if necessary, can form interlayer dielectric 458.
In the case, for example silicon oxide layer or silicon nitride layer form by insulating barrier for interlayer dielectric 458 or planarization layer 456.
Form photoresist figure 457, so that at first adopt spin coating method or injection method that it is coated on the substrate, implement exposure and development treatment subsequently.
Then, Figure 10 B is the profile of the step of the explanation first through hole contact hole that has first degree of depth with the part of high corrosion rate dry etching planarization layer with formation.Shown in Figure 10 B, adopt photoresist figure 457, planarization layer or gate insulation layer or the planarization layer in area B, interlayer dielectric or gate insulation layer among the A of dry etching zone form the first through hole contact hole 459 with first degree of depth thus.
In the case, in regional A, can use the method for only corroding the part planarization layer, penetrate the method that planarization layer does not corrode the method for gate insulation layer simultaneously or gate insulation layer corroded into the degree of depth of part gate insulation layer, and in area B, can adopt with regional A in the same procedure that adopted, planarization layer, interlayer dielectric or gate insulation layer are corroded into the required degree of depth, form the first through hole contact hole thus.
In other words, by corroding into the dry etching of first degree of depth, just formed the first through hole contact hole with high corrosion rate.In addition, this high corrosion rate dry etching can corrode planarization layer or gate insulation layer, perhaps can high corrosion rate corrode planarization layer, interlayer dielectric or gate insulation layer, so that just can adjust the coning angle of the first through hole contact hole and the degree of depth of the first through hole contact hole.In the case, the coning angle 460 of the first through hole contact hole that forms by this high corrosion rate dry etching just can be accepted as 30 °-70 ° scope, preferably 30 °-50 ° scope.
In the case, for high corrosion rate dry etching, can use ion etching to handle or the reaction corrosion treatment.
Then, Figure 10 C is the explanation first through hole contact hole that adopts high selectivity to corrode to come dry etching to have first degree of depth with the profile of the step that forms the second through hole contact hole.Shown in Figure 10 C, formed planarization layer and gate insulation layer or the planarization layer in area B, passivation layer and gate insulation layer among the regional A of the first through hole contact hole with the high selectivity dry etching therein, formed and expose or the second through hole contact hole 461 of second degree of depth of exposed semiconductor layer not.
In the case, the high selectivity dry etching will make for the corrosion rate of planarization layer, passivation layer and gate insulation layer high and low for the corrosion rate of semiconductor layer.The result, just can corrode planarization layer, passivation layer and gate insulation layer by the high selectivity dry etching, corrode simultaneously semiconductor layer hardly, and the coning angle 462 of the second through hole contact hole with second degree of depth that forms by the high selectivity dry etching also can become the coning angle greater than the first through hole contact hole with first degree of depth.
In other words, the coning angle of the second through hole contact hole with second degree of depth that forms by the high selectivity dry etching is in 60 °-90 ° scope, preferred 70 °-90 ° scope just almost perpendicular to adjacent layer.
As shown in the regional A of Figure 10 C, the second through hole contact hole with second degree of depth can be formed the not degree of depth of exposed semiconductor layer, perhaps as shown in the area B of Figure 10 C, the second through hole contact hole with second degree of depth can be formed the degree of depth that exposes semiconductor layer.This result results from the following fact: by the high selectivity dry etching, the surface of corroding semiconductor layer hardly with regard to only corroding gate insulation layer and interlayer dielectric, so that even when as shown in area B, exposing semiconductor layer, also damage the surface of semiconductor layer hardly.Yet the high selectivity dry etching may influence semiconductor layer as the case may be, thereby semiconductor layer can be corroded into the degree of depth of the not exposed semiconductor layer shown in the regional A, has initially avoided semiconductor layer to be damaged or excessive erosion thus.
Figure 10 D is that the explanation wet etching has corroded into the profile of the zone of second degree of depth with the step of formation third through-hole contact hole.Shown in Figure 10 D, further wet etching dry etching become the second through hole contact hole of second degree of depth, the surface of exposed semiconductor layer 453 forms third through-hole contact hole 463 thus.
In the case, as shown in the regional A of Figure 10 D, can remove the photoresist figure, but the first and second through hole contact holes that wet etching forms by high corrosion rate dry etching and high selectivity dry etching, so that the coning angle 143 of third through-hole contact hole is diminished by the isotropism wet etching, thereby the surface that exposes semiconductor layer (perhaps, when exposing this surface, just increase each width of the first and second through hole contact holes), perhaps as shown in the area B of Figure 10 D, can not remove the photoresist figure, and, can form the coning angle of little third through-hole contact hole by the isotropism wet etching.
In the case, the coning angle of the third through-hole contact hole that utilizes wet etching to form can be formed and have 5 °-50 ° scope, yet it can preferably have 5 °-35 ° scope.In addition, implement wet etching with wet etching solution, so that come wet etching planarization layer and gate insulation layer according to have high selectivity with respect to semiconductor layer, or planarization layer, interlayer dielectric and gate insulation layer, so that even when exposing semiconductor layer surperficial, also can not damage semiconductor layer fully, and can remove some polymer residues of generation it on by this wet etching solution.
The result, just finished three kinds of profiles that contain first, second and third through-hole contact hole, these three kinds of profiles will make the top of three kinds of profile through holes form wet etching profile, its middle body and form the high corrosion rate dry etching profile that high selectivity dry etching profile with big coning angle and its lower part have the roundlet cone angle.
Then, Figure 10 E is the profile that adopts the formation operation of the display device of the above-mentioned through hole with three kinds of profiles or TFT.As shown in the regional A of Figure 10 E, formed therein on the whole surface of substrate of through hole contact hole with three kinds of profiles, can be formed for forming the material of pixel electrode, and can composition it, form the pixel electrode 465 that it directly contacts with semiconductor layer 453.Although among Figure 10 E not shown in, can form luminescent layer and public electrode, form for example organic EL device of display device thus.In addition, as shown in the area B of Figure 10 E, can on the whole surface of substrate, be formed for forming the material of metal interconnecting wires, can this material of composition, form metal interconnecting wires 466, so that can produce that through hole contact hole wherein directly is connected to metal interconnecting wires with semiconductor layer and the TFT that do not need source and drain electrode.
The result, the through hole contact hole just contacts with three kinds of profile contact holes 467, and the top of contact hole 467 has the wet etching profile, its middle body has the high selectivity dry etching profile of big coning angle and the high corrosion rate dry etching profile that its lower part has the roundlet cone angle, so that removed polymer residue fully, thereby just can not have the contact resistance that causes because of residue, and can not corrode the surface of semiconductor layer, thereby semiconductor layer is not damage just, and three kinds of profiles of through hole contact hole just are easy to come the filling vias contact hole with the material that forms pixel electrode or with the material that forms metal interconnecting wires.
(the 9th embodiment)
When showing according to still a further embodiment, Figure 11 forms contact hole and the method for through hole and the profile that uses the semiconductor device of this contact hole and through hole.
As shown in figure 11, zone A represents a TFT, wherein adopt the contact hole of two kinds of profiles that in first embodiment, form to come formation source and drain electrode, and area B is represented a kind of semiconductor device, wherein adopt the through hole of two kinds of profiles that in the 5th embodiment, form to form metal interconnecting wires, and form this two zones in the present embodiment simultaneously.
In other words, at dielectric substrate 501 for example plastics or formation resilient coating 502 on glass, adopt with first embodiment in describe same procedure, in the presumptive area of substrate such as regional A, form semiconductor layer 503, on substrate, form gate insulation layer 504, and on substrate, be formed for forming the material of gate electrode, this material of composition forms gate electrode 505 then.
In the case, in the area B of distance areas A predetermined space, form first metal interconnecting wires 506.The gate material that forms on the whole surface of the substrate in being patterned at regional A can adopt this figure to form first metal interconnecting wires 506 when forming gate electrode 505.In other words, the gate electrode 505 and first metal interconnecting wires 506 are formed by mutually the same material, and can interiorly at one time form.In addition, on the substrate of area B, can not be removed each stacked when in regional A, forming resilient coating 502 and gate insulation layer 504 layer, yet, among Figure 11 not shown it.
Then, in regional A, form interlayer dielectric 507.In area B, form interlayer dielectric 508 equally, and can form this two kinds of interlayer dielectrics 507 and 508 simultaneously.
Use and the same procedure described in the first and the 5th embodiment, to show high corrosion rate dry etching and optionally interlayer dielectric and the gate insulation layer of wet etching zone A, form two kinds of profile contact holes 509 thus, and, form two kinds of profile through holes 510 thus with the high corrosion rate dry etching and the interlayer dielectric of wet etching area B optionally.In the case, implement simultaneously to the dry etching of regional A and B with to the wet etching of regional A and B, so that form two kinds of profile contact holes 509 and two kind of profile through hole 510 simultaneously.The coning angle of dry etching profile can have 60 °-90 ° scope, preferred 75 °-90 ° scope, and the coning angle of wet etching profile can have 5 °-60 ° scope, preferred 5 °-45 ° scope.
Then, in regional A, be formed for the material of formation source and drain electrode, then this material of composition, formation source and drain electrode 511, the same material that is formed for forming second metal interconnecting wires in area B, this material of composition forms second metal interconnecting wires 512 then.In the case, can on the whole surface of substrate, apply and be used to form the material of source and drain electrode, and can adopt source and drain electrode and second pattern of metal interconnect lines to form source and the drain electrode and second metal interconnecting wires simultaneously.In other words, source and drain electrode and second metal interconnecting wires can be formed by the same material of implementing an operation.
Then, on substrate, can form passivation layer and planarization layer, and also can form positive electrode, luminescent layer and negative electrode thereon, form for example organic EL device of display device thus, yet, not shown this structure among Figure 11.
(the tenth embodiment)
When showing according to still a further embodiment, Figure 12 forms contact hole and the method for through hole and the profile that uses the operation of this contact hole and through hole.As shown in figure 12, zone A represents a TFT, wherein adopt the contact hole of three kinds of profiles that form in a second embodiment to come formation source and drain electrode, and area B is represented a kind of metal interconnecting wires district, wherein adopt the through hole that in the 6th embodiment, forms to form metal interconnecting wires, and formed this two zones in the present embodiment simultaneously with three kinds of profiles.In other words, at dielectric substrate 551 for example plastics or formation resilient coating 552 on glass, adopt with first embodiment in describe same procedure, in the presumptive area of substrate such as regional A, form semiconductor layer 553, on substrate, form gate insulation layer 554, and on substrate, be formed for forming the material of gate electrode, this material of composition forms gate electrode 555 then.
In the case, in the area B of distance areas A predetermined space, form first metal interconnecting wires 556.When the gate material that forms on the whole surface that is patterned at substrate when in regional A, forming gate electrode 555, can adopt this figure to form first metal interconnecting wires 556.In other words, the gate electrode 555 and first metal interconnecting wires 556 are formed by identical materials, and form in can be at one time.In addition, on the substrate of area B, can not remove each stacked when in regional A, forming resilient coating 552 and gate insulation layer 554 layer, yet, not shown this structure among Figure 12.
Then, in regional A, form interlayer dielectric 557.In area B, form interlayer dielectric 558 equally, and can form this two kinds of interlayer dielectrics 557 and 558 simultaneously.
Use and the same procedure described in the second and the 6th embodiment, so that utilize high corrosion rate dry etching, high selectivity dry etching and optionally wet etching come interlayer dielectric 557 and the gate insulation layer of corrosion area A, form three kinds of profile contact holes 559 thus, and utilize high corrosion rate dry etching, high selectivity dry etching and optionally wet etching come the interlayer dielectric 558 of corrosion area B, form three kinds of profile through holes 560 thus.In the case, implement simultaneously to the high corrosion rate dry etching of regional A and B and high selectivity dry etching with to the wet etching of regional A and B, so that form three kinds of profile contact holes 559 and three kind of profile through hole 560 simultaneously.The coning angle of high corrosion rate dry etching profile can have 30 °-70 ° scope, preferred 30 °-50 ° scope, the coning angle of high selectivity dry etching profile can have 60 °-90 ° scope, preferred 70 °-90 ° scope, and the coning angle of wet etching profile can have 5 °-50 ° scope, preferred 5 °-35 ° scope.
Then, in regional A, be formed for the material of formation source and drain electrode, then this material of composition, formation source and drain electrode 561, the same material that is formed for forming second metal interconnecting wires in area B, this material of composition forms second metal interconnecting wires 562 then.In the case, can on the whole surface of substrate, apply and be used to form the material of source and drain electrode 561, and can adopt source and drain electrode and the second metal interconnected line graph to form source and the drain electrode and second metal interconnecting wires simultaneously.In other words, source and drain electrode and second metal interconnecting wires can be formed by the same material of implementing an operation.
Then, can on substrate, form passivation layer, planarization layer etc., and also can form pixel electrode, luminescent layer and public electrode thereon, form for example organic EL device of display device thus, yet, not shown this structure among Figure 12.
First and second embodiment have the contact hole of two kinds of profiles or three kinds of profiles corresponding to formation, third and fourth embodiment has the through hole of two kinds of profiles or three kinds of profiles corresponding to formation, the the 5th and the 6th embodiment has the through hole of two kinds of profiles or three kinds of profiles corresponding to formation, and the 7th and the 8th embodiment has the through hole contact hole of two kinds of profiles or three kinds of profiles corresponding to formation, the the 9th and the tenth embodiment is corresponding to forming through hole and the contact hole with two kinds of profiles or three kinds of profiles simultaneously, yet, can also form contact hole with four kinds of profiles or more kinds of profile and above-mentioned two kinds of profiles or three kinds of profiles, through hole or through hole contact hole.In other words, when repeating to implement wet etching or dry etching at least for example when high selectivity dry etching or high corrosion rate dry etching, just can obtain to have the structure of multiple profile.Yet, use wet etching to handle for last corrosion treatment, so that remove etching residue or impurity fully, just can form each contact hole that all has good characteristic, through hole or through hole contact hole thus.
Therefore, semiconductor device according to the invention and manufacture method thereof just can initially be avoided following problem: the contact portion dry etching of contact hole, through hole or through hole contact hole is become to have the contact heterogeneity and produces polymer residue, and can not damage the semiconductor layer, source and the drain electrode that are exposed by contact hole, through hole or through hole contact hole and the surface of metal interconnecting wires fully.
Though described the present invention with reference to some exemplary embodiment of the present invention, but those of ordinary skills are to be understood that, do not breaking away within the spirit or scope of the present invention, can modifications and variations of the present invention are, the spirit or scope of the present invention is limited among accessory claim and their equivalents.
The application requires the priority of the Korean Patent Application No. No.2004-37052 of submission on May 24th, 2004, quotes its full content as a reference at this.
Claims (24)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR37052/04 | 2004-05-24 | ||
| KR1020040037052A KR20050112031A (en) | 2004-05-24 | 2004-05-24 | Contact hole and method fabricating thereof |
| KR48560/04 | 2004-06-25 |
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| CN1725511A true CN1725511A (en) | 2006-01-25 |
| CN100481512C CN100481512C (en) | 2009-04-22 |
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| CNB2005100792571A Active CN100481512C (en) | 2004-05-24 | 2005-05-24 | Semiconductor device and method of fabricating the same |
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| Country | Link |
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| JP (2) | JP4521295B2 (en) |
| KR (1) | KR20050112031A (en) |
| CN (1) | CN100481512C (en) |
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| CN104952934B (en) * | 2015-06-25 | 2018-05-01 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and manufacture method, array base palte, display panel |
| CN104952934A (en) * | 2015-06-25 | 2015-09-30 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method, array substrate and display panel |
| CN108363252A (en) * | 2017-01-26 | 2018-08-03 | 三菱电机株式会社 | The manufacturing method of liquid crystal display device and tft array substrate |
| CN108363252B (en) * | 2017-01-26 | 2021-10-15 | 三菱电机株式会社 | Liquid crystal display device and manufacturing method of TFT array substrate |
| CN107134412A (en) * | 2017-03-23 | 2017-09-05 | 北京理工大学 | A kind of source-drain electrode via etch technique and application |
| CN107134412B (en) * | 2017-03-23 | 2019-08-16 | 北京理工大学 | A kind of source-drain electrode via etch technique and application |
| CN109860106A (en) * | 2019-02-28 | 2019-06-07 | 合肥京东方光电科技有限公司 | A kind of preparation method of display base plate |
| CN110136574A (en) * | 2019-05-13 | 2019-08-16 | 友达光电（昆山）有限公司 | display panel |
| CN113517223A (en) * | 2021-06-29 | 2021-10-19 | 上海华力集成电路制造有限公司 | Method for manufacturing active region metal zero layer |
| CN113517223B (en) * | 2021-06-29 | 2024-03-15 | 上海华力集成电路制造有限公司 | Method for manufacturing active area metal zero layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005340168A (en) | 2005-12-08 |
| CN100481512C (en) | 2009-04-22 |
| JP4430568B2 (en) | 2010-03-10 |
| JP4521295B2 (en) | 2010-08-11 |
| JP2005340776A (en) | 2005-12-08 |
| KR20050112031A (en) | 2005-11-29 |
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