CN1716593A - Electrostatic discharge protection circuit - Google Patents

Abstract

The invention relates to an electrostatic discharge protection circuit, which is electrically connected with an input pad, and comprises: a diode disposed in a substrate and electrically connected to the input pad; a P-type deep well region in the substrate; an N-type well region located in the P-type deep well region; a first P + doped region in the N-well region, wherein the first P + doped region is electrically connected to the input pad; an NMOS transistor on the substrate, wherein the NMOS transistor has a gate, a source and a drain, the drain is located in the N-well and electrically connected to a control circuit power (Vcc), and the source is located in the P-well; and a second P + doped region in the P-type deep well region. Compared with the traditional circuit design, the electrostatic discharge protection circuit only needs a smaller area.

Description

Electrostatic discharge protection circuit

technical field

The present invention relates to an electrostatic discharge protection circuit (ESD), in particular to an electrostatic discharge protection circuit applied to a high-speed input pad (High-Speed Input Pad).

Background technique

Electrostatic discharge is the phenomenon of the movement of static electricity from non-conductive surfaces that can cause damage to semiconductors and other circuit components in integrated circuits. For example, a human body walking on a carpet can detect a static voltage of several hundred to several thousand volts in the case of high relative humidity, and a static voltage of about 10,000 volts in the case of low relative humidity. above the quiescent voltage. A static voltage of several hundred to several thousand volts may also be generated in a machine for packaging integrated circuits or an instrument for testing integrated circuits. When the above-mentioned charged body (human body, machine or instrument) touches the chip, it will discharge to the chip, and the instantaneous power of this electrostatic discharge may cause damage or failure of the integrated circuit in the chip.

In order to prevent integrated circuits from being damaged due to electrostatic discharge phenomena, an electrostatic discharge protection circuit design is generally added to integrated circuits. However, there are many design methods for general electrostatic discharge protection circuits, and one of the common methods is to use MOS transistors (transistors are transistors, hereinafter referred to as transistors) for layout. Using MOS transistors to design electrostatic discharge protection circuits can usually achieve a good protection effect, but the area of this circuit design will be relatively large, so there will be a relatively large loading effect of parasitic capacitance, which will affect the signal. transfer speed. Especially for components with high-speed or high-voltage input requirements, the above-mentioned load effect is a problem that must be overcome.

Another way to design an ESD protection circuit is to use diodes and MOS transistors for layout. Generally speaking, diodes have excellent current conduction efficiency, and this design method of mainly using diodes to achieve the effect of electrostatic discharge protection can solve the above-mentioned problem of parasitic capacitance loading effect. However, since the diode itself does not have the ability to discharge electrostatic current, it usually still has to be matched with a MOS transistor. However, the MOS transistor designed in this ESD protection circuit also needs a large area, and usually the MOS transistor needs to be designed close to the input pad, thus increasing the complexity and area of the entire protection circuit design.

It can be seen that the above-mentioned existing electrostatic discharge protection circuit obviously still has inconveniences and defects in structure and use, and needs to be further improved urgently. In order to solve the problems existing in the ESD protection circuit, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above problems. This is obviously a problem that relevant industry players are eager to solve.

In view of the defects existing in the above-mentioned existing electrostatic discharge protection circuit, the inventor actively researches and innovates based on years of rich practical experience and professional knowledge engaged in the design and manufacture of this type of product, and cooperates with the application of academic theory, in order to create a new type of structure The electrostatic discharge protection circuit can improve the general existing electrostatic discharge protection circuit and make it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.

Contents of the invention

The purpose of the present invention is to overcome the existing defects in the electrostatic discharge protection circuit, and provide a novel structure of the electrostatic discharge protection circuit, the technical problem to be solved is to make this circuit design do not need to use a large area, and It can effectively achieve the effect of electrostatic discharge protection, so it is more suitable for practical use.

Another object of the present invention is to provide an electrostatic discharge protection circuit. The technical problem to be solved is to make this protection circuit only need to use a small area, and can be applied to high-voltage or high-speed input pads, so that it is more suitable for practical use. .

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to an electrostatic discharge protection circuit proposed by the present invention, it is electrically connected to an input pad, and the electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad; A deep well region of the first type is located in the base; a well region of the second type is located in the deep well region of the first type; a first doped region of the first type is located in the second type in the well region of the second type, and it is electrically connected to the input pad; a second doped region of the second type is located in the well region of the second type, and it is electrically connected to a control circuit Power supply (Vcc); a third doped region of the second type, located in the deep well region of the first type; and a fourth doped region of the first type, located in the deep well region of the first type middle.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned electrostatic discharge protection circuit, one end of the diode is electrically connected to the input pad, and the other end is grounded.

In the aforementioned electrostatic discharge protection circuit, the third doped region of the second type and the fourth doped region of the first type are grounded.

In the aforementioned ESD protection circuit, the second doped region of the second type is located between the first doped region of the first type and the third doped region of the second type.

In the aforementioned electrostatic discharge protection circuit, part of the second type of second doped region is located in the second type of well region, and another part of the second type of second doped region is located in In the deep well area of the first type.

The aforementioned electrostatic discharge protection circuit further includes a fifth doped region of the first type located in part of the second type well region and part of the first type deep well region.

In the aforementioned electrostatic discharge protection circuit, the fifth doped region of the first type is further electrically connected to a control circuit to control whether the fifth doped region of the first type is grounded.

In the aforementioned electrostatic discharge protection circuit, when the input pad receives an electrostatic current, the power supply (Vcc) of the control circuit is turned off, and the first doped region of the first type, the well of the second type Region and the deep well region of the first type constitute a first parasitic bicarrier transistor, and the well region of the second type, the deep well region of the first type and the third doped The region constitutes a second parasitic bipolar transistor, and the first parasitic bipolar transistor and the second parasitic bipolar transistor constitute a forward loop.

In the aforementioned electrostatic discharge protection circuit, the first type is P-type, and the second type is N-type.

The purpose of the present invention and the solution to its technical problems are also achieved by the following technical solutions. According to an electrostatic discharge protection circuit proposed by the present invention, it is electrically connected to an input pad, and the electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad; A deep well region of the first type is located in the base; a well region of the second type is located in the deep well region of the first type; a first doped region of the first type is located in the second type In the well region of the state, and it is electrically connected with the input pad; a transistor is located on the substrate, wherein the first transistor has a gate, a source and a drain, and the drain is located on the first In the two-type well region and electrically connected to a control circuit power supply (Vcc), the source is located in the first-type deep well region; and a first-type second doped region is located in the first-type deep well region. Type I deep well area.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned electrostatic discharge protection circuit, one end of the diode is electrically connected to the input pad, and the other end is grounded.

In the aforementioned electrostatic discharge protection circuit, the gate and the source of the transistor and the second doped region of the first type are grounded.

In the aforementioned electrostatic discharge protection circuit, a part of the drain of the transistor is located in the second-type well region, and another part is located in the first-type deep well region.

In the aforementioned electrostatic discharge protection circuit, when the input pad receives an electrostatic current, the control circuit power supply (Vcc) is in the off state, the first doped region of the first type, the second type The well region of the first type and the deep well region of the first type constitute a first parasitic bicarrier transistor, and the well region of the second type, the deep well region of the first type and the drain of the transistor constitute A second parasitic bijac transistor, and the first parasitic bijac transistor and the second parasitic bijac transistor will form a forward loop.

In the aforementioned electrostatic discharge protection circuit, the first type is P-type, and the second type is N-type.

The purpose of the present invention and the solution to its technical problems are also achieved by the following technical solutions. According to an electrostatic discharge protection circuit proposed by the present invention, it is electrically connected to an input pad, and the electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad; A deep well region of the first type is located in the base; a well region of the second type is located in the deep well region of the first type; a first doped region of the first type is located in the second type in the well region of the second type, and it is electrically connected to the input pad; a second doped region of the second type is located in the well region of the second type, and it is electrically connected to a control circuit power supply (Vcc); a transistor on the substrate, wherein the first transistor has a gate, a source and a drain, the source and the drain are both located in the deep well region of the first type, And the drain is electrically connected to the control circuit power supply (Vcc); and a third doped region of the first type is located in the deep well region of the first type.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned electrostatic discharge protection circuit, one end of the diode is electrically connected to the input pad, and the other end is grounded.

In the aforementioned electrostatic discharge protection circuit, the gate and the source of the transistor and the third doped region of the first type are grounded.

In the aforementioned electrostatic discharge protection circuit, a part of the second-type second doped region is located in the second-type well region, and another part is located in the first-type deep well region.

The aforementioned electrostatic discharge protection circuit, wherein when the input pad receives an electrostatic current, the control circuit power supply (Vcc) is in the off state, the first doped region of the first type, the second type of The well region and the deep well region of the first type constitute a first parasitic bicarrier transistor, and the well region of the second type, the deep well region of the first type and the source of the transistor constitute a The second parasitic bijac transistor, and the first parasitic bijac transistor and the second parasitic bijac transistor form a forward loop.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from the above technical solutions, in order to achieve the aforementioned object of the invention, the main technical contents of the present invention are as follows:

The present invention proposes an electrostatic discharge protection circuit, which is electrically connected to an input pad. The electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad; A deep well region of the first type is located in the base; a well region of the second type is located in the deep well region of the first type; a first doped region of the first type is located in the well region of the second type In the region, and the first doped region of the first type is electrically connected to the input pad; a second doped region of the second type is located in the well region of the second type, and the second type of the The second doped region is electrically connected to a control circuit power supply (Vcc); a third doped region of the second type is located in the deep well region of the first type; and a fourth doped region of the first type The miscellaneous area is located in the deep well area of the first type.

The present invention also proposes another ESD protection circuit, which is electrically connected to an input pad. The ESD protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad. ; A deep well region of the first type is located in the substrate; a well region of the second type is located in the deep well region of the first type; a first doped region of the first type is located in the second type In the well region, and the first doped region of the first type is electrically connected to the input pad; a transistor is located on the substrate, wherein the transistor has a gate, a source and a drain, and the drain is located in the well region of the second type and is electrically connected to a control circuit power supply (Vcc), and the source is located in the deep well region of the first type; and a second doped region of the first type, Located in the first type of deep well area.

The present invention also proposes another electrostatic discharge protection circuit, which is electrically connected to an input pad. The electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad. ; A deep well region of the first type is located in the substrate; a well region of the second type is located in the deep well region of the first type; a first doped region of the first type is located in the second type In the well region of the first type, and the first doped region of the first type is electrically connected to the input pad; a second doped region of the second type is located in the well region of the second type, and the second type The second doped region in the state is electrically connected to a control circuit power supply (Vcc); a transistor is located on the substrate, wherein the first transistor has a gate, a source and a drain, and the source and the drain They are located in the deep well region of the first type, and the drain is electrically connected to the control circuit power supply (Vcc); and a third doped region of the first type is located in the deep well region of the first type.

It can be seen from the above that the present invention relates to an electrostatic discharge protection circuit, which is electrically connected to an input pad. The electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is connected to the above input pad electrical connection; a P-type deep well region, located in the substrate; an N-type well region, located in the P-type deep well region; a first P+ doped region, located in the N-type well region, and the first P+ doped region is It is electrically connected with the input pad; an NMOS transistor is located on the substrate, wherein the NMOS transistor has a gate, a source and a drain, and the drain is located in the N-type well region and is electrically connected to a control circuit power supply (Vcc), and the source is located in the P-type deep well region; and a second P+ doped region is located in the P-type deep well region. Compared with the traditional circuit design, the electrostatic discharge protection circuit of the present invention only needs a smaller area.

With the above technical solution, the electrostatic discharge protection circuit of the present invention has at least the following advantages:

1. Compared with the traditional electrostatic discharge protection circuit, the electrostatic discharge protection circuit of the present invention requires a much smaller area, so it is more suitable for practical use.

2. Since the area of the entire electrostatic discharge protection circuit is reduced, the load effect of parasitic capacitance can be reduced, so the electrostatic discharge protection circuit of the present invention can be applied to components with high-speed or high-voltage input requirements.

To sum up, the electrostatic discharge protection circuit with special structure of the present invention can make this kind of circuit design not need to use a large area, and can effectively achieve the effect of electrostatic discharge protection; in addition, the present invention can make this kind of protection circuit only A small area is required and it can be applied to input pads for high voltage or high speed. It has the above-mentioned many advantages and practical value, and there is no similar structural design publicly published or used in similar products, so it is indeed innovative. It has great improvements in both structure and function. It has made great progress, and has produced easy-to-use and practical effects, and has improved multiple functions compared with the existing electrostatic discharge protection circuit, so it is more suitable for practical use, and has wide application value in the industry. It is a novel, Progressive, practical new design.

The above description is only an overview of the technical solutions of the present invention. In order to understand the technical means of the present invention more clearly and implement them according to the contents of the description, the preferred embodiments of the present invention and accompanying drawings are described in detail below.

Description of drawings

FIG. 1A is a schematic cross-sectional view of an electrostatic discharge protection circuit according to a preferred embodiment of the present invention.

FIG. 1B is an equivalent circuit diagram of FIG. 1A .

FIG. 2A is a schematic cross-sectional view of an ESD protection circuit according to another preferred embodiment of the present invention.

FIG. 2B is an equivalent circuit diagram of FIG. 2A.

FIG. 3 is a schematic cross-sectional view of an ESD protection circuit according to another preferred embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of an ESD protection circuit according to another preferred embodiment of the present invention.

FIG. 5 is a circuit diagram of a control circuit in FIG. 5 .

FIG. 6 is a schematic cross-sectional view of an ESD protection circuit according to yet another preferred embodiment of the present invention.

7 is a schematic cross-sectional view of an ESD protection circuit according to another preferred embodiment of the present invention.

100: Base 101: P-type deep well area

102: N-type well area 104, 110, 150: P+ doped area

106, 108, 190: N+ doped region 109: Gate

112, 114: Parasitic bipolar transistor (parasitic bipolar transistor)

120, 130: diode (diode) 122: input pad

N, 180, 280: transistor (transistor) 400: control circuit

R1, R2, R: Resistor C: Capacitor

Detailed ways

In order to further explain the technical means and effects that the present invention adopts to achieve the intended purpose of the invention, the specific implementation, structure, characteristics and effects of the electrostatic discharge protection circuit proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. , as detailed below.

The electrostatic discharge protection circuit proposed by the present invention is particularly applicable to components with high-speed input pads, and the electrostatic discharge protection circuit provided by the present invention requires only a small area compared with the existing traditional electrostatic discharge protection circuit. The following preferred embodiments illustrate the present invention in detail, but are not intended to limit the present invention. In particular, in the following embodiments, the first type is P-type and the second type is N-type for illustration, but those skilled in the art should know that the first type can also be replaced by N type, replacing the second type with the P type.

first embodiment

Please refer to FIG. 1A and FIG. 1B , FIG. 1A is a schematic cross-sectional view of an ESD protection circuit according to a preferred embodiment of the present invention, and FIG. 1B is an equivalent circuit diagram of the ESD protection circuit in FIG. 1A . The ESD protection circuit of this embodiment is electrically connected to an input pad 122, and the ESD protection circuit includes: a diode 120, a deep well region 101 of a first type, and a well region 102 of a second type , a first doped region 104 of a first type, a second doped region 106 of a second type, a third doped region 108 of a second type, and a fourth doped region of a first type District 110.

Wherein, the diode 120 is formed in the substrate 100 , for example, it is composed of an N-type well region and a P+ doped region and an N+ doped region formed in the N-type well region. In a preferred embodiment, one end of the diode 120 is electrically connected to the input pad 122 , and the other end of the diode 120 is grounded.

In a preferred embodiment, the above-mentioned first-type deep well region 101 is, for example, a P-type deep well region, and the second-type well region 102 is, for example, an N-type well region. The impurity region 104 is, for example, a P+ doped region, the second type doped region 106 is, for example, an N+ doped region, and the second type third doped region 108 is, for example, an N+ doped region, and The fourth doped region 110 of the first type is, for example, a P+ doped region.

Wherein, the P+ doped region 104 is located in the N-type well region 102 . In a preferred embodiment, the P+ doped region 104 is electrically connected to the input pad 122 . In addition, the N+ doped region 106 is also located in the N-type well region 102 . In a preferred embodiment, the N+ doped region 106 is electrically connected to a control circuit power supply (Vcc). In addition, the P+ doped region 110 and the N+ doped region 108 are located in the P-type deep well region 101 . In a preferred embodiment, the P+ doped region 110 and the N+ doped region 108 are grounded.

Here, the N-type well region 102 and the P+ doped region 104 and N+ doped region 106 located in the N-type well region 102 constitute another diode 130 structure, and one end of the diode 130 is electrically connected to the input pad 122, The other end is electrically connected to the control circuit power supply (Vcc).

When attacked by electrostatic current, Vcc is off. At this time, electrostatic current will enter from the input pad 122 , and the protection mechanism of the electrostatic discharge protection circuit will be turned on. More detailed explanation is that when positive electrostatic current flows in from the input pad 122 , the diode 130 can conduct positive electrostatic current, and when negative electrostatic current flows in from the input pad 122 , the diode 120 can conduct negative electrostatic current. Moreover, the P+ doped region 104 , the N-type well region 102 and the P-type deep well region 101 form a PNP parasitic bicarrier transistor 112 , wherein R1 is the resistance value of the N-type well region 102 . The N-type well region 102 , the P-type deep well region 101 and the N+ doped region 108 form an NPN parasitic bicarrier transistor 114 , wherein R2 is the resistance value of the P-type deep well region. In particular, the base of the PNP parasitic bijac transistor 112 is connected to the collector of the NPN parasitic bijac transistor 114, and the base of the NPN parasitic bijac transistor 114 is connected to the collector of the PNP parasitic bijac transistor 112. Pole connected. In other words, the base of each parasitic bicarrier transistor is driven by the collector of another parasitic bicarrier transistor to form a positive feedback loop, and the formed PNPN semiconductor structure is A silicon controlled rectifier (silicon control rectifier, SCR) structure.

Therefore, in this embodiment, the electrostatic discharge protection circuit designed with diodes does not need to use a large-area MOS transistor, but an SCR structure composed of two diodes 120, 130 and parasitic bicarrier transistors 112, 114 constituted. Therefore, the electrostatic discharge protection circuit of the present invention can achieve the effect of electric discharge protection without using a large area.

In another preferred embodiment, as shown in FIG. 2A and FIG. 2B, the N+ doped region 106 described in FIG. 1A is arranged between the P+ doped region 104 and the N+ doped region 108, so that N The N+ doped region 106 in the P-type well region 102 is relatively close to the N+ doped region 108 in the P-type deep well region 101 . The N+ doped region 106 which is a part of the diode 130 can serve as a guard ring of a silicon controlled rectifier (SCR) at the same time.

In the embodiment of FIG. 2A and FIG. 2B , when the component is in normal operation, Vcc is in an open state, and at this time, the voltage from the base to the emitter of the PNP parasitic bipolar transistor 112 will be reverse-biased (reverse- biased), so that the PNP parasitic bipolar transistor 112 will not be turned on. And if the PNP parasitic bicarrier transistor 112 is not turned on, the forward feedback loop (or SCR) will not be formed, so the occurrence of the latch up phenomenon can be suppressed.

This is because, when a silicon controlled rectifier (SCR) needs electrons and holes during operation, and when electrons pass through the N+ doped region 106, they will be attracted by the N+ doped region 106, which will make the silicon controlled rectifier (SCR) ) is relatively difficult to be turned on, so the N+ doped region 106 acts as a guard ring to suppress the occurrence of the latch-up phenomenon.

When being attacked by electrostatic discharge, Vcc is in a closed state. At this time, when the electrostatic discharge current enters from the input pad 122, the circuit will form a positive feedback loop as shown in FIG. 1A and FIG. The silicon-controlled rectifier (SCR) composed of the carrier transistors 112 and 114 can thus play the role of electrostatic discharge protection.

In yet another preferred embodiment, as shown in FIG. 3 , the N+ doped region 106 in FIG. 2A is arranged in a special position, so that part of the N+ doped region 106 is located in a part of the N-type well region. 102 and part of the P-type deep well area 101.

In the embodiment shown in FIG. 3 , when the device is in normal operation, Vcc is turned on, and the N+ doped region 106 can also be used as a guard ring to suppress the latch-up phenomenon. And when subjected to the impact of electrostatic discharge, Vcc is the state of shutting down, and at this moment, because the junction breakdown voltage (for example, about 10～15V) of N+ doped region 106/P type deep well region 101, compared with that in FIG. 2 The breakdown voltage (for example, about 20-30V) of the N-type well region 102/P-type deep well region 101 junction is low, so the silicon-controlled rectifier (SCR) formed in FIG. 3 is compared with the silicon-controlled rectifier (SCR) formed in FIG. 2A. SCR) is relatively easy to be turned on, and can effectively play the role of electrostatic discharge protection.

In another preferred embodiment, as shown in FIG. 4 , a P+ doped region 150 is additionally arranged in the N-type well region 102 in FIG. 2A . In a preferred embodiment, the P+ doped region 150 is located in part of the N-type well region 102 and part of the P-type deep well region 101 . In a more preferred embodiment, the P+ doped region 150 is further electrically connected to a control circuit 400 to control the P+ doped region 150 to be grounded during normal operation, and to control the P+ doped region 150 to be subjected to electrostatic current. The attack is floating (float) state.

In a preferred embodiment, the circuit diagram of the control circuit 400 is shown in FIG. 5 , and point B in FIG. 5 is connected to the P+ doped region 150 . The control circuit 400 includes an NMOS transistor N, a resistor R and a capacitor C. Wherein, when in normal operation, Vcc is turned on, and point A has a relatively high potential at this time, so that the NMOS transistor N is turned on. That is to say, point B has a relatively low potential at this time, and can ground the P+ doped region 150 . When being impacted by electrostatic discharge, since Vcc is floating or relatively low potential, the NMOS transistor N is turned off, and point A has a relatively low potential. That is to say, point B is in a floating state at this time, so that the P+ doped region 150 will not be grounded.

In particular, the resistor R and the capacitor C are designed as a delay circuit so that when there is static electricity flowing in, the speed at which the current reaches point A is slowed down, so that the static electricity has sufficient time to discharge.

In the embodiment shown in FIG. 4, when the device is in normal operation, Vcc is turned on. At this time, the grounded P+ doped region 150 will attract holes, thus making it difficult to form a forward loop (or SCR). , so that the occurrence of the latch-up phenomenon can be suppressed.

However, when the device shown in FIG. 4 is impacted by electrostatic discharge, Vcc is turned off, and the P+ doped region 150 is not grounded and is in a floating state. Moreover, due to the breakdown voltage of the junction of the P+ doped region 150/N-type well region 102 (for example, about 10-15V), compared with the breakdown voltage of the junction of the N-type well region 102/P-type deep well region 101 in FIG. 2A (For example, about 20-30V) is low, so the silicon-controlled rectifier (SCR) formed in Figure 4 is relatively easier to be turned on than the silicon-controlled rectifier (SCR) formed in Figure 2A, and can be more effective Play the role of electrostatic discharge protection.

second embodiment

Please refer to FIG. 6 , which is a schematic cross-sectional view of an electrostatic discharge protection circuit according to a preferred embodiment of the present invention. The ESD protection circuit of this embodiment is electrically connected to an input pad 122, and the ESD protection circuit includes: a diode 120, a deep well region 101 of a first type, and a well region 102 of a second type , a first type doped region 104 , a transistor 180 and a first type second doped region 110 .

Wherein, the diode 120 is formed in the substrate 100 , for example, it is composed of an N-type well region and a P+ doped region and an N+ doped region formed in the N-type well region. In a preferred embodiment, one end of the diode 120 is electrically connected to the input pad 122, and the other end of the diode 120 is grounded.

In a preferred embodiment, the above-mentioned first-type deep well region 101 is, for example, a P-type deep well region, and the second-type well region 102 is, for example, an N-type well region. The impurity region 104 is, for example, a P+ doped region, the transistor 180 is, for example, an NMOS transistor, and the second doped region 110 of the first type is, for example, a P+ doped region.

Wherein, the P+ doped region 104 is located in the N-type well region 102 . In a preferred embodiment, the P+ doped region 104 is electrically connected to the input pad 122 . In addition, the P+ doped region 110 is located in the P-type deep well region 101 . In a preferred embodiment, the P+ doped region 110 is grounded. In addition, the NMOS transistor 180 is formed on the substrate 100 , and the NMOS transistor 180 includes a gate 109 , a drain 106 and a source 108 . In a preferred embodiment, the drain 106 of the NMOS transistor 180 is electrically connected to the control circuit power supply (Vcc), and the gate 109 and the source 108 thereof are grounded. In a more preferred embodiment, the drain 106 of the NMOS transistor 180 is formed in a part of the well region 102 and a part of the deep well region 101 of the P type.

Here, the N-type well region 102, the P+ doped region 104 and the drain 106 located in the N-type well region 102 constitute another diode 130 structure, and one end of the diode 130 is electrically connected to the input pad 122, and the other end is electrically connected to the input pad 122. One end is electrically connected to the control circuit power supply (Vcc).

When the component is in normal operation, Vcc is on. At this time, the drain 106 of the transistor 180 can serve as a guard ring to suppress the occurrence of the latch-up phenomenon.

When being attacked by electrostatic current, Vcc will be turned off, and at this time, electrostatic current will enter from the input pad 122, and the protection mechanism of the electrostatic discharge protection circuit will be turned on. Please refer to FIG. 6 , under the design of the ESD protection circuit, the P+ doped region 104 , the N-type well region 102 and the P-type deep well region 101 will form a PNP parasitic bicarrier transistor 112 . The N-type well region 102 , the P-type deep well region 101 and the source 108 form an NPN parasitic bicarrier transistor 114 , wherein R2 is the resistance value of the P-type deep well region. In particular, the base of the PNP parasitic bijac transistor 112 is connected to the collector of the NPN parasitic bijac transistor 114, and the base of the NPN parasitic bijac transistor 114 is connected to the collector of the PNP parasitic bijac transistor 112. Pole connected. In other words, the base of each parasitic bicarrier transistor is driven by the collector of another parasitic bicarrier transistor to form a positive feedback loop, and the formed PNPN semiconductor structure is A silicon controlled rectifier (silicon control rectifier, SCR) structure.

The electrostatic discharge protection circuit of this embodiment is similar to the structure of the first embodiment (shown in FIG. 3 ), the only difference is that an additional gate 109 is formed on the substrate 100, so that the gate 109 and its two sides can be The N+ doped regions 106, 108 form an NMOS transistor. Therefore, the area required by the electrostatic discharge protection circuit in FIG. 6 is almost or even the same as that required by the circuit in FIG. The required area is relatively small.

In particular, since the electrostatic discharge protection circuit of FIG. 6 has the design of the NMOS transistor 180, and generally when the gate of the NMOS transistor is grounded, in the voltage collapse behavior of the components, the breakdown voltage of the gate (gated) can be clearly found ( About less than 7~8V) is lower than the junction breakdown voltage. Therefore, when being impacted by electrostatic discharge, the design of the electrostatic discharge protection circuit in FIG. 6 can enable the silicon controlled rectifier (SCR) to exert a better electrostatic discharge protection capability.

In another preferred embodiment, please refer to FIG. 7 . The ESD protection circuit in FIG. 7 is similar to the ESD protection circuit in FIG. 3 , except that an NMOS transistor 280 is formed on the substrate 100 . The NMOS transistor 280 includes a gate 109 , a source 190 and a drain 108 . The drain 108 of the NMOS transistor 280 is electrically connected to Vcc, and the source 190 and gate 109 of the NMOS transistor 280 are grounded.

The function of the electrostatic discharge protection circuit in FIG. 7 is similar to that in FIG. 6 , which is another structural variation of FIG. 6 .

It can be known from the above embodiments that the ESD protection circuit of the present invention requires much smaller area than the conventional ESD protection circuit. Since the area of the entire ESD protection circuit is reduced, the load effect of parasitic capacitance can be reduced, so the ESD protection circuit of the present invention can be applied to components with high-speed or high-voltage input requirements.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but all the content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence still belong to the scope of the technical solutions of the present invention.

Claims (20)

1. An electrostatic discharge protection circuit, which is electrically connected to an input pad, is characterized in that the electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad; a deep well region of a first type located in the substrate; a second type of well located within the first type of deep well; a first type doped region located in the second type well region and electrically connected to the input pad; a second-type second doped region located in the second-type well region and electrically connected to a control circuit power supply (Vcc); a third doped region of the second type located in the deep well region of the first type; and A fourth doped region of the first type is located in the deep well region of the first type. 2. The electrostatic discharge protection circuit according to claim 1, wherein one end of the diode is electrically connected to the input pad, and the other end is grounded. 3. The electrostatic discharge protection circuit according to claim 1, wherein the third doped region of the second type and the fourth doped region of the first type are grounded. 4. The electrostatic discharge protection circuit according to claim 1, wherein the second doped region of the second type is located at the first doped region of the first type and the second doped region of the second type Between the third doped region. 5. The electrostatic discharge protection circuit according to claim 4, wherein said part of the second type of second doped region is located in the second type of well region, and the other part of The second doped region of the second type is located in the deep well region of the first type. 6. The ESD protection circuit according to claim 4, further comprising a fifth doped region of the first type, located in part of the well region of the second type and part of the first type In the state of the deep well area. 7. The electrostatic discharge protection circuit according to claim 6, wherein the fifth doped region of the first type further includes a control circuit electrically connected to control the fifth doped region of the first type. Whether the five-doped region is grounded. 8. The electrostatic discharge protection circuit according to claim 1, wherein when the input pad receives an electrostatic current, the control circuit power supply (Vcc) is turned off, and the first type of the first The doped region, the second type well region and the first type deep well region constitute a first parasitic bicarrier transistor, and the second type well region, the first type deep well region And the third doped region of the second type constitutes a second parasitic bipolar transistor, and the first parasitic bipolar transistor and the second parasitic bipolar transistor constitute a forward loop. 9. The ESD protection circuit according to claim 1, wherein the first type is P-type, and the second type is N-type. 10. An electrostatic discharge protection circuit, which is electrically connected to an input pad, characterized in that the electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad; a deep well region of a first type located in the substrate; a second type of well located within the first type of deep well; a first type doped region located in the second type well region and electrically connected to the input pad; a transistor on the substrate, wherein the first transistor has a gate, a source and a drain, the drain is located in the second type well region and is electrically connected to a control circuit power supply ( Vcc), the source is located in the deep well region of the first type; and A first-type second doped region is located in the first-type deep well region. 11. The ESD protection circuit according to claim 10, wherein one end of the diode is electrically connected to the input pad, and the other end is grounded. 12. The electrostatic discharge protection circuit according to claim 10, wherein the gate and the source of the transistor and the second doped region of the first type are grounded. 13. The electrostatic discharge protection circuit according to claim 10, wherein a part of the drain of the transistor is located in the well region of the second type, and another part is located in the well region of the first type in the deep well area. 14. The electrostatic discharge protection circuit according to claim 10, wherein when the input pad receives an electrostatic current, the control circuit power supply (Vcc) is in the off state, and the first type of the first doped The heterogeneous region, the second type well region and the first type deep well region constitute a first parasitic bicarrier transistor, and the second type well region, the first type deep well region and The drain of the transistor constitutes a second parasitic bipolar transistor, and the first parasitic bipolar transistor and the second parasitic bipolar transistor constitute a forward feedback loop. 15. The electrostatic discharge protection circuit according to claim 10, wherein the first type is P-type, and the second type is N-type. 16. An electrostatic discharge protection circuit, which is electrically connected to an input pad, characterized in that the electrostatic discharge protection circuit includes: a diode configured in a substrate, and the diode is electrically connected to the input pad; a deep well region of a first type located in the substrate; a second type of well located within the first type of deep well; a first type doped region located in the second type well region and electrically connected to the input pad; a second-type second doped region located in the second-type well region and electrically connected to a control circuit power supply (Vcc); A transistor located on the substrate, wherein the first transistor has a gate, a source and a drain, the source and the drain are located in the first type deep well region, and the drain is electrically connected to the control circuit power supply (Vcc); and A first-type third doped region is located in the first-type deep well region. 17. The electrostatic discharge protection circuit according to claim 16, wherein one end of the diode is electrically connected to the input pad, and the other end is grounded. 18. The electrostatic discharge protection circuit according to claim 16, wherein the gate and the source of the transistor and the third doped region of the first type are grounded. 19. The electrostatic discharge protection circuit according to claim 16, wherein a part of the second-type second doped region is located in the second-type well region, and another part is located in the second-type well region. In the deep well area of the first type. 20. The electrostatic discharge protection circuit according to claim 16, wherein when the input pad receives an electrostatic current, the control circuit power supply (Vcc) is in the off state, and the first type of the first doped The heterogeneous region, the second type well region and the first type deep well region constitute a first parasitic bicarrier transistor, and the second type well region, the first type deep well region and The source of the transistor constitutes a second parasitic bipolar transistor, and the first parasitic bipolar transistor and the second parasitic bipolar transistor constitute a forward loop.

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