CN1713301A - Over-erase correction method and circuit of flash EEPROM - Google Patents

Abstract

An over-erase correction method for flash EEPROM and its circuit, wherein the method for over-erase correction of memory cells in the memory array after data erasure comprises the following steps: selecting a first bit line with leakage current exceeding a threshold value, and setting the gate voltage of the memory cell coupled with the first bit line as an initial voltage value; (b) applying a series of overerase correction pulses to the selected first bit line during a predetermined time period; (c) checking whether the first bit line has a leakage current exceeding a threshold value within a preset time limit; (d) if the first bit line still has a leakage current exceeding the threshold value after the predetermined time period has passed, increasing the gate voltage and repeating the steps (b) and (c); and (e) if the leakage current of the first bit line is detected to be below the threshold value within the predetermined time period, selecting a second bit line and repeating the steps to (d).

Description

Over-erase correction method and circuit of flash EEPROM

technical field

The present invention relates to an integrated circuit memory, and in particular to an array comprising flash memory cells (flash memory cells), and providing flash memory cells with Over erase correction (overerase correction) circuit.

Background technique

What Fig. 1 shows is a typical integrated circuit, which includes flash electrically erasable programmable read-only memory (flash electrically erasable programmable read-only memory, hereinafter referred to as flash EEPROM) array 100, and provides circuit for fast The memory cells within the flash EEPROM array 100 implement circuitry for programming, erasing, reading, and over-erase correction. Flash EEPROM array 100 is composed of individual cells, such as cell 102 . Each unit cell has a drain coupled to a bitline, such as bitline 104, and each bitline is coupled to a bitline switching circuit 106 and a row decoder (columndecoder). )108. The sources (source) of each unit cell in the array are connected to each other and are coupled to a common source signal (common source signal) VSL, while the gates (gate) of each unit cell are coupled to row decoder 110 .

The column decoder 110 receives the voltage signal from the power supply 112 , and is controlled by a row address (row address) issued by a processor (processor) or a state machine (state machine) 114 to distribute a special voltage signal to the word line. Similarly, the bit line switching circuit 106 also receives the voltage signal from the power supply 112 , and is controlled by the signal sent by the processor 114 to distribute a specific voltage signal to the bit line. The voltage sent by the power supply 112 is also controlled by the signal sent by the processor 114 .

The row decoder 108 is controlled by a column address signal from the processor 114 and sends signals from the bit lines to a sense amplifier or comparator 116 . The power supply 112 provides voltage to the row decoder 108 and all bit lines 104 . Sense amplifier 116 also receives signals from reference cells within reference array 118 . With signal inputs from row decoder 108 and reference array 118, sense amplifier 116 provides a signal to indicate the state between a bit line and a reference cell line, where the signal passes through A data latch or buffer 120 is sent to the processor 114 .

To write to a certain unit cell in the flash memory array 100, the power supply 112 will provide a high voltage gate-to-source pulse to the unit cell, and the source of the unit cell must be grounded simultaneously. . For example, during programming, multiple gate voltage pulses of about 10 volts are sent to a unit cell, each lasting about three to six microseconds (microsecond), while the drain voltage of the unit cell remains at 4.5 volts, and Its source is grounded. This drain-to-source bias of 4.5 volts generates hot electrons near the drain. A high voltage pulse from the gate-source gives hot electrons the opportunity to overcome the energy barrier formed by the channel and a thin dielectric layer, and drive the hot electrons into the floating state of the unit cell. gate. This programming process, called "hot electron injection," raises the cell's threshold voltage, the gate-to-source voltage required to make the cell conduct.

In order to erase a certain cell of the flash memory array 100, generally speaking, a procedure of "Fowler-Nordheim tunneling" is used, that is, a high negative gate-source voltage pulse is continuously applied. , each lasting a few milliseconds. For example, during an erase process, several -10V gate voltage pulses may be applied to a cell, wherein the source voltage of the cell is maintained at 5.5V and its drain is floating. This highly negative gate-source voltage pulse lowers its threshold voltage, allowing electrons to tunnel away from the floating gate of the memory cell.

In a flash memory array, all cells are usually erased at once, usually by applying several short erase pulses in succession to each cell in the array (eg, flash memory array 100 ), as described above. mentioned. After each erase pulse, there is an erase verify (erase verify) step, which checks one by one whether the threshold voltage of each memory cell in the array is higher than a certain value, such as about 3.0 volts, or the cell The cells are not completely erased (undererased). When performing erase confirmation, if the current is measured, as described above, that is to say, the threshold voltage is less than 3 volts, it means that the cell has been erased. If an incompletely erased cell is found, another erase pulse is typically applied to the entire array until the cell is successfully erased. Under such an erasing procedure, even if the unit cell is successfully erased for the first time, it may be repeatedly erased several times, and finally the threshold voltage of its control gate may be reduced to below 0 volts. If the threshold voltage of a unit cell is erased below 0.5V or even below 0V, it is called "overerased".

The over-erased cell will also generate a leakage current at a gate-source voltage of 0 volts because the threshold voltage is too low. Cell leakage can cause non-negligible bit line currents, resulting in read and write errors. Therefore, over-erase correction is required to reduce the aforementioned bit line current. During over-erase correction, in the flash memory array 100, all the unit cells coupled to the same bit line have the same gate-source voltage, and the source is all grounded, and the drain voltage remains at About 5 volts. In this way, hot electrons are re-injected into the floating gate to increase the threshold voltage of the cell on the bit line.

During the writing process, the current on a bit line is composed of the output current of the unit cell in the writing state and the output currents of other unselected unit cells on the same bit line. Generally, the gate-source voltage of unselected cells is at ground level. During over-erase correction, the current on a bit line is the sum of the output currents of all unit cells coupled to the bit line. If over-erase correction is performed by the bit lines, all cells will have the same gate-to-source voltage. If over-erase correction is performed by cells, the gate-source voltage of the selected cell will be different from other cells.

To store a data bit (bit) in the floating gate of a unit cell, it will go through the aforementioned writing and erasing steps. After the write state, the threshold voltage of the unit cell is usually kept above about 5.0V; and after the erased state, the threshold voltage of the unit cell is usually limited below about 3.0V. If one wants to read a cell, the control gate voltage is between 3.0 volts and 6.5 volts, usually 5 volts. The 5 volt read pulse is supplied to the gate of an array cell and a cell in the reference array 118 with a threshold voltage close to 3.5 volts. The programmed cell in the array 100 has a threshold voltage greater than 5.0 volts, and its output current is lower than the current supplied by the reference cell whose threshold voltage is 3.5 volts, indicating that the memory cell has been written with data. Erased data cells in array 100 have a threshold voltage lower than 3.0 volts and output currents greater than the current supplied by the reference cell whose threshold voltage is 3.5 volts to indicate that the memory cell has been erased. . When confirming writing or erasing, the read voltage is also input to one cell of the memory array and one cell of the reference array 118 . When confirming writing, a reference cell with a critical value of 5.0 volts is used for comparison; when used for confirming erasing, a reference cell with a critical value of 3.0 volts is used for comparison.

It is not good for cells to be over-erased because they will leak current during writing or reading. For example, when writing or reading, only one word line will have a positive voltage, while the other word lines are usually grounded. When the word line is grounded or the voltage is 0V, the cell whose threshold voltage is lower than about 0.5V will generate cell leakage current. A bit line may be coupled to as many as 512 cells, and if each cell generates a small amount of leakage current, the total current added up cannot be ignored. If the over-erased cell operates in the sub-threshold region, coupled with high temperature, the leakage current will be amplified by more than one level. Once a leakage current occurs during the writing process, it may overload the power supply that provides the bit line power. Also, during the read process, leakage current on the bit lines may cause read errors.

In order to avoid over-erasing, manufacturers of integrated circuits containing flash memory cells provide over-erasing correction mechanisms, usually by erasing the over-erased cells and increasing their threshold voltages to a lower limit. Converging the threshold voltage after erasing can avoid write or read errors caused by leakage current from over-erase cells. US Pat. No. 5,642,311 to Cleveland et al. proposes a circuit for sensing over-erased cells and applying programming pulses to bring the threshold voltage back to an acceptable value. The circuit of Cleveland et al. uses ground as the word line voltage and 5 volts as the bit line voltage when sending over-erase correction pulses. This method cannot provide sufficient bit line voltage when the bit line leakage current increases. FIG. 2 is a circuit diagram showing a bit line 104, a memory cell 102, and the write circuits associated therewith. If the power supply voltage VCC is lower than 5 volts, such as 3 volts or lower, a charge pump is used to increase the bit line voltage VBL to above 3 volts during writing or over-erasing correction. Charge pumps are usually used in small power devices, such as battery-operated notebook computers, in which the flash memory array is a 3-volt circuit device. For over-erase correction to be efficient, the charge pump must be able to withstand the bit line leakage current. FIG. 2 shows the path of the current I entering the unit cell 102 from the P-type metal-oxide-semiconductor field-effect transistor (MOSFET) QP0 through the bit line 104 during over-erase correction. VDQ1 is the output of the charge pump circuit. If VCC is high enough, there is no need for a charge pump circuit. VDQ2 is a regulated voltage, which is also the bit line voltage standard during over-erase correction. VR is the bandgap reference voltage, input to differential amplifier 122, which converts VDQ2 to VR*((Ra+Rb)/Ra), because VD=VR and VD=VDQ2*(Ra /(Ra+Rb)). If the bit line leakage current is larger than the charge pump current, VDQ1 and VDQ2 will drop below the standard value, which reduces the efficiency of over-erase correction. A bit switch 124 is selected by the row decoder to open a path from VDQ2 to the selected bit line 104 . In FIG. 2, the bit switcher 124 includes pass transistors Qbs0, Qbs1 and Qbs2. Every time a pass transistor is passed, the voltage will drop, making VBL even lower than the standard value, so that VBL is equal to VDQ2-(I*Req), where Req is bit switch 124 and PMOSFET QPL[ n] equivalent resistance (equivalent resistance), and I is the bit line current. The P-type metal oxide semiconductor field effect transistor QPL[n] is an I/O switching transistor, which is coupled to a plurality of bit lines sharing one I/O, and is used to select a group of related I/Os when writing data. bit line. The voltage drop across the bit switcher 124 increases as the current on the bit line 104 increases.

US Patent No. 6,046,932 by Bill et al. proposes a solution to the problems of the aforementioned Cleveland et al. patent. It connects a resistor in series between the source of the memory cell and ground. In this way, the leakage current increases the source voltage, and the unselected cells are forced to have lower leakage current by the auto-occurring body effect. This method is used for write and over-erase corrections. The drain to source voltage will be lower than VDQ2. In order to improve the efficiency of over-erase correction and programming, VDQ2 will be kept at a higher target value to maintain a sufficiently high drain-to-source voltage. However, when the leakage current of the bit line decreases, the voltage drop across the resistor also decreases, and the drain-to-source voltage increases and approaches VDQ2. The drain-to-source voltage can vary by as much as 1 volt. At this time, the drain-to-source voltage may be too high, which damages the Si-SiO ₂ interface of the memory cell due to the generation of more hot holes. The result is that the reliability of writing and erasing gradually decreases.

Therefore, we need a method and circuit that can control the bit line current and improve the efficiency of the over-erase correction during over-erase correction.

Contents of the invention

It is an object of the present invention to provide a method for performing erase correction after memory cells in a memory array have been erased, the method comprising the steps of: (a) selecting a leakage current exceeding a threshold value the first bit line, and set the gate voltage of the memory unit cell coupled to it to an initial voltage value; (b) within a preset time limit, apply a voltage to the selected first bit line A series of erase correction pulses; (c) within the preset time limit, check whether the first bit line has a leakage current exceeding the critical value; (d) if the preset time limit is exceeded, the first bit line still has a leakage current exceeding the critical value When the leakage current exceeds a certain value, the gate voltage is increased, and steps (b) and (c) are repeated; and (e) if within the preset time limit, it is detected that the leakage current of the first bit line is below the critical value, Then select a second bit line, and repeat steps (a) to (d).

Description of drawings

In order to make the above and other objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below with accompanying drawings.

FIG. 1 is an embodiment of a known technology, that is, an integrated circuit, including a flash EEPROM memory array, and circuits responsible for writing data, erasing data, reading data and correcting erase in the array.

FIG. 2 is a bit line in a memory array, including circuits responsible for programming and over-erase correction.

FIG. 3 is a flowchart of an exemplary over-erasure correction method.

FIG. 4 is an embodiment of a circuit for supplying a word line voltage to a memory cell during over-erase correction.

Detailed ways

In the present invention, a method for overerase correction of memory cells in a memory array is provided. In one embodiment, the memory array includes flash memory cells. The method can control the current through the bit line during over-erase correction, so as to maintain an appropriate bit line voltage during the correction process.

The flowchart of Fig. 3 is an embodiment of the present invention. In step 300, it starts the erasure correction algorithm. This algorithm is more suitable for multiple bit lines in the same memory array, and in one embodiment, the over-erase correction is used on selected I/O, and is used on the selected bit line . Therefore, in step 302, the row address (columnaddress) of the row decoder (column decoder) will correspond to the first selected bit line corresponding to each I/O in the storage array, thereby selecting the accepted bit line First bit line corrected by erasing. As shown in Figure 3, a flag (or other indicator) is set corresponding to an initial voltage applied to the word line of each memory cell for the selected bit line (word line). The values of the initial voltage and the subsequent voltage (described later) are determined according to the design of the memory array and its memory cells. In one embodiment, the initial value of the word line voltage is set as a negative value, and then a positive value is added each time until the maximum value. In one embodiment, the initial voltage is -2.0 volts, incremented by 0.5 volts each time, four times in total, until the maximum value is 0 volts. However, it should be noted that how to select the word line voltage value during over-erase correction must be determined according to the characteristics of the memory cell. The incrementing step is explained in detail later along with step 320 .

In step 304, the word line voltage WL is set as a confirmation voltage to determine whether there is an over-erased cell in the selected bit line, that is, the leakage current of the bit line Whether the preset critical value is exceeded. The verification voltage can be set to 0 volts or higher to ensure that the leakage current of the bit line is small enough. In step 306, it is determined whether the selected bit line has any over-erased cells. This step tests the total leakage current of the bit lines. The verification step is to ground the word line, apply about 1.0 volts to the selected bit line, and then sense the bit line current. If the bit line current exceeds a preset value, it means that at least one cell coupled to the bit line has been erased and has leakage current. If the bit line has no erased cells, in step 310, the row address will be checked to determine the last bit in the memory array or sector to be erased corrected in the memory array Whether the line's row address has been reached. If the last row address has been reached, it means that all the bit lines have been erased and corrected, and the erased correction process ends at step 314 . In step 310, if the maximum row address has not been reached, the row address is incremented to the next row, and the over-erase corrected voltage flag is reset to the initial value (step 312). In step 306, an over-erase confirmation is then performed on the next selected bit line.

If it is determined in step 306 that the current bit line has "leakage", that is, the leakage current is greater than the threshold set by the reference cell (reference cell) current when performing the verification, the method will check the first stage of the erase correction Whether the time limit has been exceeded (step 316). The bit line leakage may come from one or a few heavily over-erased cells, from many lightly over-erased cells, or a combination of both. In this embodiment, each word line voltage applied for over-erase correction corresponds to a "stage" of over-erase correction. In one embodiment, each stage lasts about 20 to 100 milliseconds, and a suitable time is about 50 milliseconds. A timer in the timing circuit is started in each stage, for example, it can be started when the first over-erase correction pulse is applied in each stage (step 308 ). In step 316, if the time limit has not expired, the drain of the memory unit cell of the selected bit line will receive an over-erase correction pulse (step 308), at this time the word line of each unit cell The voltage is set to the word line voltage identified by the word line voltage flag. This time period can be a preset time, or a preset number of pulses, or even a combination of both. For example, in addition to checking whether the time limit is exceeded, the method can also check the number of applied over-erase correction pulses, for example, a phase time limit may include five pulses. In this embodiment, the "preset time limit" may be a preset period of time, or a preset number of pulses. In the first stage of the over-erase correction algorithm, the word line voltage is set to an initial voltage value (eg -2.0V).

In one embodiment, the over-erase correction pulse of step 308 lasts about 0.5 to 2.0 milliseconds, and a suitable time is about 1.0 milliseconds.

In step 308, after a pulse is issued, the word line voltage is set to the verify voltage (step 304), and then step 306 is used to test the bit line for erased cells. Collectively, the total number of pulses that can be emitted within a preset time limit is called a "series of pulses". If the bit line is determined to be free of leakage, the algorithm proceeds to step 310, details as previously described. If there is still leakage on the bit line (that is, step 308 is not enough to correct the over-erased condition), step 316 checks the timer again. If the timer has not expired, the next over-erase correction pulse or series of pulses is issued in step 308, and the word line voltage is also set to confirm the word line voltage by the word line voltage flag. This loop (steps 316, 308, 304, 306) is repeated until it is determined that the bit line has no leakage (step 306) or the time limit has expired (step 316). In step 316, if the time limit is exceeded, it is checked in step 318 whether the maximum word line voltage has been reached, that is, whether the word line voltage flag has been set to the allowable maximum word line voltage value.

If the allowable maximum word line voltage has been reached in step 318, an error flag will be set in step 322 to indicate that the bit line has at least one over-erased cell, and the over-erase correction algorithm Law has been completed. For example, severely overerased cells may not be correctable. Each bit line has a bit switch driven by a row decoder. The transistor size of these bit switches is limited. If the leakage current of the bit line is too large, the voltage drop caused by these bit switches cannot be ignored, and the drain-to-source voltage will also decrease, which will reduce the efficiency of over-erase correction, resulting in fail.

In step 318, if the word line voltage has not reached the maximum value, in step 320 the word line voltage flag is incremented to indicate the next highest word line voltage value. For example, as mentioned above, the initial word line voltage during over-erase correction is -2.0 volts, and then increases by 0.5 volts until the maximum value is 0 volts. In this embodiment, in step 320 , the word line voltage flag is incremented to indicate -1.5 volts for the first time, and the timer is restarted to start timing after being cleared. In step 308, over-erase correction is performed, that is, by applying an over-erase correction pulse or series of pulses to the drain of the memory cell of the selected bit line, the word line voltage Set to the value indicated by the word line voltage flag. The validation procedure (steps 304 and 306) and other steps of FIG. 3 are then performed as previously described.

The algorithm in Figure 3 can converge the threshold voltage of the selected bit line to an acceptable range when detecting an over-erased cell on the bit line, while avoiding Excessive total leakage current. Furthermore, since the over-erase state of the memory cell is checked after each over-erase correction pulse before each increment of the word line voltage, the algorithm avoids the use of excessive or unnecessary pulses , to provide an efficient over-erase correction method that saves time and energy, while still ramping up the word line voltage when necessary.

As mentioned above, the present invention provides a method and structure for erasing and correcting the memory cells in the memory array after erasing the data of the memory cells, including the following steps: (a) selecting Determining the first drain potential element line, and setting the gate voltage of the memory unit cell coupled to it to an initial voltage value; (b) applying a voltage to the selected bit line within a preset time limit A series of over-erase correction pulses; (c) within the preset time limit, check whether there is leakage on the bit line; (d) if the preset time limit has passed and the bit line still has leakage, increase the gate voltage and repeat Steps (b) and (c); and (e) if it is detected that the bit line has no leakage within the preset time limit, then select the next bit line, and repeat steps (a) to (d).

Referring now to FIG. 4, the function of the circuit 400 is to provide the word line voltage to the memory cell during over-erase correction. The word line voltage in FIG. 4 is represented by VNG(WL). Circuit 400 is designed to initially supply negative initial word line voltages, and then increment positive values as needed in conjunction with the over-erase correction algorithm shown in FIG. 3 . Of course, other circuits can also be used to provide this step-wise word line voltage. For example, the tunable resistance ladder 406 can be replaced with other tunable resistance circuits. Circuit 400 includes charge pump circuit 402 to generate negative voltage VNG. The bandgap reference voltage VR is generated by a bandgap reference circuit (not shown). The voltage VR can be multiplied by several times (multiply) and input to a differential amplifier (differential amplifier). The voltage fVR is the reference voltage VR multiplied by f times, first passes through the first resistance divider (resistance divider) 406, and then is input into the differential amplifier, which is marked as the comparator 404 in FIG. 4 . The value of "f" varies with the circuit design, and in an embodiment, it is approximately between 1 and 3, and a more suitable value is 2. The voltage gVR is multiplied by g times the reference voltage VR, first passes through the second resistor divider 408 , and then is input into the comparator 404 . The value of "g" varies with the circuit design, and in an embodiment, it is approximately between 1 and 3, and a more suitable value is 2. In one embodiment, fVR and gVR are generated by a voltage regulator circuit, and VR is set to be about 1.2 volts.

The comparator 404 has two input voltages, VRN (the output of the first resistive divider 406 ) and VD (the output of the second resistive divider 408 ). The voltage VRN is determined by the signals F[0:n], each of which corresponds to one of the aforementioned word line voltage flags. The value of VRN is equal to fVR*R1[k]/(R1[k]+R2[k]), where “k” is a number from 0 to n, corresponding to an over-erase correction stage mentioned above. When VD and VRN are in regulation, they remain the same, that is, if VD is not equal to VRN, the circuit of Figure 4 will force VD to be equal to VRN. VD is equal to (gVR-VNG)*(Rb/(Ra+Rb))+VNG. In one embodiment, a negative bias VNG is allowed for the resistors Ra and Rb, wherein the resistors Ra and Rb are formed of strip-shaped polysilicon or p+ diffusion regions. The N well (N-well) surrounding the p+ diffusion region should be connected to a voltage of gVR or higher.

In the embodiment of FIG. 4, only one signal (eg, F[k]) among F[0:n] is valid in any over-erase correction phase. In one embodiment, F[0:n] corresponds to word line voltage flags and can be generated or supplied by a shift register. During over-erase correction, the number of available incremental word line voltages is n+1. In the embodiment of FIG. 4, in the first stage of over-erase correction, that is, when the word line voltage is about to be set to an initial value, F[0] is set to a logical value 1 (logical one), and F[1 ] to F[n] are set to the logical value 0 (logical zero). When F[0] is set to logic 1, the switching transistors 410 and 412 coupled to F[0] are turned on, while the other switching transistors 410 and 412 are turned off, thereby allowing the voltage fVR to pass through A resistor circuit including resistors R1 [ 0 ] and R2 [ 0 ] reaches the positive contact of the comparator 404 . In the second stage (that is, after the first stage), F[0], F[2] to F[n] are all set to 0, and F[1] is set to 1 until the The second stage (step 316) or over-erasure correction has been confirmed (step 306). When F[1] is set to a logic value of 1 and other signals are set to a logic value of 0, the switching transistors 410 and 412 coupled to F[1] are in the ON state, while the other switching transistors 410 and 412 are in the ON state. The off state, thereby allowing the voltage fVR to reach the positive contact of the comparator 404 through the resistor circuit including the resistors R1[1] and R2[1]. In the last stage of over-erase correction, that is, when the word line voltage is set to the maximum value (provided that for the same bit line, the previous stages of over-erase correction are not enough), F[n] is set to logical value 1, and F[0] to F[n-1] are set to logical value 0. As mentioned above, there are n+1 stages in the over-erasure correction in this embodiment. When the corresponding switching transistors 410 and 412 of a certain stage are triggered by the signal F[0:n], a corresponding R1[0:n] and R2[0:n] will be selected to provide the voltage VRN, thereby forcing the voltage VD to generate a suitable The word line voltage VNG(WL) at this stage (for example, -2.0V, -1.5V, -1.0V, -0.5V or 0V in one embodiment).

As before, circuit 400 forces VD to be equal to VRN. Since VRN is coupled to the positive node of the differential amplifier 404, the amplifier 404 will output a high voltage when VRN is greater than VD. This means that the negative value of VNG is too large, and the leakage path 414 will open to pull VNG high, making VD equal to VRN. In one embodiment, the leakage path 414 is made of a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) and/or a triple well N-type metal-oxide-semiconductor field-effect transistor. Composed in series. When VRN is less than VD, the differential amplifier will output a low voltage. This means that when the positive value of VNG is too large, the leakage path will be closed to reduce VNG, and make VD equal to VRN.

Since circuit 400 forces VRN=VD, it follows that (R1[k]/(R1[k]+R2[k]))*fVR=(Rb/(Ra+Rb))*(gVR−VNG)+VNG. The voltage VNG is thus equal to (((R1[k]/(R1[k]+R2[k]))*fVR)-(Rb/(Ra+Rb))*gVR)*(Ra+Rb)/Ra. The designer can select the number of stages (thus specifying n) and the VNG value for each stage to specify and find VR, Ra, Rb, R1[0:n] and R2[0:n]. Therefore, the circuit 400 has great design flexibility.

The following is an example of selecting fVR, gVR and R1[k]/(R1[k]+R2[k]), where Ra/(Ra+Rb)=0.25, n=4. The unit of voltage in the table below is "Volt". K VNG wxya VD f R1[k]/(R1[k]+R2[k]) 0 0V 2V 1.5V 2V 0.75 1 -0.5V 2V 1.375V 2V 0.6875 2 -1V 2V 1.25V 2V 0.625 3 -1.5V 2V 1.125V 2V 0.5625 4 -2V 2V 1V 2V 0.5

As mentioned above, the present invention provides a method and structure for erasing and correcting the memory cells in the memory array after erasing the data of the memory cells, including the following steps: (a) selecting determining the first drain bit line, and setting the gate voltage of the memory unit cell coupled thereto to an initial voltage value; (b) applying a voltage to the selected bit line within a preset time limit A series of over-erase correction pulses; (c) within the preset time limit, check whether there is leakage on the bit line; (d) if the preset time limit has passed and the bit line still has leakage, increase the gate voltage and repeat Steps (b) and (c); and (e) if it is detected that the bit line has no leakage within the preset time limit, then select the next bit line, and repeat steps (a) to (d).

Another object of the present invention is to provide a semiconductor device, which includes a memory array, and the array includes a plurality of memory cells connected to each other through a plurality of bit lines, the semiconductor device includes erasing memory cells Afterwards, erase correction circuits are made for these memory cells. In one embodiment, the circuit includes (a) a selected first bit line whose leakage current exceeds a threshold value, and applying a gate voltage to the memory cells to which the first bit line is coupled Circuit set to initial voltage value. For example, the gate voltage setting means may include a regulated voltage source controlled by a flag or other indicator representing the initial gate voltage required for over-erase correction. The circuit may also include (b) a circuit for applying a series of over-erase correction pulses to the selected first bit line within a predetermined time period. The over-erase correction pulse applying device may include a voltage source to output a suitable over-erase correction pulse voltage to the bit line, and a timing circuit for controlling the pulse length. The over-erase correction circuit also includes (c) a circuit for checking whether the leakage current of the first bit line exceeds a critical value within a preset time limit. In this embodiment, the correction circuit also includes (d) a method of increasing the gate voltage when the leakage current of the first bit line exceeds the critical value after a preset time limit, and repeating the steps of (b) and (c). circuit. For example, the voltage boosting device may include a stable voltage source as shown in FIG. 4 , and the voltage source receives a control signal indicating whether the bit line still has leakage after a preset time limit. Finally, the over-erase correction circuit in this embodiment may include (e) a method of selecting the second bit line when it is detected that the leakage current of the first bit line is lower than a critical value within a preset time limit, And repeat the circuit for devices (a) to (d). In one embodiment, the selecting and repeating means may include the above-mentioned means (a) to (d), a validation circuit for checking the over-erase status of the bit line, a device for storing and incrementing the required over-erase state in the memory array. A register of row addresses for erasing the corrected bit lines, and a row address selection circuit for selecting the bit lines.

The above method and circuit can control the current flowing through the bit line during the over-erase correction process, and keep the voltage of the bit line stable, so as to improve the over-erase correction efficiency. In one embodiment, initially using a negative gate voltage during over-erase correction can greatly reduce leakage current. Because the gate voltage is negative, as long as the threshold voltage is higher than the negative gate voltage, even the over-erased memory cell will not conduct current. Once the number of leakage over-erase cells decreases, the current required for convergence also decreases. If the bit line voltage needs to be maintained by a charge pump when the critical voltage is converged to increase the VCC voltage of the integrated circuit, such as in a power saving device, the previous method is particularly beneficial. Furthermore, checking the over-erase status of the memory cell of the selected bit line after each over-erase correction pulse or a certain number of pulses before raising the word line voltage to the next level, It avoids applying unnecessary or excessive pulses, provides a time and energy efficient over-erase correction method, and still increments the word line voltage when necessary.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of an invention shall be defined by the scope of the patent applied for.

Claims (25)

1. A method for over-erase correction, which is applicable after a memory cell in a memory array is erased, the method comprising the following steps: (a) selecting a first bit line whose leakage current exceeds a threshold value, and setting a gate voltage of the memory cell coupled to the first bit line to an initial voltage value; (b) applying a series of over-erase correction pulses to the selected first bit line within a predetermined time limit; (c) within the preset time limit, check whether the first bit line has a leakage current exceeding the critical value; (d) if the preset time limit has elapsed and the first bit line still has a leakage current exceeding the critical value, increasing the gate voltage, and repeating steps (b) and (c); and (e) If it is detected within the preset time limit that the leakage current of the first bit line is below the critical value, then select the next bit line and repeat steps (a) to (d). 2. The method for correcting over-erasure as claimed in claim 1, wherein the preset time limit is between 20 and 100 milliseconds. 3. The method for over-erasing correction as claimed in claim 1, wherein the application time of each over-erasing correction pulse in the series of over-erasing correction pulses is 0.5 to 2.0 milliseconds. 4. The method for over-erasing correction as claimed in claim 1, wherein step (c) comprises the following steps: After each over-erase correction pulse, it is checked whether the first bit line has a leakage current exceeding the threshold. 5. The method for over-erasing correction as claimed in claim 1, further comprising setting an error flag if the gate voltage has reached a maximum gate voltage value. 6. The method for over-erasing correction as claimed in claim 1, wherein the initial voltage value is a negative voltage. 7. The over-erase correction method as claimed in claim 6, wherein the initial voltage is -2.0V, and the step (d) includes increasing the gate voltage in a forward direction by 0.5V each time. 8. A semiconductor device comprising a memory array comprising a plurality of memory cells interconnected by a plurality of bit lines, the semiconductor device comprising after erasing the memory cells, A circuit for erase correction for the memory cells, the circuit comprising: (a) selecting a first bit line whose leakage current exceeds a threshold and setting a gate voltage of the memory cells coupled to the first bit line to an initial Circuits with voltage values; (b) a circuit for applying a series of over-erase correction pulses to the selected first bit line within a predetermined time period; (c) a circuit for checking whether the leakage current of the first bit line exceeds the critical value within the preset time limit; (d) a circuit that increases the gate voltage and repeats means (b) and (c) when the leakage current of the first bit line exceeds the threshold after the predetermined time period; and (e) A circuit that selects a second bit line and repeats means (a) to (d) when it is detected that the leakage current of the first bit line is lower than the critical value within the predetermined time period. 9. The device as claimed in claim 8, wherein the predetermined time period is between 20 and 100 milliseconds. 10. The semiconductor device as claimed in claim 8, wherein the application time of each over-erase correction pulse in the series of over-erase correction pulses is 0.5 to 2.0 milliseconds. 11. The semiconductor device as claimed in claim 8, wherein the circuit (c) comprises a method of checking the first bit line for a leakage current exceeding the critical value and No circuit. 12. The semiconductor device of claim 8, further comprising a circuit for setting an error flag when the gate voltage has reached a maximum gate voltage value. 13. The semiconductor device according to claim 8, wherein the initial voltage value is a negative voltage. 14. The semiconductor device as claimed in claim 13, wherein the initial voltage is -2.0V, and the circuit (d) comprises a circuit for increasing the gate voltage in a positive direction by 0.5V each time. 15. The semiconductor device of claim 13, further comprising a circuit for increasing the gate voltage to a maximum gate voltage value in a positive direction. 16. The semiconductor device according to claim 15, wherein the incrementing means comprises: A comparator, the comparator includes: a first voltage input terminal, coupled to an adjustable resistance circuit, the adjustable resistance circuit is controlled by a word line voltage; and a second voltage input end coupled to a second resistor circuit; the second resistor circuit coupled to a voltage source for providing the word line voltage, Wherein the output signal of the comparator controls the output signal of the voltage source, and the voltage source is affected by a voltage signal at the first voltage input end. 17. The semiconductor device as claimed in claim 16, wherein the output terminal of the comparator is coupled to an output terminal of the voltage source through a leakage path. 18. The semiconductor device according to claim 8, wherein the memory array is a flash memory array. 19. A method for over-erase correction, which is applicable after a memory cell in a memory array is erased, the method comprising the following steps: (a) selecting a first bit line whose leakage current exceeds a threshold value, and setting a gate voltage of the memory cell coupled to the first bit line to an initial voltage value; (b) applying a series of over-erase correction pulses to the selected first bit line within a predetermined time limit; (c) within the predetermined time period, after each over-erase correction pulse in the series of over-erase correction pulses, checking whether the bit line has a leakage current exceeding the threshold value; (d) if the preset time limit has elapsed and the first bit line still has a leakage current exceeding the critical value, increasing the gate voltage, and repeating steps (b) and (c); and (e) If it is detected within the preset time limit that the leakage current of the first bit line is below the critical value, select the next bit line and repeat steps (a) to (d). 20. The method for over-erasing correction as claimed in claim 19, wherein the preset time limit is between 20 and 100 milliseconds, and wherein each over-erasing correction pulse in the series of over-erasing correction pulses The application time of the correction pulse is 0.5 to 2.0 milliseconds. 21. The method for correcting over-erase as claimed in claim 20, wherein the initial voltage is -2.0V, and the step (d) comprises increasing the gate voltage in a forward direction by 0.5V each time. 22. The method for correcting over-erase as claimed in claim 21, further comprising checking whether the gate voltage reaches a maximum gate voltage value. 23. The method for correcting over-erase as claimed in claim 22, wherein the maximum gate voltage is 1.0 volts. 24. A semiconductor device comprising a memory array comprising a plurality of memory cells interconnected by a plurality of bit lines, the semiconductor device comprising after erasing the memory cells, A circuit for erase correction for the memory cells, the circuit comprising: a power supply for supplying an over-erasing correction pulse for a predetermined period of time; an over-erase confirmation circuit for checking a leakage current of a selected bit line exceeding a threshold value within the predetermined time limit; a gate voltage source influenced by a control signal representing one of a plurality of gate voltages applied to the the memory cells of the selected bitline; and A bit line selection circuit, the bit line selection circuit is affected by a control signal indicating whether the selected bit line has a leakage current exceeding the critical value within the preset time limit. 25. A method for over-erase correction, suitable for use after a memory cell in a memory array is erased, the method comprising the following steps: (a) selecting a first bit line containing an over-erase memory cell, and setting a gate voltage of the memory cell coupled thereto to an initial voltage value; (b) applying a series of over-erase correction pulses to the selected first bit line within a preset time limit; (c) within the predetermined time limit, checking whether the first bit line contains the over-erased memory cell; (d) if the predetermined time period has elapsed and the bit line still contains the over-erased memory cell, increasing the gate voltage and repeating steps (b) and (c); and (e) If within the preset time limit, it is checked that the first bit line does not include the memory cell that has been erased, then select the next bit line, and repeat steps (a) to (d).

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