CN1702711A

CN1702711A - Display and driving method thereof

Info

Publication number: CN1702711A
Application number: CNA2005100738488A
Authority: CN
Inventors: 申东蓉
Original assignee: Samsung SDI Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2004-05-25
Filing date: 2005-05-25
Publication date: 2005-11-30
Anticipated expiration: 2025-05-25
Also published as: CN100414578C; KR20050113683A; KR100578843B1

Abstract

In an organic light emitting display, a first pixel and a second pixel share a data line, a selection scan line, and a driving element, and one domain is divided into first and second sub-domains. The organic light emitting element of the first pixel is driven by the first emission control signal transmitted to the first emission scanning line, and the organic light emitting element of the first pixel is driven by the second emission control signal transmitted to the second emission scanning line. The first emission control signal has a low-level pulse in the first subfield, the second emission control signal has a low-level pulse in the second subfield, and the selection signal sent to the selected scan line has a low-level pulse in the first and second subfields. Each of the fields has a low pulse in it. In addition, a scan line driver for driving the selection signal line, the first emission scan line, and the second emission scan line is provided.

Description

Display and driving method thereof

Technical field

The present invention relates to display and driving method thereof.

Background technology

In the viewing area of the Active Matrix Display such as LCD and organic light emitting display, form along the sweep trace of line direction extension and the data line that extends along column direction.Article two, adjacent scanning lines and two adjacent data lines limit a pixel region and form pixel on pixel regions.On pixel, form active component such as transistor and active component response from the selection signal of sweep trace, send data-signal from data line.Therefore, Active Matrix Display need be used for the scanner driver of driven sweep line and the data driver of driving data lines.

In Active Matrix Display, the color combinations Show Color that sends by some pixel.In general, pixel comprises the red pixel of demonstration, shows green pixel and shows blue pixels and passes through red, green and blue combination Show Color.In display, pixel is coupled with the pixel of arranging along line direction respectively by red, green and blue series arrangement and data line along line direction.

Because data driver converts data-signal aanalogvoltage or analog current to and those aanalogvoltages or analog current are imposed on data line, data driver contains many and the corresponding output terminal of data line.In general, data driver manufactures the form of integrated circuit.But, because the quantity of the output terminal that each integrated circuit has is limited, so integrated circuit is used to drive all data lines.In addition, if form data line and driving element on each pixel, (aperture ratio) reduced with the corresponding void ratio in the luminous zone of pixel.

Summary of the invention

In the one exemplary embodiment of the present invention, provide display with integrated circuit that is used for driving data lines that quantity reduced.

In another one exemplary embodiment of the present invention, provide display with data line that quantity reduced.

In another one exemplary embodiment of the present invention, two pixel shared data lines and sweep trace.

In one aspect of the invention, display comprises viewing area and scanner driver.The viewing area comprises many data lines sending the data-signal be used for display image, be used to send many first sweep traces selecting signal, be used for sending respectively many second sweep traces and many articles of three scan lines and a plurality of pixel region of emissioning controling signal.Pixel region comprises first pixel and second pixel with corresponding data line and the coupling of corresponding first sweep trace.First pixel response, second pulsed illumination and second pixel response the 3rd pulsed illumination.Scanner driver sends to first sweep trace by moving first signal with first signal, by mobile secondary signal secondary signal is sent to second sweep trace and by moving the 3rd signal the 3rd signal is sent to three scan line.First signal has first pulse in each of a plurality of subdomains (subfield) that form a territory (field), in first subdomain of a plurality of subdomains secondary signal have second pulse and in second subdomain of a plurality of subdomains the 3rd signal have the 3rd pulse.

In another aspect of the present invention, display device comprises many first sweep traces sending a plurality of first signals, sends many second sweep traces of a plurality of secondary signals and sends many articles of three scan lines of a plurality of the 3rd signals.Display further comprises first driver, second driver and the 3rd driver.First driver is by moving first signal first period (period) output, first signal, and second driver is exported the 3rd signal by secondary signal being moved first period output secondary signal and the 3rd driver by the 3rd signal was moved for first period.First signal has first pulse in second period in each of a plurality of subdomains that form a territory, in first subdomain of a plurality of subdomains in than second o'clock segment length's the 3rd period secondary signal have second pulse and in second subdomain of a plurality of subdomains in than second o'clock segment length's the 4th period the 3rd signal have the 3rd pulse.

In another aspect of the present invention, display comprises many first sweep traces sending a plurality of first signals, sends many second sweep traces of a plurality of secondary signals and sends many articles of three scan lines of a plurality of the 3rd signals.Display further comprises first driver and second driver.First driver is exported first signal by first signal was moved for first period.Second driver generates secondary signal and the 3rd signal from the 4th signal.In addition, second driver is by moving secondary signal first period output secondary signal and exporting the 3rd signal by the 3rd signal was moved for first period.First signal has first pulse in second period in each of a plurality of subdomains that form a territory.According to the 4th signal, in first subdomain of a plurality of subdomains in than second o'clock segment length's the 3rd period secondary signal have second pulse and in second subdomain of a plurality of subdomains in than second o'clock segment length's the 4th period the 3rd signal have the 3rd pulse.

In another aspect of the present invention, scanner driver is exported first signal by first signal was moved for first period, by secondary signal being moved first period output secondary signal and exporting the 3rd signal by the 3rd signal was moved for first period.Scanner driver comprises first driver and second driver.First driver by the 4th signal was moved first period and exports the 4th signal and in a territory the 4th signal have first pulse and with second pulse of first pulse inversion.Second driver is created on the 3rd signal that has first signal of the 3rd pulse in second period, have the secondary signal of the 4th pulse and have the 5th pulse in first subdomain of a plurality of subdomains in the 3rd period than second o'clock segment length in second subdomain of a plurality of subdomains in the 4th period than second o'clock segment length in each of a plurality of subdomains of forming a territory from the 4th signal.

In another aspect of the present invention, display comprises first sweep trace, second sweep trace, three scan line, sends the data line of the data-signal that is used for display image and the pixel region that is limited by first, second and three scan line and data line.The driving method of display comprises: output has the selection signal of first pulse in first period in each of a plurality of subdomains that form a territory, output has first emissioning controling signal of second pulse and output has the 3rd pulse in the 3rd period than first o'clock segment length in second subdomain of a plurality of subdomains second emissioning controling signal in second period than first o'clock segment length in first subdomain of a plurality of subdomains.Response and the corresponding pulse of first pulse that sends to first sweep trace are programmed into pixel region with data-signal.First pixel response of pixel region and the corresponding pulse of second pulse that sends to second sweep trace, begin to send and the corresponding light of (programmed) data-signal of programming, second pixel response and the corresponding pulse of the 3rd pulse that sends to three scan line with pixel region begin to send and the corresponding light of programming data signal.

Description of drawings

Fig. 1 shows the planimetric map of the organic light emitting display of first one exemplary embodiment according to the present invention;

Fig. 2 shows the synoptic diagram of the pixel region of the organic light emitting display of first one exemplary embodiment according to the present invention;

Fig. 3 shows the signal timing diagram of the organic light emitting display of first one exemplary embodiment according to the present invention;

Fig. 4 A shows the selection scanner driver in the organic light emitting display of first one exemplary embodiment according to the present invention;

Fig. 4 B shows the trigger in the selection scanner driver that is used in Fig. 4 A;

Fig. 5 shows the signal timing diagram in the selection scanner driver of Fig. 4 A;

Fig. 6,9 and 11 shows according to the present invention the emission scan driver in the organic light emitting display of second, third and the 4th one exemplary embodiment respectively;

Fig. 7 shows the synoptic diagram of the pixel region of the organic light emitting display of second one exemplary embodiment according to the present invention;

Fig. 8 shows the signal timing diagram of the organic light emitting display of second one exemplary embodiment according to the present invention;

Figure 10 and 12 shows the signal timing diagram in the emission scan driver of Fig. 9 and 11 respectively;

Figure 13 and 14 shows the planimetric map of the organic light emitting display of the 4th and the 5th one exemplary embodiment according to the present invention respectively;

Figure 15,16 and 18 shows the emission scan driver in the organic light emitting display of the 5th, the 6th and the 7th one exemplary embodiment according to the present invention respectively;

Figure 17 shows the signal timing diagram in the emission scan driver of Figure 16;

Figure 19 and 20 shows the signal timing diagram in the emission scan driver of Figure 18 respectively;

Figure 21 and 22 shows the planimetric map of the organic light emitting display of the 8th and the 9th one exemplary embodiment according to the present invention respectively;

Figure 23,25,26 and 28 shows according to the present invention the 9th, the tenth respectively, the 11 and the organic light emitting display of the 12 one exemplary embodiment in scanner driver;

Figure 24 and 27 shows the signal timing diagram in the scanner driver of Figure 23 and 26 respectively;

Figure 29 shows the signal timing diagram in the scanner driver of the 13 one exemplary embodiment according to the present invention respectively;

Figure 30 and 32 show respectively according to the present invention the 14 and the organic light emitting display of the 15 one exemplary embodiment in scanner driver;

Figure 31 shows the signal timing diagram in the scanner driver of Figure 30;

Figure 33 shows the planimetric map of the organic light emitting display of the 16 one exemplary embodiment according to the present invention; With

Figure 34 shows the signal timing diagram in the selection scanner driver of the 17 one exemplary embodiment according to the present invention.

Describe in detail

Referring now to Fig. 1, organic light emitting display comprises that the substrate (not shown) and the substrate that form display panel are divided into viewing area 100 and viewing area 100 external zones on every side of being regarded as screen by the user.External zones comprises selects scanner driver 200, emission scan driver 300,400 and data driver 500.

Viewing area 100 comprises many data line D ₁-D _n, many select sweep trace S ₁-S _m, many transmit scan line E ₁₁-E _1mAnd E ₂₁-E _2mWith a plurality of pixels.Data line D ₁-D _nExtend and the data-signal of representative image is sent to respective pixel along column direction.Select sweep trace S ₁-S _mWith transmit scan line E ₁₁-E _1mAnd E ₂₁-E _2mExtend and will select signal and emissioning controling signal to send to respective pixel respectively along line direction.Pixel region 110 is by two adjacent scanning lines S ₁-S _mWith two adjacent data line D ₁-D _nLimit and on pixel region 110, form two pixels 111,112.That is to say two pixels, 111, the 112 common and data line D of pixel region 110 ₁-D _nOne of with select sweep trace S ₁-S _mOne of the coupling.

Select scanner driver 200 will be used to select the selection signal of homologous lines to send to selection sweep trace S successively ₁-S _m, so that data-signal is imposed on the pixel of homologous lines.Emission scan driver 300 will be used to control pixel 111 luminous emissioning controling signals successively and send to transmit scan line E in a subdomain ₁₁-E _1mAnd emission scan driver 400 will be used to control pixel 112 luminous emissioning controling signals successively and send to transmit scan line E in another subdomain ₂₁-E _2mWhen applying the selection signal successively, data driver 500 just will impose on data line D with the corresponding data-signal of pixel of the line that it has been applied the selection signal ₁-D _m

Select and emission scan driver 200,300,400 and data driver 500 and substrate coupling.In addition, select and emission scan driver 200,300 and/or 400 and/or data driver 500 can be directly installed in the substrate, with can be used in the substrate with form sweep trace, layer that data line is identical with transistorized layer go up the driving circuit replacement that forms they.And, select and emission scan driver 200,300 and/or 400 and/or data driver 500 tape carrier that can be installed in the form of chip with the substrate coupling encapsulate (tape carrier package:TCP), flexible printed circuit board (FPC) or be with automatic combining unit (TAB).

Fig. 2 shows the synoptic diagram of pixel region of the organic light emitting display of Fig. 1.Sweep trace S with i capable (wherein, ' i ' is the positive integer less than ' m ') has demonstrated in Fig. 2 _iThree pixel regions 110 with j to the (j+2) row (wherein, ' j ' is the positive integer less than ' n ') coupling _Ij, 110 _{I (j+1)}, 110 _{I (j+2)}Suppose pixel along the line direction of Fig. 2 by red, green and blue series arrangement.

With reference to Fig. 2, two pixels 111,112 have data line D jointly ₁-D _nOne of and pixel driver and pixel driver comprise driving transistors M1, switching transistor M2 and capacitor Cst.Select sweep trace S by i _iWith j data line D _jThe pixel region 110 that limits _IjTwo

pixels

111 _Ij, 112 _IjComprise pixel driver, two ballistic transistor M31, M32 and two organic illuminating element OLED1, OLED2.Organic illuminating element OLED1, OLED2 send ruddiness and green glow respectively.Organic illuminating element sends brightness and the corresponding light of electric current that applies.Select sweep trace S by i _iWith (j+1) data line D _J+1The pixel region 110 that limits _{I (j+1)}Two

pixels

111 _{I (j+1)}, 112 _{I (j+1)}With select sweep trace S by i _iWith (j+2) data line D _J+2The pixel region 110 that limits _{I (j+2)}Two

pixels

111 _{I (j+2)}, 112 _{I (j+2)}Have and

pixel

111 _Ij, 112 _IjIdentical structure.Two

pixels

111 _{I (j+1)}, 112 _{I (j+1)}Organic illuminating element OLED1, OLED2 sends blue light and ruddiness and two pixels 111 respectively _{I (j+2)}, 112 _{I (j+2)}Organic illuminating element OLED1, OLED2 sends green glow and blue light respectively.

In more detail, driving transistors M1 has with the source electrode of the power lead VDD coupling that supply voltage is provided and has grid with the drain coupled of switching transistor M2, and capacitor Cst is coupling between the source electrode and grid of driving transistors M1.Have and selection sweep trace S _iThe coupling grid and with data line D _jThe switching transistor M2 response of the source electrode of coupling is by selecting sweep trace S _iThe selection signal that provides sends data line D _jThe data-signal that converts aanalogvoltage (hereinafter referred to as " data voltage ") to that provides.Driving transistors M1 has and ballistic transistor M31, the drain electrode of the source-coupled of M32 and ballistic transistor M31, the grid of M32 respectively with emissioning controling signal line E _1i, E _1iCoupling.Ballistic transistor M31, the drain electrode of M32 respectively with organic illuminating element OLED1, coupling of the anode of OLED2 and supply voltage VSS are applied to organic illuminating element OLED1, on the negative electrode of OLED2.Supply voltage VSS in first one exemplary embodiment can be negative voltage or ground voltage.

Switching transistor M2 response is by selecting sweep trace S _iThe low level that provides is selected signal, makes data line D _jThe data voltage that provides be sent to driving transistors M1 grid and with the corresponding store voltages of difference of the data voltage of the grid that sends to transistor M1 and supply voltage VDD in capacitor Cst.As response emissioning controling signal line E _1iThe low level emissioning controling signal conducting ballistic transistor M that provides ₃₁The time, make as following equation 1 is expressed with the corresponding electric current I of voltage that is stored among the capacitor Cst _OLEDBe sent to organic illuminating element OLED1 from driving transistors M1, so that make it luminous.Equally, as response emissioning controling signal line E _2iDuring the low level emissioning controling signal conducting ballistic transistor M32 that provides, the corresponding electric current of voltage that makes and be stored among the capacitor Cst is sent to organic illuminating element OLED2 from driving transistors M1, so that make it luminous.Impose on emissioning controling signal line E respectively _1i, E _2ITwo emissioning controling signals have the unduplicated low level period in a territory so that a pixel region can show two kinds of colors.

Equation 1

I_{OLED} = \frac{β}{2} {(| V_{SG} | - | V_{TH} |)}^{2}

Wherein, β is the constant by the channel width of transistor M1 and channel length decision, V _SGBe the source electrode of transistor M1 and the voltage between the grid, and V _THThe starting voltage of transistor M1.

The driving method of the organic light emitting display of first one exemplary embodiment according to the present invention is described in more detail below with reference to Fig. 3.In Fig. 3, impose on and select sweep trace S _iThe selection signal be expressed as ' select[i] ' and impose on transmit scan line E _1i, E _2iEmissioning controling signal be expressed as ' emit1[i] ', ' emit2[i] '.Because data voltage imposes on data line D simultaneously ₁-D _nSo, in Fig. 3, described to impose on data line D _jData voltage data[j].

With reference to Fig. 3, a territory comprises two

subdomain

1F, and 2F and low level are selected signal to impose on successively in each

subdomain

1F or 2F and selected sweep trace S ₁-S _mShare the organic illuminating element OLED1 of two pixels of pixel driver, OLED2 respectively with subdomain SF1, luminous in the corresponding period of SF2.

In subdomain 1F, when low level is selected signal select[1] impose on the selection sweep trace S on first row ₁The time, go up the corresponding data voltage data[j of organic illuminating element OLED1 of each pixel region with first row] impose on corresponding data line D _jAnd low level emissioning controling signal emit1[i] impose on first the row on emissioning controling signal line E _1iThe ballistic transistor M31 conducting of the pixel region on first row and with data voltage data[j] corresponding electric current is sent to organic illuminating element OLED1 from driving transistors M1, thereby causes luminous.Only at emissioning controling signal emit1[i] be in and send in the period on the low level, emissioning controling signal emit1[i] the low level period with corresponding to the period of subdomain 1F identical.

Equally, data voltage imposes on first to the m capable pixel region successively, so that make organic illuminating element OLED1 luminous.When low level is selected signal select[i] impose on the selection sweep trace S of i on capable _iThe time, with i capable on the corresponding data voltage data[j of organic illuminating element OLED1 of each pixel region] impose on corresponding data line D _jAnd low level emissioning controling signal emit1[i] impose on the emissioning controling signal line E of i on capable _1iBy data line D _jEach bar provide with data voltage data[j] corresponding electric current offer thus i capable on the organic illuminating element OLED1 in respective pixel district, thereby luminous in the corresponding period with subdomain 1F.Therefore, in subdomain 1F, the pixel that forms organic illuminating element OLED1 in two pixels adjacent along line direction is luminous.

In

subdomain

2F, 1F is the same with subdomain, and low level is selected signal select[1] to select[m] impose on first to the m capable selection sweep trace S successively ₁-S _mWith when selecting signal select[i] impose on corresponding selection sweep trace S _iThe time, with the corresponding data voltage data[j of organic illuminating element OLED1 of each pixel region of corresponding line] impose on corresponding data line D respectively _jLow level emissioning controling signal emit2[i] select signal select[i with low level] impose on successively and select sweep trace S ₁-S _mSynchronously impose on emissioning controling signal line E successively ₂₁-E _2mBe sent to organic illuminating element OLED2 with applying the corresponding electric current of data voltage by the ballistic transistor M32 in each pixel region, so that make it luminous.Emissioning controling signal emit2[i] the low level period with corresponding to the period of subdomain 2F identical.Therefore, in subdomain 2F, the pixel that forms organic illuminating element OLED2 in two pixels adjacent along line direction is luminous.

As mentioned above, territory is divided into two subdomains and drives this two subdomains successively in the method according to the organic light emitting display of first one exemplary embodiment.An organic illuminating element of two of a pixel region pixels is luminous and two organic illuminating elements are luminous successively by two subdomains in each subdomain, thus representative color.In addition, because two pixel shared data line D _jAnd pixel driver, can reduce the bar number of data line and the number of pixel driver.As a result, can reduce the integrated circuit that is used for driving data lines number and can be easily with element arrangements in pixel region.

Then, with reference to Fig. 4 A to 6 selection scanner driver 200 and the emission scan driver 300,400 that is used to generate waveform as shown in Figure 3 described.

Fig. 4 A shows according to the selection scanner driver 200 in the organic light emitting display of first one exemplary embodiment.Fig. 4 B shows the trigger in the selection scanner driver 200 that is used in Fig. 4 A.Fig. 5 shows the signal timing diagram in the selection scanner driver 200 of Fig. 4 A.The inversion signal of time clock VCLK is expressed as VCLKb in Fig. 4 A, not shown VCLKb in Fig. 5.The low level period in a time clock VCLK cycle is identical with the high level period in a time clock VCLK cycle.

Because the structure of scanner driver 200,300,400 is supposed scanner driver 200,300 by the pulse width and the impulse level decision of output signal, the condition of 400 output signal is as follows.Select signal select[i] the low level pulse width identical with half time clock VCLK cycle so that make the frequency minimum of time clock VCLK; Select sweep trace S ₁-S _mBar to count m be even number and emissioning controling signal emit1[i] or emit2[i] the low level pulse width corresponding to the integral multiple of ' m '; Be used in scanner driver 200,300, the trigger in 400 is exported the signal of importing in half time clock VCLK cycle in a time clock VCLK cycle.Under these conditions, because the output pulse of trigger is the integral multiple in a time clock VCLK cycle, the output signal of trigger cannot be with the signal that elects.

Therefore, shown in Fig. 4 A, select scanner driver 200 to comprise (m+1) individual trigger FF ₁₁-FF _{1 (m+1)}With m NAND door NAND ₁₁-NAND _1mAnd play shift register.NAND door NAND _1iOutput signal be to select signal select[i] (wherein, ' i ' is the positive integer less than ' m ').In Fig. 4 A, commencing signal VSP1 imports the first trigger FF ₁₁In and i trigger FF _1iOutput signal SR _1iInput (i+1) trigger FF _{1 (i+1)}In.I NAND door NAND _1iTo two adjacent trigger FF _1i, FF _{1 (i+1)}Output signal SR _1i, SR _{1 (i+1)}Carry out NAND computing and output selection signal select[i].Be used in trigger FF _1iIn time clock VCLK or anti-phase time clock VCLKb or the VCLK of VCLKb be used in and trigger FF _1iAdjacent flip-flops FF _{1 (i+1)}In.

In more detail, be positioned at trigger FF on the odd positions along the longitudinal _1iWith time clock VCLK, VCLKb is as internal clock pulse clk, clkb respectively.Be positioned at the locational trigger FF of even number along the longitudinal _1iWith time clock VCLKb, VCLK is as internal clock pulse clk, clkb respectively.In addition, trigger FF _1iResponse high level time clock clk exports an input signal and responds the input signal that low level time clock clk latched and exported high level time clock clk.As a result, trigger FF _{1 (i+1)}Output signal SR _{1 (i+1)}With respect to trigger FF _1iOutput signal SR _1iMoved the time clock VCLK cycle half.

As shown in Figure 5, because at corresponding subdomain 1F, commencing signal VSP1 has high level pulse at the high level in a time clock VCLK cycle in the period among the 2F, so at corresponding subdomain 1F, trigger FF among the 2F ₁₁In a time clock VCLK cycle, export high level pulse.As a result, by high level pulse being moved half time clock VCLK cycle, trigger FF ₁₁-FF _1mCan export each output signal SR successively _1i

NAND door NAND _1iCarry out trigger FF _1i, FF _{1 (i+1)}Output signal SR _1i, SR _{1+ (i+1)}The NAND computing and as two output signal SR _1i, SR _{1 (i+1)}When all being high level, the output low level pulse.Here, because trigger FF _{1 (i+1)}Output signal SR _{1 (i+1)}With respect to trigger FF _1iOutput signal SR _1iMoved the time clock VCLK cycle half, at corresponding subdomain 1F, NAND door NAND among the 2F _1iOutput signal a period, that is, and output signal SR _1i, SR _{1 (i+1)}Both have jointly in half clock cycle of high level pulse and have low level pulse.In addition, NAND door NAND _{1 (I+1)}Output signal select[i+1] with respect to NAND door NAND _1iOutput signal select[i] moved half the time clock VCLK cycle.Therefore, by low level pulse being moved half the time clock VCLK cycle, select scanner driver 200 can export each successively and select signal select[i].

With reference to Fig. 4 B, trigger FF _1iThe phase inverter 212 and the timing phase inverter 213 that comprise timing (clocked) phase inverter 211 and formation latch.When time clock clk was in high level, timing phase inverter 211 made the anti-phase and phase inverter 212 of input signal (in) make the output signal of timing phase inverter 211 anti-phase.When time clock clk was in low level, the output signal that the output of timing phase inverter 211 is blocked and the output signal of phase inverter 212 is input to timing phase inverter 213 and timing phase inverter 213 was input to phase inverter 212.As a result, formation is latched.At this moment, the output signal of phase inverter 212 (out) is trigger FF _1iOutput signal and the input signal (inv) of phase inverter 212 are inversion signals of output signal (out).Therefore, trigger FF _1iWhen time clock clk is in high level, can export this input signal (in) and when time clock clk is in low level, latch and export this input signal (in) in the period at the high level of time clock (clk).

The emission scan driver 300,400 of the waveform that generates Fig. 3 then, is described with reference to Fig. 6.Fig. 6 shows according to the

emission scan driver

300 or 400 in the organic light emitting display of first one exemplary embodiment.

With reference to Fig. 6, emission scan driver 300 comprises m trigger FF ₂₁-FF _2mAnd play shift register.Emission scan driver 300 uses and the identical time clock of time clock VCLK of selecting scanner driver 200.Commencing signal VSP2 imports the first trigger FF ₂₁In and i trigger FF _2iOutput signal be i emissioning controling signal line E _1iEmissioning controling signal emit[i] and import (i+1) trigger FF _{2 (i+1)}In.

Be used in trigger FF _2iIn time clock VCLK or anti-phase time clock VCLKb or the VCLK of VCLKb be used in and trigger FF _2iAdjacent flip-flops FF _{2 (i+1)}In.In addition, the first trigger FF ₂₁Emissioning controling signal emit[1] in the negative edge and the first trigger FF of low level pulse ₁₁Output signal SR ₁₁The rising edge of middle high level pulse is removed.Therefore, different with Fig. 4 A, be positioned at the trigger FF on the odd positions along the longitudinal _2iRespectively with time clock VCLb, VCLK is as internal clock pulse clk, clkb and be positioned at the locational trigger FF of even number along the longitudinal _2iWith time clock VCLK, VCLKb is as internal clock pulse clk, clkb respectively.Here, trigger FF _2iWith the trigger FF that in Fig. 4 A and 4B, describes _1iHas identical structure.

Because the low level in all the time clock VCLK cycles of commencing signal VSP2 in subdomain 1F has low level pulse in the period, trigger FF ₂₁Output signal e mit1[1] in subdomain 1F, have low level pulse.In addition, because the low level in all the time clock VCLK cycles of commencing signal VSP2 in subdomain 2F has high level pulse in the period, trigger FF ₂₁Output signal e mit1[1] in subdomain 2F, have high level pulse.

Therefore, by moving half time clock VCLK cycle, emission scan driver 300 can be exported successively has each emissioning controling signal emit1[1 of low level pulse with subdomain 1F in the corresponding period].Here, if the low level period than and corresponding period of subdomain 1F short, the low level period becomes and is shorter than the corresponding period with subdomain 1F.

Because emissioning controling signal emit2[i as the output signal of emission scan driver 400] be inverted into the emissioning controling signal emit1[i of emission scan driver 300], emission scan driver 400 can have the structure identical with emission scan driver 300.Here, if subdomain 1F has the period identical with subdomain 2F, moved the commencing signal that can be used as emission scan driver 300 with the signal of corresponding period of subdomain 1F with respect to commencing signal VSP2.Then, by moving half time clock VCLK cycle as shown in Figure 3, the emission scan driver can be exported each emissioning controling signal emit2[i successively].

According to aforesaid selection scanner driver 200 and

emission scan driver

300 and 400, corresponding subdomain 1F selects signal select[i among the 2F] negative edge corresponding to sending to emissioning controling signal line E _1i, E _2iCorresponding emissioning controling signal emit1[i], emit2[i] rising edge.Select signal select[i] and emissioning controling signal emit1[i], emit2[i] can be used for the organic light emitting display of working voltage programmed method.But, in using the organic light emitting display of current programmed method, when the corresponding data signal is programmed into pixel, need blocking-up from the electric current of driving transistors M1 from organic illuminating element OLED1, OLED2 flows out.These one exemplary embodiment are described to Figure 12 with reference to Fig. 7.

Fig. 7 shows the synoptic diagram of the pixel region of the organic light emitting display of second one exemplary embodiment according to the present invention.Use the data-signal that wherein converts analog current (hereinafter referred to as " data current ") to impose on data line D according to the organic light emitting display of second one exemplary embodiment ₁-D _nCurrent programmed method.

As shown in Figure 7, except pixel driver, according to the pixel region 110 of second one exemplary embodiment ' _Ij, 110 ' _{I (j+1)}, 110 ' _{I (j+2)}Have and the structure identical according to the pixel region of first one exemplary embodiment.In more detail, pixel driver comprises driving transistors M1 ', switching transistor M2 ', the continuous transistor M4 of diode and capacitor Cst '.Transistor M1 ', M2 ', M31 ', M32 ', capacitor Cst ', selection sweep trace Si, transmit scan line E _1i, E _2iWith data line D _jSyndeton with to describe those in Fig. 2 identical.In addition, transistor M4 is coupling in drain electrode and the data line D of transistor M1 ' _jBetween and the grid of transistor M4 with select sweep trace S _iCoupling.

Sweep trace S is selected in response _iThe low level that provides is selected signal, transistor M2 ', M4 conducting and data line D _jThe data current that provides flows to the drain electrode of transistor M1 '.Then, to capacitor Cst ' charging, the electric current that the voltage in being stored in capacitor Cst ' makes the drain electrode that flows to transistor M1 ' corresponding to data current till.That is to say, stored and the corresponding voltage of data current in that capacitor Cst ' is middle.

As response emissioning controling signal line E _1iThe low level emissioning controling signal emit1[i that provides] ' conducting ballistic transistor M31 ' time, make and be stored in the corresponding electric current I of voltage among the capacitor Cst ' _OLEDBe sent to organic illuminating element OLED1 ' from driving transistors M1 ', so that make it luminous.Equally, as response emissioning controling signal line E _2iThe low level emissioning controling signal emit2[i that provides] ' conducting ballistic transistor M32 ' time, make and be stored in the corresponding electric current of voltage among the capacitor Cst ' from driving transistors M1, be sent to organic illuminating element OLED2 ', so that make it luminous.

The driving method of the organic light emitting display of second one exemplary embodiment according to the present invention then, is described in more detail with reference to Fig. 8.

With reference to Fig. 8, a territory is divided into two

subdomain

1F, and 2F is except emissioning controling signal emit1[i] ', emit2[i] ' sequential outside, according to the driving method of second one exemplary embodiment with identical according to the driving method of first one exemplary embodiment.

In subdomain 1F, sending to i selection sweep trace S _iSelection signal select[i] be raised to after the high level, send to i emissioning controling signal line E _1iEmissioning controling signal emit1[i] ' have a low level pulse.In addition, with subdomain 1F and select signal select[i] the difference of low level pulse width in the corresponding period, emissioning controling signal emit1[i] ' also have a low level pulse.

Then, as low level selection signal select[i] impose on and select sweep trace S _iThe time, the corresponding data current data[j of the organic illuminating element OLED1 of each pixel region on i is capable] ' impose on corresponding data line D _jAt this moment, because high level emissioning controling signal emit1[i] ', emit2[i] ' impose on the emissioning controling signal line E of i on capable _1i, E _2i, organic illuminating element OLED1 ', OLED2 ' disconnects with driving transistors M1 ' electricity.Therefore, storing and data current data[j in that capacitor Cst ' is middle] ' corresponding voltage.Then, low level emissioning controling signal emit1[i] ' impose on first the row on emissioning controling signal line E _1iBallistic transistor M31 ' the conducting of the pixel region on i is capable and be sent to organic illuminating element OLED1 ' with the corresponding electric current of voltage that is stored among the capacitor Cst ', thus make it luminous.

Equally, low level is selected signal select[1]-select[m] impose on first to the m capable selection sweep trace S successively ₁-S _mAs the selection signal select[i that selects sweep trace Si] when being raised to high level, low level emissioning controling signal emit1[i] ' impose on the transmit scan line E of i on capable _1i

In

subdomain

2F, 1F is the same with subdomain, is sending to i selection sweep trace S _iSelection signal select[i] be raised to after the high level, send to i emissioning controling signal line E _2iEmissioning controling signal emit2[i] ' have a low level pulse.In addition, with subdomain 2F and select signal select[i] the difference of low level pulse width in the corresponding period, emissioning controling signal emit2[i] ' also have a low level pulse.

Then, with reference to Fig. 9 to 12 the emission scan driver 300a that generates waveform as shown in Figure 8,400a are described.

Fig. 9 shows the signal timing diagram that shows emission scan driver 300a as shown in Figure 9 according to the emission scan driver 300a in the organic light emitting display of second one exemplary embodiment and Figure 10.Shown in Fig. 3 and 8, because according to the selection signal select[i in the organic light emitting display of second one exemplary embodiment] sequential with according to the selection signal select[i in the organic light emitting display of first one exemplary embodiment] sequential identical, the selection scanner driver 200 shown in Fig. 4 A and 4B can be used as the selection scanner driver according to second one exemplary embodiment.

In second one exemplary embodiment, because as selection signal select[i] when being in low level, emissioning controling signal emit1[i] ' be in high level, emissioning controling signal emit1[i] ' the low level pulse width become the odd-multiple of half clock cycle.But because the output signal of emission scan driver 300 as shown in Figure 6 is integral multiples of a clock cycle, emission scan driver 300 as shown in Figure 6 cannot be applied to signal timing diagram as shown in Figure 8.

Therefore, as shown in Figure 9, comprise (m+1) individual trigger FF according to the emission scan driver 300a of second one exemplary embodiment ₃₁-FF _{3 (m+1)}With m NAND door NAND ₃₁-NAND _3mAnd play shift register.Beginning pulse VSP2a shown in Fig. 8 and 10 imports the first trigger FF ₃₁In and i trigger FF _3iOutput signal SR _3iInput (i+1) trigger FF _{3 (i+1)}In (wherein, ' i ' is the positive integer less than ' m ').NAND door NAND _3iAt two trigger FF _3i, FF _{3 (i+1)}Output signal SR _3i, SR _{3 (i+1)}Between carry out NAND computing and output emissioning controling signal emit1[i] '.

Here, except time clock VCLK, outside the VCLKb, emission scan driver 300a has and the identical structure of emission scan driver shown in Fig. 4 A.That is to say, be positioned at the trigger FF on the odd positions along the longitudinal _3iRespectively with time clock VCLKb, VCLK is as internal clock pulse clk, clkb and be positioned at the locational trigger FF of even number _3iWith time clock VCLK, VCLKb is as internal clock pulse clk, clkb respectively.Then, emissioning controling signal emit[i] ' in the negative edge of low level pulse with respect to selecting signal select[i] in the negative edge of low level pulse can move the time clock VCLK cycle half.

The first trigger FF ₃₁When time clock VCLK is in low level, receive commencing signal VSP2a and in a time clock VCLK cycle, export received signal.With reference to Figure 10, the low level in all the time clock VCLK cycles of commencing signal VSP2a in subdomain 1F has high level pulse in the period and the low level in all the time clock VCLK cycles in subdomain 2F has low level pulse in the period.Therefore, by moving half time clock VCLK cycle, trigger FF _3I-FF _{3 (i+1)}Can export successively and have the output signal of high level pulse in the corresponding period respectively with subdomain 1F.

NAND door NAND _3iAt trigger FF _3i, FF _{3 (i+1)}Output signal SR _3i, SR _{3 (i+1)}Between carry out the NAND computing and as two output signal SR _3i, SR _{3 (i+1)}When all being high level, the output low level pulse.Therefore, NAND door NAND _3iOutput signal, that is, emissioning controling signal emit1[i] ' have low level pulse with the subdomain 1F and the difference in half time clock VCLK cycle in the corresponding period.Emissioning controling signal emit1[i] ' negative edge corresponding to selecting signal select[i] rising edge.In addition, shown in Fig. 4 A and 5, as NAND door NAND _{3 (I+1)}The emissioning controling signal emit1[i+1 of output signal] ' with respect to as NAND door NAND _3iThe emissioning controling signal emit1[i of output signal] ' moved half the time clock VCLK cycle.

Because the emissioning controling signal emit2[i among the subdomain 2F] ' have with respect to emissioning controling signal emit1[i] ' waveform that moved, emission scan driver 300a can be used as emission scan driver 400a.Here, if corresponding to period of subdomain 1F with corresponding to the period of subdomain 2F identical, the signal that has moved subdomain 1F with respect to commencing signal VSP2a can be as the commencing signal VSP3a of emission scan driver 400a.

As mentioned above,

emission scan driver

300a, 400a have and the identical structure of selection scanner driver 200 shown in Fig. 4 A and 4B, and still, further embodiment may have the structure different with selection scanner driver 200.Below with reference to Figure 11 and 12 these further embodiment are described in more detail.

Figure 11 shows the signal timing diagram that shows emission scan driver 300b as shown in figure 11 according to the emission scan driver 300b in the organic light emitting display of the 3rd one exemplary embodiment and Figure 12.

As shown in figure 11, the emission scan driver 300b according to the 3rd one exemplary embodiment comprises (m+1) individual trigger FF ₄₁-FF _{4 (m+1)}With m NOR door NOR ₄₁-NOR _4mAnd play shift register.NOR door NOR _4iOutput signal be to send to transmit scan line E _1iEmissioning controling signal emit[i] '.Beginning pulse VSP2b as shown in figure 12 imports the first trigger FF ₄₁In and i trigger FF _4iOutput signal SR _4iInput (i+1) trigger FF _{4 (i+1)}In (wherein, ' i ' is the positive integer less than ' m ').NOR door NOR _4iAt two trigger FF _4i, FF _{4 (i+1)}Output signal SR _4i, SR _{4 (i+1)}Between carry out NOR computing and output emissioning controling signal emit1[i] '.

In the 3rd embodiment, emissioning controling signal emit1[i] ' generate by the NOR computing.For the NOR computing, trigger FF _4iOutput signal SR _4iWith respect to trigger FF _3iOutput signal SR _3iMoved the time clock VCLK cycle half.Therefore, trigger FF _4iUse and trigger FF as shown in Figure 9 _3iTime clock VCLKb or anti-phase time clock VCLK or the VCLKb and the first trigger FF of VCLK _4iWhen time clock VCLK is in high level, receive commencing signal VSP2b and in a time clock VCLK cycle, export received signal.As shown in figure 12, since commencing signal VSP2b with subdomain 1F and the difference in a time clock VCLK cycle in the corresponding period high level in all time clock VCLK cycles have high level pulse in the period, trigger FF ₄₁Output signal SR ₄₁In this period, has high level pulse.In addition, because commencing signal VSP2b is on the low level output signal SR in subdomain 2F ₄₁In subdomain 2F, be on the low level.Therefore, by high level pulse being moved half time clock VCLK cycle, trigger FF _4I-FF _{4 (m+1)}Output signal output SR successively ₄₁-SR _{4 (m+1)}, corresponding output signal SR ₄₁-SR _{4 (m+1)}Has high level pulse with the subdomain 1F and the difference in a time clock VCLK cycle in the corresponding period.

NOR door NOR _4iAt trigger FF _4i, FF _{4 (i+1)}Output signal SR _4i, SR _{4 (i+1)}At least one output low level pulse when being in high level.Therefore, output signal e mit1[i] ' have low level pulse with the subdomain and the difference in half time clock VCLK cycle in the corresponding period, the negative edge of low level pulse is corresponding to selecting signal select[i] rising edge.In addition, because output signal SR _{4 (i+1)}With respect to output signal SR _4iMoved the time clock VCLK cycle half, output signal e mit1[i+1] ' with respect to emissioning controling signal emit1[i] ' moved half the time clock VCLK cycle.

Because the emissioning controling signal emit2[i among the subdomain 2F] ' have with respect to emissioning controling signal emit1[i] ' waveform that moved, emission scan driver 300b can be used as emission scan driver 400b.Here, if corresponding to period of subdomain 1F with corresponding to the period of subdomain 2F identical, the signal that has moved subdomain 1F with respect to commencing signal VSP2b can be as the commencing signal of emission scan driver 400b.

As mentioned above, the emission scan driver that is used in the display of organic electroluminescence that uses current programmed method can be as the emission scan driver in the display of organic electroluminescence of working voltage programmed method.That is to say, can be used for organic illuminating element in the low level of selecting signal non-luminous organic light emitting display in the period according to the emission scan driver of the second and the 3rd one exemplary embodiment.

In addition, can be used for as shown in figure 13 organic light emitting display according to the selection of first to the 3rd one exemplary embodiment and emission scan driver.Figure 13 shows the planimetric map of the organic light emitting display of the 4th one exemplary embodiment according to the present invention.

With reference to Figure 13, the transmit scan line E on i is capable _1i, E _2iAnd pixel region 110 ' between connection be different from transmit scan line E on (i+1) row _{1 (i+1)}, E _{2 (i+1)}And pixel region 110 ' between connection.In more detail, if transmit scan line E _1iWith pixel region 110 on the i capable (wherein, ' i ' is the odd-integral number less than ' m ') ' left pixel 111 ' coupling and transmit scan line E _2iPixel region 110 with i on capable ' right pixel 112 ' coupling, so, transmit scan line E _{1 (i+1)}With pixel region 110 on (i+1) row ' right pixel 112 ' coupling and transmit scan line E _{2 (i+1)}With pixel region 110 on (i+1) row ' left pixel 111 ' coupling.Then, pixel region 110 on the odd-numbered line ' left pixel 111 ' and even number line on pixel region 110 ' the luminous and odd-numbered line of right pixel 112 ' in subdomain 1F on pixel region 110 ' right pixel 112 ' and even number line on pixel region 110 ' left pixel 111 ' luminous in subdomain 2F.

Then, with reference to Figure 14 to 21 one exemplary embodiment that forms as the emission scan driver 300,400 of an emission scan driver is described.

Figure 14 shows the planimetric map of the organic light emitting display of the 5th one exemplary embodiment according to the present invention.Except emission scan driver 600 replaces outside the emission scan drivers 300,400, have and as shown in Figure 1 the identical structure of organic light emitting display according to the organic light emitting display of the 5th one exemplary embodiment.Emission scan driver 600 will be controlled the luminous emissioning controling signal emit1[1 of pixel 111 successively in subdomain 1F]-emit1[m] send to transmit scan line E ₁₁-E _1mAnd in subdomain 2F, will control the luminous emissioning controling signal emit2[1 of pixel 112 successively]-emit2[m] send to transmit scan line E ₂₁-E _2m

The emission scan driver 600 of generation signal sequence is as shown in Figure 3 described below with reference to Figure 15.

As shown in Figure 3, because emissioning controling signal emit2[i] be emissioning controling signal emit1[i] inversion signal, emission scan driver 600 can be as emission scan driver 300 as shown in Figure 6, one of output emissioning controling signal emit1[i], emit2[i], for example, emit1[i], and, make emissioning controling signal emit1[i] and anti-phase, output emissioning controling signal emit2[i].

With reference to Figure 15, comprise m trigger FF according to the emission scan driver 600 of the 5th one exemplary embodiment ₅₁-FF _5mWith m phase inverter INV ₅₁-INV _5mAnd play shift register.In the time clock VCKL input emission scan driver 600 as shown in Figure 3.Trigger FF _5iWith trigger FF as shown in Figure 6 _2iHave identical connection and structure.Commencing signal VSP2 input trigger FF as shown in Figure 3 ₅₁In.

I trigger FF _5iOutput signal become the emissioning controling signal line E of i on capable _1iEmissioning controling signal emit1[i], (i+1) trigger FF _{5 (i+1)}Input signal and i phase inverter INV _5iInput signal.I phase inverter INV _5iOutput signal be the emissioning controling signal line E of i on capable _2iEmissioning controling signal emit2[i] and phase inverter INV _5iWith emissioning controling signal emit2[i] be inverted into emissioning controling signal emit1[i].

So by moving half time clock VCLK cycle, emission scan driver 600 can be exported successively has the emissioning controling signal emit1[1 of low level pulse respectively with subdomain 1F in the corresponding period]-emit1[m].By moving half time clock VCLK cycle, emission scan driver 600 is with emissioning controling signal emit1[1]-emit1[m] anti-phase, have the emissioning controling signal emit2[1 of low level pulse thereby export successively in the corresponding period respectively with subdomain 2F]-emit2[m].

With reference to Fig. 4 B, because output signal (out) is the inversion signal of the input signal of phase inverter 212, so the input signal of phase inverter 212 can be the reversed-phase output signal (inv) of trigger.Therefore, reversed-phase output signal (inv) can be used as emissioning controling signal emit2[i], in emission scan driver 600, can save phase inverter INV _5i

Below with reference to Figure 16 and 17 the emission scan driver 600a that generates signal sequence is as shown in Figure 8 described.Figure 16 has gone out the signal timing diagram that shows emission scan driver 600a as shown in figure 16 according to the emission scan driver 600a in the organic light emitting display of the 6th one exemplary embodiment and Figure 17.

One of emission scan driver 600a can generate emissioning controling signal emit1[i as emission scan driver 300a as shown in Figure 9] ', emit2[i] ', for example, emit1[i] ', and, can be from emissioning controling signal emit1[i] ' generation emissioning controling signal emit2[i] '.

With reference to Figure 16, comprise (m+1) individual trigger FF according to the emission scan driver 600a of the 6th one exemplary embodiment ₆₁-FF _{6 (m+1)}, a m NAND door NAND ₆₁-NAND _6m, a m NOR door NOR ₆₁-NOR _6mWith m phase inverter INV ₆₁-INV _6mAnd play shift register.Among the time clock VCKL input emission scan driver 600a as shown in Figure 3.I NAND door NAND _6iOutput signal be the emissioning controling signal line E of i on capable _1iEmissioning controling signal emit1[i] ' and phase inverter INV _6iWith NOR door NOR _6iThe anti-phase signal that obtains of output signal be the emissioning controling signal line E of i on capable _2iEmissioning controling signal emit2[i] '.

Trigger FF _6iWith NAND door NAND _6iHave and trigger FF as shown in Figure 9 _2iWith NAND door NAND _2iThe structure of identical connection.Commencing signal VSP2a input trigger FF shown in Fig. 8 and 17 ₆₁In.Then, as shown in Figure 9, by moving half time clock VCLK cycle, NAND door NAND ₆₁-NAND _6mCan export successively and have the emissioning controling signal emit1[1 of low level pulse in the corresponding period respectively with the subdomain 1F and the difference in half time clock VCLK cycle] '-emit1[m] '.

NOR door NOR _6iAt trigger FF ₆₁-FF _{6 (m+1)}Output signal SR ₆₁-SR _{6 (m+1)}Between carry out the NOR computing, output signal is exported to phase inverter INV _6iHere, NOR door NOR _6iWith phase inverter INV _6iPlay the OR door.

With reference to Figure 17, trigger FF _6iOutput signal SR _6iHave low level pulse and NOR door NOR in the corresponding period with subdomain 2F _6iAt trigger FF _6i, FF _{6 (i+1)}Output signal SR _6i, SR _{6 (i+1)}Output high level pulse when the both is in low level.So, NOR door NOR _6iOutput signal have high level pulse and phase inverter INV in the corresponding period with the subdomain 2F and the difference in half time clock VCLK cycle _6iWith NOR door NOR _6iOutput signal anti-phase, output emissioning controling signal emit2[i] '.In addition, because NOR door NOR _{6 (i+1)}Output signal with respect to NOR door NOR _6iOutput signal moved the time clock VCLK cycle half, so, can export emissioning controling signal emit2[1 successively by moving half time clock VCLK cycle] '-emit2[m] '.

In the 6th one exemplary embodiment, generate emissioning controling signal emit1[i respectively by NAND computing and NOR computing] ', emit2[i] ', but emissioning controling signal emit2[i] ' also can generate by the NAND computing.

With reference to Fig. 8 and 17, the emissioning controling signal emit2[i among the subdomain 2F] ' have with respect to emissioning controling signal emit1[i] ' waveform that moved and subdomain 2F in trigger FF _6iOutput signal SR _6iHave with subdomain 1F in trigger FF _6iOutput signal SR _6iAnti-phase waveform.Therefore, emissioning controling signal emit2[i] ' can from output signal SR _6iGenerate in the NAND computing of anti-phase signal.This one exemplary embodiment is described with reference to Figure 18 and 19.

Figure 18 shows the signal timing diagram that shows emission scan driver 600b as shown in figure 18 according to the emission scan driver 600b in the organic light emitting display of the 7th one exemplary embodiment and Figure 19.

With reference to Figure 18, except NAND door NAND _5iOutside, have and as shown in figure 16 the identical structure of emission scan driver 600a according to the emission scan driver 600b of the 7th one exemplary embodiment.In more detail, emission scan driver 600b comprises trigger FF as shown in figure 16 ₆₁-FF _{6 (m+1)}With NAND door NAND ₆₁-NAND _6mAnd comprise and replace NOR door NOR ₆₁-NOR _6mNAND door NAND ₅₁-NAND _5mWith phase inverter INV ₆₁-INV _6m

Shown in Fig. 4 B, because trigger FF _6iOutput signal be the inversion signal of the input signal (inv) of phase inverter 212, input signal (inv) becomes trigger FF _6iReversed-phase output signal/SR _6iNAND door NAND _5iAt trigger FF _6i, FF _{6 (i+1)}Reversed-phase output signal/SR _6i, SR _{6 (i+1)}Between carry out the NAND computing, output emissioning controling signal emit2[1] '.

With reference to Figure 19, because reversed-phase output signal/SR in the 2F subdomain _6iWaveform and the 1F subdomain in output signal SR _6iWaveform identical, as NAND door NAND _5iThe emissioning controling signal emit2[1 of output signal] ' have a signal sequence shown in Fig. 8 and 19.

In the 6th and the 7th one exemplary embodiment, emissioning controling signal emit1[1] ' have low level pulse with the subdomain 1F and the difference in half time clock VCLK cycle in the corresponding period.Here, by change as shown in figure 20 the NAND door and/or the input signal of NOR door can control emissioning controling signal emit1[1] ' the low level period.

With reference to Figure 20, (i-1) and (i+1) trigger FF _{6 (i-1)}, FF _{6 (i+1)}Output signal SR _{6 (i-1)}, SR _{6 (i+1)}Input i NAND door NAND as shown in figure 16 _6iWith i NOR door NOR _6iIn.Emissioning controling signal emit1[i] " have low level pulse and emissioning controling signal emit2[i in the corresponding period with the subdomain 1F and the difference in half time clock VCLK cycle] " have low level pulse with the subdomain 2F and the difference in half time clock VCLK cycle in the corresponding period.

As shown in figure 21, select scanner driver 200 and emission scan driver 600,600a, or 600b can be applicable to organic light emitting display as shown in figure 13.Figure 21 shows the planimetric map of the organic light emitting display of the 8th one exemplary embodiment according to the present invention.

With reference to Figure 21, as shown in Figure 13, transmit scan line E _1iWith pixel region 110 on the i capable (wherein, ' i ' is the odd-integral number less than ' m ') ' left pixel 111 ' coupling and transmit scan line E _2iPixel region 110 with i on capable ' right pixel 112 ' coupling and transmit scan line E _{1 (i+1)}With pixel region 110 on (i+1) row ' right pixel 112 ' coupling and transmit scan line E _{2 (i+1)}With pixel region 110 on (i+1) row ' left pixel 111 ' coupling.In addition, transmit scan line E _1i, E _2i, E _{1 (i+1)}, E _{2 (i+1)}All with 600 couplings of emission scan driver.

Then, with reference to Figure 22 to 33 one exemplary embodiment that forms as the emission scan driver and the selection scanner driver of single scanning driver 700 is described.

Figure 22 shows the planimetric map of the organic light emitting display of the 9th one exemplary embodiment according to the present invention.Except scanner driver 700 is shared the emission scan drivers and selected the scanner driver, have and the identical structure of organic light emitting display shown in Fig. 1 and 14 according to the organic light emitting display of the 9th one exemplary embodiment.Scanner driver 700 will be used to select the selection signal select[1 of homologous lines successively in

subdomain

1F and 2F]-select[m] send to and select sweep trace S ₁-S _mIn addition, scanner driver 700 will be used to control the luminous emissioning controling signal emit1[1 of pixel 111 successively in subdomain 1F]-emit1[m] send to transmit scan line E ₁₁-E _1mAnd in subdomain 2F, will be used to control the luminous emissioning controling signal emit2[1 of pixel 112 successively]-emit2[m] send to transmit scan line E ₂₁-E _2m

As described in the 5th and the 8th one exemplary embodiment, scanner driver can generate emissioning controling signal emit1[i] ', emit2[i] '.Therefore, describe below from this scanner driver to generate select signal select[i] method.

At first, with reference to Figure 23 and 24 scanner driver 700 that generates signal sequence is as shown in Figure 3 described.Figure 23 shows the signal timing diagram that shows scanner driver 700 as shown in figure 23 according to the scanner driver in the organic light emitting display of the 9th one exemplary embodiment 700 and Figure 24.

With reference to Fig. 3, emissioning controling signal emit1[i] be emissioning controling signal emit2[i] inversion signal, and select signal select[i] at emissioning controling signal emit1[i] level and emissioning controling signal emit1[i+1] level have low level in different period.Therefore, scanner driver 700 can generate selects signal select[i] and emissioning controling signal emit1[i], emit2[i].

As shown in figure 23, scanner driver 700 comprises (m+1) individual trigger FF ₇₁-FF _{7 (m+1)}, a m XNOR door XNOR ₇₁-XNOR _7mWith m phase inverter INV ₇₁-INV _7mAnd play shift register.Here, XOR gate and phase inverter can be used as the XNOR door.In addition, in time clock VCLK as shown in figure 15 and the commencing signal VSP2 input scan driver 700.

Trigger FF _7iWith phase inverter INV _7iHave and trigger FF as shown in figure 15 _5iWith phase inverter INV _5iIdentical connection and structure.Therefore, trigger FF _7iOutput signal SR _7iBe emissioning controling signal emit1[i] and phase inverter INV _7iWith trigger FF _7iOutput signal SR _7iThe anti-phase signal that obtains is emissioning controling signal emit2[i].

XNOR door XNOR _7iAt trigger FF _7i, FF _{7 (i+1)}Output signal SR _7i, SR _{7 (i+1)}Between carry out the XNOR computing, signal select[i is selected in output].That is to say XNOR door XNOR _7iAt trigger FF _7i, FF _{7 (i+1)}Output signal SR _7i, SR _{7 (i+1)}Output low level is selected signal select[i when having varying level].

With reference to Figure 24, trigger FF _{7 (i+1)}Output signal SR _{7 (i+1)}With respect to trigger FF _7iOutput signal SR _7iMoved the time clock VCLK cycle half.Therefore, XNOR door XNOR _7iOutput signal select[i] at corresponding subdomain 1F, have low level pulse in half time clock VCLK cycle among the 2F.Select signal select[i] in the negative edge of low level pulse correspond respectively to trigger FF _7iOutput signal SR _7iRising edge.In addition, because output signal SR _{7 (i+1)}With respect to output signal SR _7iMoved the time clock VCLK cycle half, selected signal select[i+1] with respect to selecting signal select[i] moved half the time clock VCLK cycle.

With reference to Fig. 4 B, because slave flipflop FF _7iOutput reversed-phase output signal/SR _7iSo, reversed-phase output signal/SR _7iCan be used as emissioning controling signal emit2[i].

Figure 25 shows according to the scanner driver 700a in the organic light emitting display of the tenth one exemplary embodiment.With reference to Figure 25, except phase inverter INV _6iOutside, scanner driver 700a has and as shown in figure 23 the identical structure of scanner driver.In scanner driver 700a, trigger FF _7iOutput signal SR _7iAnd reversed-phase output signal/SR _7iCorrespond respectively to emissioning controling signal emit1[i] and emit2[i].

Referring now to Figure 26 and 27 the scanner driver 700b that generates signal sequence is as shown in Figure 8 described.Figure 26 shows the signal timing diagram that shows scanner driver 700b as shown in figure 26 according to the scanner driver 700b in the organic light emitting display of the 11 one exemplary embodiment and Figure 27.

As shown in figure 16, the emission scan driver 600b according to the 11 one exemplary embodiment comprises (m+1) individual trigger FF ₈₁-FF _{8 (m+1)}, a m XNOR door XNOR ₈₁-XNOR _8m, a m NAND door NAND ₈₁-NAND _8m, a m NOR door NOR ₈₁-NOR _8mWith m phase inverter INV ₈₁-INV _8mAnd play shift register.Here, among time clock VCLK as shown in figure 17 and the commencing signal VSP2a input scan driver 700b.

Trigger FF _8i, NAND door NAND _8i, NOR door NOR _8iWith phase inverter INV _8iHave and trigger FF as shown in figure 16 _6i, NAND door NAND _6i, NOR door NOR _6iWith phase inverter INV _6iIdentical structure.So, NAND door NAND _8iAt trigger FF _8i, FF _{8 (i+1)}Output signal SR _8i, SR _{8 (i+1)}Between carry out the NAND computing, as shown in figure 27 emissioning controling signal emit1[i of output] '.NOR door NOR _8iAt trigger FF _8i, FF _{8 (i+1)}Output signal SR _8i, SR _{8 (i+1)}Between carry out the NOR computing, output signal is outputed to phase inverter INV _8iAnd phase inverter INV _8iWill be from NOR door NOR _8iThe signal inversion of input, output emissioning controling signal emit2[i as shown in figure 27] '.

In addition, trigger FF _8iWith XNOR door XNOR _8iHave and trigger FF as shown in figure 23 _7iWith XNOR door XNOR _7iIdentical structure.Therefore, XNOR door XNOR _8iAt trigger FF _8i, FF _{8 (i+1)}Output signal SR _8i, SR _{8 (i+1)}Between carry out the XNOR computing, signal select[i is selected in output].

In the 11 one exemplary embodiment, scanner driver 700b has used the commencing signal VSP2a anti-phase with commencing signal VSP2 as shown in figure 24.But scanner driver 700b also can use commencing signal VSP2 as shown in figure 24.Then, because trigger FF _8iOutput signal and as shown in figure 27 output signal SR _8iAnti-phase, NAND door NAND _8iOutput signal corresponding to emissioning controling signal emit2[i] ' and phase inverter INV _8iOutput signal corresponding to emissioning controling signal emit1[i] '.

In addition, scanner driver 700b can use trigger FF _8iReversed-phase output signal.That is to say that the NAND door can be used for replacing NOR door NOR _8iWith phase inverter INV _8iAnd the NAND door can be at trigger FF _8i, FF _{8 (i+1)}Reversed-phase output signal between carry out the NAND computing, output emissioning controling signal emit2[i] '.

And, select signal select[i] can be from emissioning controling signal emit1[i] ', emit2[i] ' middle generation.This one exemplary embodiment is described with reference to Figure 28.Figure 28 shows according to the scanner driver 700c in the organic light emitting display of the 12 one exemplary embodiment.

As shown in figure 28, except generate selecting signal select[i] NAND door NAND _9iOutside, have and as shown in figure 26 the identical structure of scanner driver 700b according to the scanner driver 700c of the 12 one exemplary embodiment.NAND door NAND _9iAt emissioning controling signal emit1[i] ', emit2[i] ' between carry out the NAND computing, signal select[i is selected in output].

With reference to Figure 27, emissioning controling signal emit1[i] ', emit2[i] ' selecting signal select[i] low level be on the high level in the period and emissioning controling signal emit1[i] ', emit2[i] ' one of selecting signal select[i] high level be on the low level in the period.Here, NAND door NAND _9iOutput signal at emissioning controling signal emit1[i] ', emit2[i] ' both is on the low level when being on the high level and NAND door NAND _9iOutput signal can be with the signal select[i that elects].

In addition, if scanner driver 700c uses trigger FF _8iReversed-phase output signal, the NAND door can be used for replacing NOR door NOR _8iWith phase inverter INV _8i

In the 11 and the 12 one exemplary embodiment, can be as controlling emissioning controling signal emit1[i as shown in Figure 20] ', emit2[i] ' the low level period.These one exemplary embodiment are described with reference to Figure 29 to 32.

At first, with reference to the emissioning controling signal emit1[i among Figure 29 description control scanner driver 700b as shown in figure 26] ', emit2[i] ' the 13 one exemplary embodiment of low level period.Figure 29 shows the signal timing diagram according to the scanner driver 700b in the scanner driver of the 13 one exemplary embodiment.

With reference to Figure 29, (i-1) and (i+1) trigger FF _{8 (i-1)}, FF _{8 (i+1)}Output signal SR _{8 (i-1)}, SR _{8 (i+1)}Input i NAND door NAND as shown in figure 26 _8iWith i NOR door NOR _8iIn.Then, emissioning controling signal emit1[i] " have low level pulse and emissioning controling signal emit2[i in the corresponding period with the subdomain 1F and the difference in a time clock VCLK cycle] " have low level pulse with the subdomain 2F and the difference in a time clock VCLK cycle in the corresponding period.

Equally, if (i-j) and (i+k) trigger FF _{8 (i-j)}, FF _{8 (i+k)}Output signal SR _{8 (i-j)}, SR _{8 (i+k)}(wherein, ' j ' and ' k ' is respectively positive integer) input i NAND door NAND _8iWith i NOR door NOR _8iIn, can be by the integral multiple in half time clock VCLK cycle control emissioning controling signal emit1[i] low level period of ", emit2[i] ".

Figure 30 shows the signal timing diagram that shows scanner driver 700d as shown in figure 30 according to the scanner driver 700d in the organic light emitting display of the 14 one exemplary embodiment and Figure 31.

In Figure 30, signal SR _{8 (i-1)}, SR _8i, SR _{8 (i+1)}Be respectively as shown in figure 26 scanner driver 700 in trigger FF _{8 (i-1)}, FF _8i, FF _{8 (i+1)}Output signal.In addition, two signal A _i, B _iCorrespond respectively to the emissioning controling signal emit1[i of scanner driver 700b] ', emit2[i] '.

With reference to Figure 30 and 31, the NAND door is to trigger FF _{8 (i-1)}, FF _8iOutput signal SR8 _(i-1), SR _8iCarry out the NAND computing, so that output signal A _I-1Signal A _I-1With subdomain 1F and half corresponding period in time clock VCLK cycle in have low level pulse and corresponding to as shown in figure 27 emissioning controling signal emit1[i-1] '.NAND door and phase inverter are to trigger FF _{8 (i-1)}, FF _8iOutput signal SR _{8 (i-1)}, SR _8iCarry out the OR computing, so that output signal B _I-1Signal B _I-1With subdomain 2F and half corresponding period in time clock VCLK cycle in have low level pulse and corresponding to as shown in figure 27 emissioning controling signal emit2[i-1] '.In addition, signal A _i, B _iCorrespond respectively to emissioning controling signal emit1[i as shown in figure 27] ', emit2[i] ' and with respect to A _I-1And B _I-1Moved the time clock VCLK cycle respectively half.

And NAND door and phase inverter are to signal A _I-1, A _iCarry out the OR computing, so that output emissioning controling signal emit1[i] ", emissioning controling signal emit1[i] " at signal A _I-1, A _iWhen being low level, the both has low level pulse.NAND door and phase inverter are to signal B _I-1, B _iCarry out the OR computing, so that output emissioning controling signal emit2[i] ", emissioning controling signal emit2[i] " at signal B _I-1, B _iWhen being low level, the both has low level pulse.To trigger FF _8i, FF _{8 (i+1)}Output signal SR _8i, SR _{8 (i+1)}Carry out the XNOR computing, so that signal select[i is selected in output].

In Figure 30 and 31, if use the output signal A of (i-j) and (i+k) NAND door _(i-j), A _(i+k)(wherein, ' j ' and ' k ' is respectively positive integer) can be by the integral multiple in half time clock VCLK cycle control emissioning controling signal emit1[i] low level period of ", emit2[i] ".

Just as shown in Figure 28, select signal select[i] can become by the NAND pupil among Figure 30.This one exemplary embodiment is described with reference to Figure 32.

Figure 32 shows according to the scanner driver 700e in the organic light emitting display of the 15 one exemplary embodiment.With reference to Figure 32, to the output signal A of i NAND door _iCarry out the NAND computing with the output signal Bi of i phase inverter, select signal select[i] so that picture is exported as shown in Figure 28.

As shown in figure 33, can be applied to as shown in figure 13 organic light emitting display according to the scanner driver of the 9th to the 15 one exemplary embodiment.Figure 33 shows the planimetric map of the organic light emitting display of the 16 one exemplary embodiment according to the present invention.

With reference to Figure 33, as shown in Figure 13, transmit scan line E _1iWith pixel region 110 on the i capable (wherein, ' i ' is the odd-integral number less than ' m ') ' left pixel 111 ' coupling and transmit scan line E _2iPixel region 110 with i on capable ' right pixel 112 ' coupling, transmit scan line E _{1 (i+1)}With pixel region 110 on (i+1) row ' right pixel 112 ' coupling and transmit scan line E _{2 (i+1)}With pixel region 110 on (i+1) row ' left pixel 111 ' coupling.In addition, transmit scan line E _1i, E _2i, E _{1 (i+1)}, E _{2 (i+1)}All with 700 couplings of emission scan driver.

In the superincumbent one exemplary embodiment, selection signal select[i-1 has been described] rising edge corresponding to selecting signal select[i] the situation of negative edge, but, select signal select[i] negative edge also can with select signal select[i-1] rising edge separate.For example, amplitude limit (clip) signal CLIP can import among the NAND door NAND4i shown in Fig. 4 A.As shown in figure 34, clipped signal CLIP has with half corresponding cycle in time clock VCLK cycle and has width than half short low level pulse of time clock VCLK cycle.In addition, the low level period of clipped signal CLIP comprises negative edge or the rising edge of time clock VCLK.Then, select signal select[i] ' the low level pulse width become shorter than half time clock VCLK cycle.That is to say, select signal select[i] ' negative edge with select signal select[i-1] ' rising edge separate the low level pulse width of clipped signal CLIP apart.

In the superincumbent one exemplary embodiment, show scanner driver 200,300,400,600, and/or 700 the selection signal that provides and emissioning controling signal directly impose on the situation of selection wire and sweep trace, but also can be 100 and scanner driver 200,300,400 in the viewing area, 600, and/or insert impact damper between 700.In addition, in the viewing area 100 and scanner driver 200,300,400,600, and/or also can insert the level shifter that changes the level of selecting signal and emissioning controling signal between 700.

According to one exemplary embodiment of the present invention, common driving and switching transistor and capacitor can drive two pixels, thereby have reduced the bar number of data line.As a result, can reduce driving data lines integrated circuit number and improved the void ratio of pixel.

Though by in conjunction with some one exemplary embodiment the present invention being described, should be understood that the present invention is not limited to disclosed embodiment, on the contrary, various modification and the equivalent device in the spirit and scope that are included in appended claims contained in the present invention.

Claims

1. display comprises:

The viewing area, described viewing area comprises many data lines sending the data-signal be used for display image, be used to send many first sweep traces selecting signal, be used for sending respectively many second sweep traces and many articles of three scan lines and a plurality of pixel region of emissioning controling signal, and described pixel region comprises first pixel and second pixel with corresponding data line and the coupling of corresponding first sweep trace; With

Scanner driver, described scanner driver sends to first sweep trace by moving first signal that has first pulse in each of a plurality of subdomains that form a territory with first signal, by moving the secondary signal that in first subdomain of a plurality of subdomains, has second pulse secondary signal is sent to second sweep trace, with by moving the 3rd signal that in second subdomain of a plurality of subdomains, has the 3rd pulse the 3rd signal is sent to three scan line

Wherein, first pixel response, second pulsed illumination and second pixel response the 3rd pulsed illumination.

2. display according to claim 1, wherein, when in first subdomain, first pulse transmission being given corresponding first sweep trace, to send to the corresponding data line with the corresponding data-signal of first pixel, with when in second subdomain, first pulse transmission being given corresponding first sweep trace, will send to the corresponding data line with the corresponding data-signal of second pixel.

3. display according to claim 1, wherein, scanner driver comprises first driver, is used for by first signal being moved first period first signal being sent to first sweep trace.

4. display according to claim 3, wherein, first driver comprises:

Second driver is used for exporting the 4th signal by the 4th signal was moved for first period, and the 4th signal has the 4th pulse in second period than first o'clock segment length in each of a plurality of subdomains; With

The 3rd driver is used for having jointly at two the 4th signals that moved for first period at least a portion of the period of the 4th pulse and generates and the corresponding pulse of first pulse.

5. display according to claim 4, wherein, second driver comprises a plurality of triggers, the output of positive going trigger be the input of reverse trigger and oppositely trigger will move for first period from the 4th signal of positive going trigger output and export corresponding the 4th signal.

6. display according to claim 3, wherein, scanner driver comprises:

Secondary signal is sent to second driver of corresponding second sweep trace; With

The 3rd signal is sent to the 3rd driver of corresponding three scan line.

7. display according to claim 6, wherein, the period that second pulse imposes on second sweep trace of corresponding first pixel comprises that first pulse imposes on the period of first sweep trace of corresponding first pixel; With

The period that the 3rd pulse imposes on the three scan line of corresponding second pixel comprises that first pulse imposes on the period of first sweep trace of corresponding second pixel.

8. display according to claim 7, wherein, second driver and the 3rd driver comprise a plurality of triggers respectively,

The output of positive going trigger is the input of reverse trigger,

The reverse trigger of second driver will be by moving output of first period and the corresponding pulse of second pulse with the corresponding pulse of second pulse of the secondary signal of exporting from the positive going trigger of second driver.

The reverse trigger of the 3rd driver will be by moving output of first period and the corresponding pulse of the 3rd pulse with the corresponding pulse of the 3rd pulse of the 3rd signal of exporting from the positive going trigger of the 3rd driver.

9. display according to claim 6, wherein, second driver after first end-of-pulsing of first sweep trace that sends to corresponding first pixel, with second pulse transmission give corresponding first pixel second sweep trace and

The 3rd driver is given the 3rd pulse transmission the three scan line of corresponding second pixel after first end-of-pulsing of first sweep trace that sends to corresponding second pixel.

10. display according to claim 9, wherein, second driver comprises:

The 4th driver is used for exporting the 4th signal by the 4th signal was moved for first period, the 4th signal in a territory, have the 4th pulse and with the 5th pulse of the 4th pulse inversion; With

The 5th driver is used for having jointly at two the 4th signals that moved for first period period generation and the corresponding pulse of second pulse of the 4th pulse.

11. display according to claim 3, wherein, scanner driver further comprises second driver, is used for by mobile secondary signal secondary signal being sent to corresponding second sweep trace and giving three scan line by moving the 3rd signal with the 3rd pulse transmission of corresponding the 3rd signal.

12. display according to claim 11, wherein, the period that second pulse imposes on second sweep trace of corresponding first pixel comprises that first pulse imposes on the period of first sweep trace of corresponding first pixel; With

13. display according to claim 12, wherein, second driver is anti-phase with secondary signal, exports the 3rd signal.

14. display according to claim 11, wherein, second driver is after first end-of-pulsing of first sweep trace that sends to corresponding first pixel, second pulse transmission is given second sweep trace of corresponding first pixel, with after first end-of-pulsing of first sweep trace that sends to corresponding second pixel, the 3rd pulse transmission of the 3rd signal is given the three scan line of corresponding second pixel.

15. display according to claim 14, wherein, second driver comprises:

The 3rd driver is used for exporting the 4th signal by the 4th signal was moved for first period, the 4th signal in a territory, have the 4th pulse and with the 5th pulse of the 4th pulse inversion; With

The 4th driver is used for having jointly at two the 4th signals of the integral multiple that moved for first period period generation and the corresponding pulse of second pulse of the 4th pulse.

16. display according to claim 15, wherein, second driver further comprises:

The 5th driver is used for having jointly at two the 4th signals of the integral multiple that moved for first period period generation and the corresponding pulse of the 3rd pulse of the 5th pulse.

17. display according to claim 15, wherein, the 4th driver further output and the 4th signal inversion the 5th signal and

Second driver further comprises the 5th driver, be used for two the 5th signals at the integral multiple that moved for first period have jointly with the 4th pulsion phase with period of level generate and the corresponding pulse of the 3rd pulse.

18. display according to claim 3, wherein, scanner driver comprises:

First driver is used for exporting the 4th signal by moving the 4th signal, the 4th signal in a territory, have the 4th pulse and with the 5th pulse of the 4th pulse inversion; With

Second driver is used for having at two the 4th signals that moved for first period at least a portion of the period of varying level and generates and the corresponding pulse of first pulse.

19. display according to claim 18, wherein, scanner driver responds the 4th pulse generation and the corresponding pulse of second pulse and responds the 5th pulse and generates and the corresponding pulse of the 3rd pulse.

20. display according to claim 19, wherein, the period that second pulse imposes on second sweep trace of corresponding first pixel comprises that first pulse imposes on the period of first sweep trace of corresponding first pixel; With

21. display according to claim 18, wherein, scanner driver further comprises:

The 3rd driver is used for having jointly at two the 4th signals of the integral multiple that moved for first period period generation and the corresponding pulse of second pulse of the 4th pulse; With

The 4th driver is used for having jointly at two the 4th signals of the integral multiple that moved for first period period generation and the corresponding pulse of the 3rd pulse of the 5th pulse.

22. display according to claim 18, wherein, scanner driver further comprises:

The 3rd driver, the period that is used for having jointly at two the 4th signals that moved for first period the 4th pulse generates the 5th signal with the 6th pulse;

The 4th driver, the period that is used for having jointly at two the 4th signals that moved for first period the 5th pulse generates the 6th signal with the 7th pulse;

The 5th driver is used for having jointly at two the 5th signals of the integral multiple that moved for first period period generation and the corresponding pulse of second pulse of the 6th pulse; With

The 6th driver is used for having jointly at two the 6th signals of the integral multiple that moved for first period period generation and the corresponding pulse of the 3rd pulse of the 7th pulse.

23. display according to claim 3, wherein, scanner driver comprises:

First driver is used for exporting the 4th signal by moving the 4th signal, the 4th signal in a territory, have the 4th pulse and with the 5th pulse of the 4th pulse inversion;

Has second driver that generates in period of the 4th pulse with the corresponding pulse of second pulse jointly at two the 4th signals that moved for first period;

The 3rd driver is used for having jointly at two the 4th signals that moved for first period period generation and the corresponding pulse of the 3rd pulse of the 5th pulse; With

The 4th driver is used for having at least a portion that has with common period of period of the pulse of the 3rd pulse inversion with period of the pulse of second pulse inversion and the 3rd signal in secondary signal and generates and the corresponding pulse of first pulse.

24. display according to claim 3, wherein, scanner driver comprises:

Second driver is used for the period that two the 4th signals at first integral multiple that moved for first period have the 4th pulse jointly to generate the 5th signal with the 6th pulse;

The 3rd driver is used for the period that two the 4th signals at first integral multiple that moved for first period have the 4th pulse jointly to generate the 6th signal with the 7th pulse;

The 4th driver is used for having jointly at two the 5th signals of second integral multiple that moved for first period period generation and the corresponding pulse of second pulse of the 6th pulse; With

The 5th driver is used for having jointly at two the 6th signals of second integral multiple that moved for first period period generation and the corresponding pulse of the 3rd pulse of the 7th pulse.

25. display according to claim 24, wherein, scanner driver further comprises:

The 6th driver is used for having at least a portion that has with common period of period of the pulse of the 3rd pulse inversion with period of the pulse of second pulse inversion and the 3rd signal in secondary signal and generates and the corresponding pulse of first pulse.

26. a display comprises many first sweep traces sending first signal, sends many second sweep traces of secondary signal and sends many articles of three scan lines of the 3rd signal, this display comprises:

First driver is used for exporting first signal by first signal was moved for first period, and first signal has first pulse in second period in each of a plurality of subdomains that form a territory;

Second driver is used for by secondary signal being moved first period output secondary signal, and secondary signal has second pulse in the 3rd period than second o'clock segment length in first subdomain of a plurality of subdomains; With

The 3rd driver is used for exporting the 3rd signal by the 3rd signal was moved for first period, and the 3rd signal has the 3rd pulse in the 4th period than second o'clock segment length in second subdomain of a plurality of subdomains.

27. display according to claim 26, wherein, first driver comprises:

The 4th driver is used for exporting the 4th signal by the 4th signal was moved for first period, and the 4th signal has the 4th pulse in each of a plurality of subdomains; With

The 5th driver is used for having jointly at two the 4th signals that moved for first period at least a portion of the period of the 4th pulse and generates and the corresponding pulse of first pulse.

28. display according to claim 26, wherein, second driver comprises:

The 5th driver is used for having jointly at two the 4th signals of the integral multiple that moved for first period period generation and the corresponding pulse of second pulse of the 4th pulse.

29. display according to claim 26, wherein, second driver comprises:

The 5th driver, the period that is used for having at least one of two the 4th signals of the integral multiple that moved for first period the 4th pulse generates and the corresponding pulse of second pulse.

30. display according to claim 26 further comprises:

Transmission is used for many data lines of the data-signal of display image; With

A plurality of pixel regions,

Wherein, each pixel region comprises:

Respond the pixel driver of one of data-signal that first pulse program of one of first signal applies;

First light-emitting component with the corresponding light of programming data signal is sent in second pulse of one of response secondary signal; With

Second light-emitting component with the corresponding light of programming data signal is sent in the 3rd pulse that responds one of the 3rd signal.

31. a display comprises many first sweep traces sending first signal, sends many second sweep traces of secondary signal and sends many articles of three scan lines of the 3rd signal, this display comprises:

First driver is used for exporting first signal by first signal was moved for first period, and first signal has first pulse in second period in each of a plurality of subdomains that form a territory; With

Second driver, be used for the 3rd signal that from the 4th signal is created on first subdomain of a plurality of subdomains, in the 3rd period, has the secondary signal of second pulse and in second subdomain of a plurality of subdomains, in the 4th period, have the 3rd pulse than second o'clock segment length than second o'clock segment length, by secondary signal being moved first period output secondary signal and exporting the 3rd signal by the 3rd signal was moved for first period.

32. display according to claim 31, wherein, first driver comprises:

The 3rd driver is used for exporting the 5th signal by the 5th signal was moved for first period, and the 5th signal has the 4th pulse in each of first and second subdomains; With

The 4th driver is used for having jointly at two the 5th signals that moved for first period at least a portion of the period of the 4th pulse and generates and the corresponding pulse of first pulse.

33. display according to claim 31, wherein, second driver is exported the 4th signal, as secondary signal with the 4th signal inversion, exports the 3rd signal.

34. display according to claim 31, wherein, second driver comprises:

The 3rd driver is used for exporting the 4th signal by the 4th signal was moved for first period, the 4th signal in a territory, have the 4th pulse and with the 5th pulse of the 4th pulse inversion;

The 4th driver is used for having jointly at two the 4th signals of the integral multiple that moved for first period period generation and the corresponding pulse of second pulse of the 4th pulse; With

35. display according to claim 31 further comprises:

A plurality of pixel regions,

Wherein, each pixel region comprises:

36. display that comprises scanner driver, scanner driver is exported first signal by first signal was moved for first period, by secondary signal being moved first period output secondary signal and exporting the 3rd signal by the 3rd signal was moved for first period, scanner driver comprises:

First driver is used for exporting the 4th signal by the 4th signal was moved for first period, the 4th signal in a territory, have first pulse and with second pulse of first pulse inversion;

Second driver is used for the 3rd signal that has first signal of the 3rd pulse in second period, have the secondary signal of the 4th pulse and have the 5th pulse in first subdomain of a plurality of subdomains in the 3rd period than second o'clock segment length in second subdomain of a plurality of subdomains in the 4th period than second o'clock segment length from the 4th signal is created on each of a plurality of subdomains of forming a territory.

37. display according to claim 36, second driver generates and the corresponding pulse of the 3rd pulse in two the 4th signals that moved for first period have at least a portion of period of varying level.

38. display according to claim 36, wherein, second driver is exported the 4th signal, as secondary signal with the 4th signal inversion, exports the 3rd signal.

39. display according to claim 36, wherein, second driver comprises:

The 3rd driver is used for having jointly at two the 4th signals of the integral multiple that moved for first period period generation and the corresponding pulse of the 4th pulse of first pulse; With

The 4th driver is used for having jointly at two the 4th signals of the integral multiple that moved for first period period generation and the corresponding pulse of the 5th pulse of second pulse.

40. according to the described display of claim 39, wherein, second driver further comprises the 5th driver, is used for having at secondary signal and the 3rd signal at least a portion of the period of same level and generates and the corresponding pulse of the 3rd pulse.

41. display according to claim 36, wherein, second driver comprises:

The 3rd driver, being used for period that two the 4th signals at first integral multiple that moved for first period have first pulse jointly generates in the period that two the 4th signals that have the 5th signal of the 6th pulse and moved first integral multiple of first period have second pulse jointly and generates the 6th signal with the 7th pulse; With

The 4th driver, being used for period that two the 5th signals at second integral multiple that moved for first period have the 6th pulse jointly generates to have jointly in period of the 7th pulse with corresponding pulse of the 4th pulse and two the 6th signals having moved second integral multiple of first period and generates and the corresponding pulse of the 5th pulse.

42. according to the described display of claim 41, wherein, second driver further comprises the 5th driver, is used for having at the 5th signal and the 6th signal at least a portion of the period of same level and generates and the corresponding pulse of the 3rd pulse.

43. display according to claim 36 further comprises:

A plurality of pixel regions,

Wherein, each pixel region comprises:

Respond the pixel driver of one of data-signal that the 3rd pulse program of one of first signal applies;

First light-emitting component with the corresponding light of programming data signal is sent in the 4th pulse of one of response secondary signal; With

Second light-emitting component with the corresponding light of programming data signal is sent in the 5th pulse that responds one of the 3rd signal.

44. the driving method of a display, display comprises first sweep trace, second sweep trace, three scan line, send the data line of the data-signal that is used for display image and the pixel region that is limited by first, second and three scan line and data line, and this driving method comprises:

Output has the selection signal of first pulse in first period in each of a plurality of subdomains that form a territory;

Output has first emissioning controling signal of second pulse in second period than first o'clock segment length in first subdomain of a plurality of subdomains; With

Output has second emissioning controling signal of the 3rd pulse in the 3rd period than first o'clock segment length in second subdomain of a plurality of subdomains,

Wherein, response and the corresponding pulse of first pulse that sends to first sweep trace, data-signal is programmed into pixel region, first pixel response of pixel region and the corresponding pulse of second pulse that sends to second sweep trace, begin to send and the corresponding light of programming data signal, second pixel response and the corresponding pulse of the 3rd pulse that sends to three scan line with pixel region begin to send and the corresponding light of programming data signal.

45., further comprise according to the described driving method of claim 44:

Export first signal by first signal was moved for the 4th period, first signal has the 4th pulse in each of a plurality of every section; With

In having at least a portion of period of the 4th pulse jointly, two first signals that moved for the 4th period generate first pulse.

46. according to the described driving method of claim 44, wherein, second emissioning controling signal is corresponding to the signal anti-phase with first emissioning controling signal.

47., further comprise according to the described driving method of claim 44:

Export first signal by first signal was moved for the 4th period, first signal in a territory, have the 4th pulse and with the 5th pulse of the 4th pulse inversion; With

In having period of the 4th pulse jointly, two first signals of the integral multiple that moved for the 4th period generate second pulse.

48., further comprise according to the described driving method of claim 47:

In having period of the 5th pulse jointly, two first signals of the integral multiple that moved for the 4th period generate the 3rd pulse.

49., further comprise according to the described driving method of claim 47:

In having at least a portion of period of varying level, two first signals that moved for the 4th period generate first pulse.

50., further comprise according to the described driving method of claim 47:

Have to have at least a portion with common period of period of the pulse of the 3rd pulse inversion at first emissioning controling signal and generate first pulse with the period of the pulse of second pulse inversion and second emissioning controling signal,

Wherein, integral multiple is 1 multiple.

51., further comprise according to the described driving method of claim 44:

In having period of the 4th pulse, two first signals of the integral multiple that moved for the 4th period generate second pulse.

52., further comprise according to the described driving method of claim 44:

Export first signal by first signal was moved for the 4th period, first signal in a territory, have the 4th pulse and with the 5th pulse of the 4th pulse inversion;

Have at two first signals that moved for the 4th period and to generate second pulse in period of varying level; With

Respond the 4th pulse and the 5th pulse and generate second pulse and the 3rd pulse respectively.