CN1678086A - A device for playing and receiving high-speed code stream based on PCI - Google Patents

Abstract

The disclosed device in use for testing and analyzing code stream in digital TV includes computer, code stream playing card, and code stream receiving card. The said code stream playing card, and code stream receiving card are composed of FPGA programmable logic device, PCI interface chip, external storage FIFO in large capacity and periphery devices respectively. FPGA is in use for controlling PCI state, coordinating operations between PCI interface chip and FIFO. PCI state and logic control, NCO circuit, data buffer, interrupt control, code rate adjustment etc. are collocated in FPGA of the playing card. Input interface selection, input signal processing, PCI state and logic control, data buffer, interrupt control etc. are collocated in FPGA of the receiving card. Reasonable using function of PCI interface chip, through FPGA processing, the invention realizes code rate in high rate played and received by computer. The transmitted code rate can reach as high as 120Mbps.

Description

A device for playing and receiving high-speed code stream based on PCI

technical field

The invention relates to the technical field of digital television broadcasting, in particular to a device for playing and receiving high-speed code streams based on peripheral device interconnection PCI.

Background technique

With the development of digital TV and the establishment of the MPEG-2 standard, the development and application of digital audio and video and MPEG in the field of digital TV at home and abroad have entered a stage of rapid development. In the process of source coding and channel maintenance design, it is often necessary to know whether the generated code stream or the obtained code stream conforms to the standard. Sometimes it is necessary to analyze the code stream to obtain its performance in encoding and transmission. In the process of digital TV system monitoring or fault checking, etc., relevant equipment is also required to analyze the generated or obtained code stream. There are other devices that also need to perform code stream verification procedures during modulation. All these tasks require devices capable of receiving and playing code streams to be implemented.

At present, several major instruments and broadcasting equipment manufacturers at home and abroad are developing or developing such equipment, and their hardware design is also based on the computer PCI interface. But its design principle is more complicated, and its performance is not ideal enough. For example, the "MPEG-2 Transport Stream Data Acquisition Card BSRC-11 and Sending Card BSTC-11" developed by Blue Topology, a well-known professional manufacturer of digital TV test and measurement equipment in China, are both devices based on PCI interface. The signal processing module uses a programmable logic device with relatively large resources, and the code rate of the code stream it can receive or send is up to 108Mbps. On the other hand, the design cost of the product is relatively high. However, although the code stream player and receiving card produced by the American computer module company is relatively simple in design, the product has a single function, and can only send and receive a single code stream, and does not have the function of code rate adjustment.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art, to provide a high-speed code stream playback and receiving device based on the interconnection of peripheral devices with PCI, and to control the playback and reception of high-speed code streams by interconnecting PCI interface chips with computer peripheral devices, which can be used for Analysis, testing and monitoring of high-speed code stream of digital TV system.

The technical scheme for realizing the present invention includes a PC, a code stream playing card and a code stream receiving card, and the PC is connected to a PCI interface chip through peripheral devices to control the code stream playing card and the code stream receiving card, so as to realize the playing and collecting of code streams. The code stream playing card is mainly composed of programmable logic device FPGA, PCI interface chip, external large-capacity memory FIFO and peripheral device 27M clock source, FPGA initialization and configuration, AD9851 frequency synthesizer, ASI output and SPI output module. The code stream receiving card is mainly composed of programmable logic device FPGA, PCI interface chip, external large-capacity memory FIFO and peripheral component 27M clock source, FPGA initialization and configuration, ASI input and SPI input module; wherein,

The programmable logic device FPGA is connected with the PCI interface chip and the external large-capacity memory FIFO, and is used to control the interconnected PCI status of peripheral devices and coordinate the work between the PCI interface chip and the external FIFO;

The PCI interface chip is used to simplify the PCI bus protocol, convert the complex PCI bus operation into a simple local bus operation, and cooperate with the programmable logic device FPGA to realize the transmission and reception of code stream data;

The 27MHZ clock source is used for the generation and shaping of the reference clock, and generates a 27MHZ system clock to provide a stable reference clock for CY7B933/CY7B923 chips, FPGA and PCI interface chips;

FPGA initialization and configuration, when powering on, download the relevant setting information required by the FPGA to the configuration space of the FPGA, so that the FPGA can realize the required functions;

External large-capacity memory FIFO is used to buffer data when playing/receiving high-speed bit rate streams, and improve the processing speed of PCs for data;

AD9851 frequency synthesizer, used to synthesize a clock with the same size as the code rate of the code stream, and send the clock signal to the clock control module;

The SPI output module completes the level conversion of the output signal, converts the output TTL level signal into a low-voltage differential level signal LVDS output, realizes the conversion of the SPI signal into a signal output suitable for cable transmission, and improves the anti-interference of the signal in channel transmission ability;

ASI output module converts ASI signal into a signal suitable for cable transmission, including CY7B923 chip, coupling shaping circuit, CY7B923 chip mainly realizes 8/10bit conversion of code word, inserts synchronous word K28.5 and parallel to serial conversion, and completes constant output rate 270MHZ ASI signal drive and coupling output;

The SPI input module completes the level conversion of the input signal, converts the low-voltage differential level signal LVDS input from the SPI interface into a TTL level signal, and outputs 11 signals that conform to the SPI signal structure;

The ASI input module mainly completes the coupling amplification and shaping of the input signal. The interface coupling circuit completes the recovery of the clock and data of the input signal. The CY7B933 chip mainly realizes the 10/8bit conversion of the code word, removes the synchronization word K28.5 and serial-to-parallel conversion. Output 8 parallel data signals, the transmission rate of ASI is constant at 270MHZ. Due to the different rates of the code stream, an internal FIFO is required to complete the rate matching of the input signal, which is realized by using the internal RAM of the FPGA.

The main configuration of the programmable logic device FPGA of the player card of the present invention includes PCI state and logic control, NCO numerical control oscillator circuit, data cache, clock control, interrupt control, output clock synthesis and control, code rate adjustment, output interface selection, interface Chip control module. in,

PCI state and logic control, realize the function of PCI and complete the DMA control of PCI, send the output interface selection signal generated by address decoding to the output interface selection module; output the generated clock control signal to the clock control module; output the generated continuous pulse Sent to the NCO circuit as the write clock of the configuration word;

Data cache, using the FIFO provided inside the FPGA, caches the configuration words input by the computer and the data transmitted between the computer and the FIFO of the external large-capacity memory, and combines the PCI status and logic control module to transmit different configuration words when the device starts To NCO circuit and output clock synthesis and control module;

NCO numerically controlled oscillator circuit, the computer software converts the new code rate to be adjusted into a configuration word and sends it to the NCO circuit module, and the NCO generates a clock signal in line with the new code rate according to the configuration word information, realizing the adjustable step accuracy of the code rate 1HZ, and send the clock signal to the code rate adjustment module;

The code rate adjustment module receives the code stream sent by the external large-capacity memory FIFO and the clock signal input by the NCO circuit, and realizes the multi-code rate playback of a single program source, that is, by changing the code rate of the original code stream, any program with an accuracy of 1HZ code rate output;

Clock control, control the clock synthesized by AD9851 according to the input clock control signal, and output this clock signal to the external large-capacity memory as the clock for reading data from the external large-capacity memory.

Output clock synthesis and control module, the computer software analyzes the code rate of the code stream and converts it into the corresponding configuration word and sends it to the module. This module realizes writing the configuration word into the AD9851 frequency synthesizer, and controls the AD9851 chip to The clock control module outputs a corresponding clock;

The interrupt control module uses the half-full state of the external memory FIFO as an interrupt signal to realize communication between the external hardware and the computer software, and the computer software uses the signal as a time mark for the computer to initiate data transmission;

The output interface selection module, according to the selection input control signal set by the computer, completes sending signals from the ASI interface or the SPI interface;

Output chip control module, the transmission rate of ASI is constant at 270MHZ, but the output code stream rate is different, it is necessary to use FIFO to achieve rate matching, and carry out logic control on the output data, communication between FIFO and CY7B923 chip;

The main configuration of the programmable logic device FPGA of the code stream receiving card of the present invention includes input interface selection, input signal processing, PCI state and logic control, interrupt control, data cache module, and the main purpose and signal transmission relationship of each configuration module are as follows:

The input interface selection module controls the input signal according to a selection set by the computer, and completes receiving the ASI input signal or the SPI input signal;

The input signal processing module analyzes the selected interface input signal and writes it into the external large-capacity memory FIFO, and controls the start/stop time of receiving data according to the input control signal set by the computer;

The data cache module caches the data to ensure stable DMA transmission of data between the external memory and the internal memory of the computer;

The interrupt control module uses the half-full state of the external memory as an interrupt signal to realize the communication between the external hardware and the computer software, and the computer software uses the signal as a sign of when the computer initiates data transmission;

The PCI state and logic control module realizes the functions of PCI and completes the DMA control of PCI, and sends the input interface selection signal generated by address decoding to the input interface selection module; the generated enable signal is sent to the input signal processing module.

The invention uses a powerful special-purpose PCI interface chip and rationally designs the configuration of the programmable logic device FPGA, and realizes playing and receiving code streams directly by a computer. Compared with the prior art, the invention has the advantages of simple hardware circuit design, perfect function, good performance, low equipment cost and high-speed transmission of code stream data. The code rate of its transmitted code stream is as high as 120Mbps, which can meet the processing of multi-channel synthesis of high code rate transmission stream. With the assistance of software, it can detect and analyze the code stream while realizing the playback and reception of the code stream. Therefore, the present invention has wide applications in the installation, debugging, detection and maintenance of digital television systems.

Description of drawings

Fig. 1: overall structural diagram of the present invention

Figure 2: Internal structure diagram of the code stream playing card of the present invention

Figure 3: Flow chart of the internal structure of the code rate adjustment module of the present invention

Figure 4: Internal structure diagram of the code stream receiving card of the present invention

Figure 5: Schematic diagram of the test of the present invention

Detailed ways

Referring to Fig. 1, the internal structure of the present invention comprises a code stream playing card, a code stream receiving card and a PC, and the PC controls the code stream playing card and the code stream receiving card through the peripheral interconnection PCI interface chip respectively, so as to realize the playing and receiving of data .

Referring to Fig. 2, the composition of code stream playing card of the present invention comprises PCI interface chip, external mass memory FIFO, programmable logic device FPGA, and SPI output, ASI output, 27MHZ clock source, AD9851 chip, FPGA initialization and configuration module. The internal configuration of programmable logic device FPGA includes PCI state and logic control, data cache, interrupt control, output clock synthesis and control, clock control, NCO numerical control oscillator circuit, code rate adjustment module, output interface selection output chip control module, the above The purpose and signal transmission relationship of each component module are as follows:

The PCI interface chip converts complex PCI bus operations into simple local bus operations and simplifies the PCI bus protocol. At the same time, the powerful functions of the PCI bus interface chip ensure the flexibility of circuit design and the stability of performance, and are more efficient in completing high-speed data processing. demonstrate its superiority. The PCI interface chip selects the PLX PCI9054 chip that can perform DMA transmission function, and cooperates with the programmable logic device FPGA to realize the transmission of code stream data.

PCI status and logic control, realizing PCI functions and completing PCI DMA control, ensuring stable and accurate playback of high-speed streams. It mainly completes the control between PCI bus interfaces, address and data control, address decoding, data DMA transmission process and state control. The address decoding generates an output interface selection signal and outputs it to the output interface selection module, generates a clock control signal and outputs it to the clock control module, generates continuous pulses and sends them to the NCO circuit as a write clock for the configuration word.

Data cache, use the FIFO provided inside the FPGA to cache the input data. The FIFO is combined with PCI state and logic control to realize the transmission of different configuration words sent by the computer to the NCO circuit and the output clock synthesis and control module, and then it is dedicated to buffering data between the computer and the external large-capacity memory.

External large-capacity memory, in order to make up for the DMA processing of the computer and the delay in computer internal data reading when realizing high-bit-rate stream playback, a large-capacity external memory is needed to cache data, and at the same time, by changing the read-write rate, improve The speed at which the local end of the PCI interface chip processes data.

Interrupt control, using the half-full state of the external memory as the interrupt signal to realize the communication between the external hardware and the computer software. At the same time, the computer software takes the signal as the time mark for the computer to initiate data output.

Output clock synthesis and control, through computer software analysis to obtain the code rate of the code stream and convert it into the corresponding configuration word and send it to the module. This module realizes the writing of the control configuration word into the AD9851 frequency synthesizer and controls the AD9851 frequency synthesizer Output the corresponding clock to the clock control module;

AD9851 frequency synthesizer, used to synthesize a clock with the same size as the code rate of the code stream, and send this clock signal to the clock control module;

Clock control, control the clock synthesized by AD9851 according to the input clock control signal, and output this clock signal to the external large-capacity memory as the clock for reading data from the external large-capacity memory.

NCO circuit, the computer software converts the new code rate to be adjusted into a configuration word and sends it to the NCO circuit module. The NCO generates a clock signal in line with the new code rate according to the configuration word information, and the output clock is sent to the code rate adjustment module. The code stream will be output from the external interface at this code rate, and the step accuracy of the circuit to realize the adjustable code rate is 1HZ.

The output interface selection realizes the control of the input signal according to a selection set by the computer, and completes sending signals from the ASI interface or the SPI interface.

The SPI output module completes the level conversion of the output signal, converts the output TTL level signal into a low-voltage differential level signal (LVDS) output, converts the SPI signal into a signal output suitable for cable transmission, and improves the resistance of signal transmission in the channel Interference ability.

Output chip control, the transmission rate of ASI is constant at 270MHZ, but the output stream rate is different, so it is necessary to use FIFO to achieve rate matching, and it is necessary to carry out logic control on the output data, communication between FIFO and CY7B923 chip.

The ASI output module converts the ASI signal into a signal suitable for cable transmission. Including CY7B923 chip, coupling shaping circuit. Among them, the CY7B923 chip mainly realizes the 8/10bit conversion of the code word, inserts the synchronous word K28.5 and parallel/serial conversion, and completes the drive and coupling output of the ASI signal with a constant output rate of 270MHZ.

27MHZ clock source, generation and shaping of reference clock, generate 27MHZ system clock, provide stable reference clock for CY7B933 chip, FPGA and PCI interface chip.

FPGA initialization and configuration. When powering on, download the relevant setting information required by the FPGA to the configuration space of the FPGA, so that the FPGA can realize the required functions.

The code rate adjustment module realizes multi-bit rate playback of a single program source, that is, by changing the code rate of the original code stream, the code stream is output at an arbitrary code rate with an accuracy of 1HZ. The code stream adjustment is to detect the synchronization header after the input TS code stream is cached, "package" the TS stream into a continuous stream of one packet per 188Byte, perform PCR detection in units of packets, and extract the PCR value in the TS stream , and subtract the PCR value from the number generated by the counter to get a new PCR value and then insert it into the TS stream. Insert the input clock generated by the NCO circuit into empty packets in the TS stream with modified PCR information to generate a new TS stream. Then extract the PCR value in the new TS stream again, add the PCR value and the number generated by the counter, modify the PCR information for the second time, and finally put the obtained PCR information into the TS stream to complete the encoding of the code stream Code rate adjustment.

As shown in Figure 3, the internal configuration of described code rate adjustment module comprises: internal FIFO (A), synchronous header detection, PCR detection, subtractor, PCR insertion, internal FIFO (B), empty packet generator and empty packet insertion , internal FIFO (C), adder and counter. The purpose and signal transmission relationship of each configuration are as follows:

[1] Internal FIFO (1): Use the FIFO provided inside the FPGA to buffer the input TS stream, use a 27MHZ high clock as the readout clock of the FIFO, and read the TS stream to increase the speed for subsequent processing;

[2] Synchronization header detection: TS stream is composed of TS packets, and each TS packet is composed of 188Byte data. This module extracts the implicit synchronization signal in the input TS stream, which is equivalent to processing the TS stream into a A string of consecutive TS packets. The output of the TS after the synchronization head detection is divided into two channels, one is used for PCR detection, and the other is input to the PCR insertion module to complete the modification of PCR information

[3] PCR detection: extract the PCR value in the TS stream. The format of the TS stream conforms to the MPEG-2 standard, in which the information of each TS packet header is fixed, and the PCR detection knows whether the packet contains PCR information by detecting the TS packet header information. If the TS packet contains PCR information, Then extract its PCR value, and output it to the addition and subtraction operator;

[4] Subtractor: Subtract the PCR value extracted from the TS stream with the count generated by the counter whose reference clock is 27MHZ, and output the result as a new PCR value;

[5] PCR insertion: Detect the input TS stream signal in units of packets, remove the PCR value in the PCR field of the TS stream, and then insert the new PCR value into the PCR field in the TS stream to complete the PCR information modification TS stream and output;

[6] Internal FIFO (2): Use the FIFO provided inside the FPGA to buffer the input TS stream, and at the same time use the input clock generated by the NCO circuit as the read clock of the FIFO to read the TS stream and match the FIFO when it is full The signals are sent to the empty packet generator together;

[7] Empty packet generator: output a data stream with empty information conforming to the TS packet format, that is, output an empty packet.

[8] Empty packet insertion: According to the empty and full signal of the input internal FIFO (2), when the half-full signal of the internal FIFO (2) is valid, the input TS stream is output in units of packets, otherwise an empty packet is output, and the empty packet is completed. Insertion of packages.

[9] Internal FIFO (3): Use the FIFO provided inside the FPGA to buffer the input new TS stream. The output signal is divided into two paths: one path enters the PCR extension for extracting PCR information; the other path is transmitted to the PCR insertion module to complete the modification of PCR information.

[10] Adder: Add the PCR value extracted from the TS stream to the number generated by the counter whose reference clock is 27MHZ, and send the result as a new PCR value.

[11] Counter: The reference clock 27MHZ is used as the counting clock of the counter, and the resulting count is input into the adder and subtractor to adjust the PCR value.

Referring to Fig. 4, the composition of code stream receiving card of the present invention comprises ASI input module, SPI input module, programmable logic device FPGA, external mass memory FIFO, PCI interface chip, 27MHZ clock source, FPGA initialization and configuration. The internal configuration of FPGA includes: input interface selection, input signal processing, PCI state and logic control, interrupt control, and data cache module. The purposes of the modules such as the external large-capacity memory FIFO, PCI interface chip, 27M clock source and FPGA initialization and configuration are the same as the corresponding modules of the stream playing card. The purpose and data transmission relationship of other components are as follows:

ASI input module: mainly completes the coupling amplification and shaping of the input signal, the interface coupling circuit completes the clock and data recovery of the input signal, the CY7B933 chip mainly realizes the 10/8bit conversion of the code word, removes the synchronization word K28.5 and serial-to-parallel conversion, Output 8 parallel data signals. The transmission rate of ASI is constant at 270MHZ, but the rate of the code stream is different, so a FIFO is needed to complete the rate matching of the input signal, which is realized by using the internal RAM of the FPGA.

SPI input module: Complete the level conversion of the input signal, convert the low-voltage differential level signal (LVDS) input by the SPI into a TTL level signal, and output 11 signals conforming to the SPI signal structure.

Input interface selection: realize a selection control input signal according to the computer setting, and complete receiving ASI input signal or SPI input signal.

Input signal processing: complete the analysis of the selected interface input signal, write it into the external large-capacity memory, and control when to start or stop receiving data according to an enabling control signal input set by the computer.

Data cache: cache data to ensure stable DMA transfer of data between external memory and computer internal memory.

Interrupt control: The half-full state of the external memory is used as the interrupt signal to realize the communication between the external hardware and the computer software. At the same time, the computer software uses this signal as a sign of when the computer initiates data transmission.

PCI state and logic control: Realize the function of interconnecting PCI with peripheral devices and complete the DMA control of PCI to ensure stable and accurate reception of high-speed code streams. It mainly completes the control between PCI bus interfaces, address and data control, address decoding, data DMA transmission process and state control. The address decoding generates an input interface selection signal and sends it to the input interface selection module, and generates an enable signal and sends it to the input signal processing module.

Working process of the present invention is as follows:

In the present invention, by rationally designing the configuration of the programmable logic device FPGA and utilizing the powerful functions of the PCI interface chips on the peripheral devices, the data stored in the computer can be continuously sent from the external interface in a predetermined format, or received from the external interface. The continuous code stream from the interface is stored in the computer.

The working process of its code stream playback is: first, the computer completes the hardware initialization; then, under the control of the PCI interface chip, the code stream data in the internal storage area of the computer is transferred to the external large-capacity memory FIFO in DMA mode, and the DMA of the data The transmission adopts the block transmission method. The block size of each transmission is half of the capacity of the external FIFO. At the same time, the half-full flag of the external FIFO is used as the interrupt signal source to feed back to the computer. The computer controls the DMA transmission of data through the received interrupt signal. , the implementation method is to transmit data by DMA every time an interrupt is received. Since the output data rate of the external interface is less than 27MBps, and the computer writes data to the external FIFO at a rate of 27MBps, there is always data in the external FIFO, which can ensure that the external interface It can continuously output data, during which FPGA controls the PCI state, coordinates the work between the PCI interface chip and the external FIFO; then the AD9851 frequency synthesis circuit generates a clock with the same size as the code rate of the bit stream, and the clock is controlled continuously from the clock through the clock control module. The code stream data is read out from the external FIFO and sent to the code rate adjustment module in the FPGA. The stream is output in ASI format or in SPI format.

The working process of receiving the code stream is: first, the computer completes the hardware initialization; then the computer controls the PCI interface chip to send read and write instructions to the FPGA, and the FPGA internally notifies the input signal processing module to start writing data to the external FIFO through instruction decoding, and The half-full flag of the external FIFO is used as an interrupt signal source, and sent to the computer through the PCI interface chip to realize the communication between the external FIFO and the computer. Under the control of the PCI interface chip, the data in the external FIFO is written into the internal memory of the computer in the form of DMA, and the DMA transmission of the data adopts the block transmission method, and the block size of each transmission is half of the capacity of the external FIFO. The DMA transmission of data is controlled by the received interrupt signal. The implementation method is to transmit data by DMA every time an interrupt is received. Since the input data rate of the external interface is less than 27MBps, and the computer reads data to the external FIFO at a rate of 27MBps, There will never be overflow in the external FIFO, which can ensure that the continuous input data of the external interface is completely received. During this time, the FPGA controls the PCI state and coordinates the work between the PCI interface chip and the external FIFO.

Fig. 5 is a schematic diagram of the present invention for code stream transmission testing. When using the present invention to test the TS flow transmitted in the communication network, the device can be connected to the node to be tested, and the TS flow can be collected into the computer through the ASI interface or SPI interface, and then the corresponding software can be used to realize the collection Analyze the code stream information to obtain the code stream information needed or to be detected; when it is necessary to add a test source to the test node, the code stream stored in the PC can be played out. This device supports the ASI signal format And SPI signal format output, and the code rate of the output code stream can be changed arbitrarily according to the needs, and the accuracy of the code rate can be changed up to 1Hz/s.

Claims (4)

1. A high-speed code stream playing and receiving device based on PCI, comprising a computer, a code stream playing card and a code stream receiving card; Playing and receiving code stream; the code stream playing card is mainly composed of programmable logic device FPGA, peripheral device interconnection PCI interface chip, external large-capacity memory FIFO and peripheral device 27MHZ clock source, FPGA initialization and configuration, AD9851 frequency synthesizer , ASI output and SPI output modules; the code stream receiving card is mainly composed of programmable logic device FPGA, peripheral device interconnection PCI interface chip, external large-capacity memory FIFO and peripheral device 27MHZ clock source, FPGA initialization and configuration, ASI input It is composed of SPI input module; the purpose and signal transmission relationship of the above-mentioned components are as follows: The programmable logic device FPGA is connected with the PCI interface chip and the external memory FIFO to control the PCI state and coordinate the work between the PCI interface chip and the external FIFO; The PCI interface chip is used to simplify the PCI bus protocol, convert the complex PCI bus operation into a simple local bus, and cooperate with the programmable logic device FPGA to realize the transmission and reception of code stream data; The 27MHZ clock source is used for the generation and shaping of the reference clock, and generates a 27MHZ system clock to provide a stable reference clock for CY7B933/CY7B923 chips, FPGA and PCI interface chips; FPGA initialization and configuration, when powering on, download the relevant setting information required by the programmable logic device FPGA to the configuration space of the FPGA, so that the FPGA can realize the required functions; The external large-capacity memory FIFO is used to cache data to compensate for the DMA processing of the computer and the delay in the internal data reading of the computer when the high-bit rate stream is played/received. At the same time, the local end of the PCI interface chip can be improved by changing the read-write rate data processing speed; AD9851 frequency synthesizer, used to synthesize a clock with the same size as the code rate of the code stream, and send the clock signal to the clock control module; The SPI output module completes the level conversion of the output signal, and realizes the conversion of the SPI signal into a signal output suitable for cable transmission; ASI output module, including CY7B923 chip, coupling shaping circuit, converts ASI signal into signal suitable for cable transmission, CY7B923 chip mainly realizes 8/10bit conversion of code word, inserts synchronous word K28.5 and parallel/serial conversion, completes output rate Drive and coupling output of ASI signal which is constant at 270MHZ; The SPI input module completes the level conversion of the input signal, and outputs 11 signals conforming to the SPI signal structure to the input interface selection module; The ASI input module completes the coupling amplification and shaping of the input signal, and the coupling shaping circuit completes the recovery of the clock and data of the input signal. The CY7B933 chip realizes the 10/8bit conversion of the code word, removes the synchronous word K28. The interface selection module outputs 8 parallel data signals. 2. The high-speed code stream playing and receiving device according to claim 1, characterized in that the configuration of the programmable logic device FPGA of the code stream playing card includes PCI state and logic control, NCO numerically controlled oscillator circuit, data cache, Clock control, interrupt control, output clock synthesis and control, code rate adjustment, output interface selection, interface chip control module, the purpose and signal transmission relationship of each configuration module are as follows: PCI state and logic control, realizing the function of interconnecting PCI with peripheral devices and completing the DMA control of PCI, sending the output interface selection signal generated by address decoding to the output interface selection module; the generated clock control signal is output to the clock control module; generating The continuous pulse is sent to the NCO numerical control oscillator circuit as the write clock of the configuration word; Data cache, using the FIFO provided inside the programmable logic device FPGA, caches the configuration words input by the computer and the data transmitted between the computer and the external large-capacity memory FIFO, and transmits different configuration words to the NCO circuit and output when the device starts Clock synthesis and control module; The NCO numerically controlled oscillator circuit generates a clock signal that meets the new code rate according to the configuration word information sent by the computer, and sends the clock signal to the code rate adjustment module; The code rate adjustment module receives the code stream sent by the external large-capacity memory FIFO, and realizes the multi-bit rate playback of a single program source; Clock control, control the clock synthesized by AD9851 according to the input clock control signal, and output this clock signal to the external large-capacity memory as the clock for reading data from the external large-capacity memory; The output clock synthesis and control module realizes writing the control configuration word into the AD9851 frequency synthesizer, and controls the AD9851 chip to output the corresponding clock to the clock control module; The interrupt control module uses the half-full state of the external memory FIFO as an interrupt signal to realize communication between the external hardware and the computer software, and the computer software uses the signal as a sign of when the computer initiates data transmission; The output interface selection module, according to the selection input control signal set by the computer, completes sending signals from the ASI interface or the SPI interface; The interface chip control module performs logic control on the output data, communication between FIFO and CY7B923 chip. 3. The high-speed code stream playing and receiving device according to claim 1, characterized in that the configuration of the programmable logic device FPGA of the code stream receiving card includes input interface selection, input signal processing, PCI state and logic control, interrupt Control, data cache module, the main purpose and signal transmission relationship of each configuration module are as follows: The input interface selection module controls the input signal according to a selection set by the computer, and completes receiving the ASI input signal or the SPI input signal; The input signal processing module analyzes the selected interface input signal and writes it into the external large-capacity memory FIFO, and controls the start/stop time of receiving data according to the input control signal set by the computer; The data cache module caches the data to ensure the stable DMA transmission of data between the external memory FIFO and the internal memory of the computer; The interrupt control module takes the half-full state of the external memory FIFO as an interrupt signal to realize the communication between the external hardware and the computer software, and the computer software uses the signal as the time mark for the computer to initiate data transmission; PCI state and logic control module, realizing the function of interconnecting peripheral devices with PCI and completing the DMA control of PCI, sending the input interface selection signal generated by address decoding to the input interface selection module; sending the generated enable signal to the input signal processing module. 4. The high-speed code stream playing and receiving device according to claim 2, wherein said code rate adjustment module mainly includes internal FIFO (A), (B), (C), synchronous head detection, PCR detection, PCR Insertion, subtractor and adder, counter, null packet generator and null packet insertion module; where: [1] Internal FIFO (A), using the FIFO provided inside the FPGA to buffer the input TS stream, and use a 27MHZ high clock as the readout clock of the FIFO to read out the TS stream to increase the speed for subsequent processing; [2] Synchronization header detection, extracting the implicit synchronization signal in the input TS stream, processing the TS stream into a series of continuous TS packets and outputting them in two ways, one for PCR detection, and the other for PCR insertion module Complete the modification of PCR information; [3] PCR detection, extract the PCR value in the TS stream, and output it to the addition and subtraction operator; [4] The subtractor performs subtraction operation on the PCR value extracted from the TS stream and the count generated by the counter whose reference clock is 27MHZ, and sends the result as a new PCR value; [5] PCR insertion, detect the input TS stream signal in units of packets, remove the PCR value in the TS stream PCR field, and then insert the new input PCR value into the PCR field in the TS stream, and obtain the modified PCR information TS stream and output; [6] Internal FIFO (B), using the FIFO provided inside the FPGA, buffers the input TS stream, and uses the input clock generated by the NCO circuit as the read clock of the FIFO to read the TS stream and match the FIFO when it is full The signals are sent to the empty packet generator together; [7] Empty packet generator, which outputs a data stream with empty information conforming to the TS packet format; [8] Empty packet insertion, when the half-full signal of the internal FIFO (B) is valid, the input TS stream is output in packets, otherwise an empty packet is output; [9] Internal FIFO (C), use the FIFO provided by the FPGA to cache the input new TS stream, and divide the output signal into two paths: one path enters the PCR expansion module to extract PCR information; the other path is transmitted to the PCR insertion module, Complete the modification of PCR information; [10] Adder, the PCR value that extracts and the reference clock are that the numerical value that the counter of 27MHZ produces is done addition operation, and the result is sent as new PCR value; [11] The counter uses the reference clock 27MHZ as the counting clock, and the resulting count is input into the adder and subtractor to adjust the PCR value.

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