CN1664685A - Manufacturing method of array substrate and thin film transistor array panel - Google Patents

Abstract

The invention relates to a manufacturing method of an array substrate, which comprises the following steps: forming a first metal layer on a substrate; performing a first photolithography process to pattern the first metal layer, forming a gate wire, a gate electrode connected to the gate wire, and a pad on the substrate; forming an insulating layer, a semiconductor layer and an ohmic contact layer on the substrate to cover the gate wire, the gate electrode and the pad; and performing a second photolithography process to pattern the ohmic contact layer, the semiconductor layer and a portion of the insulating layer, forming a semiconductor structure on the substrate and forming a via hole in the insulating layer on the pad to expose a portion of the pad, wherein the semiconductor structure comprises the insulating layer substantially covering the gate electrode, the patterned semiconductor layer and the patterned ohmic contact layer.

Description

Manufacturing method of array substrate and thin film transistor array panel

technical field

The invention relates to the manufacture of a display device, in particular to a method for manufacturing a thin film transistor array substrate.

Background technique

In order to realize high-speed image processing and high-quality display images, flat panel displays such as color liquid crystal display devices have been widely used in recent years. In a liquid crystal display device, it usually includes two upper and lower substrates with electrodes, which are bonded together by adhesive or sealing material. The liquid crystal material is filled between the two substrates, and in order to maintain a fixed distance between the two plates, particles with a certain particle size are dispersed between the two plates. Usually, a thin film transistor used as a switching element is formed on the surface of the lower substrate. The thin film transistor has a gate electrode connected to a scanning line and a drain electrode connected to a signal line. electrode), and the source electrode (source electrode) connected to the pixel electrode (pixelelectrode). The upper substrate is placed above the lower substrate, and a light filter and a plurality of light-shielding materials (such as chrome) are formed on the surface of the upper substrate. The peripheries of the two substrates are bonded and fixed by sealing material, and there is a liquid crystal material between the two substrates. The lower substrate is also referred to as an array substrate, and a plurality of elements formed thereon are usually fabricated by multi-pass photolithography processes. The number of times the photolithography process is used is closely related to the manufacturing cost and production time of the array substrate.

FIGS. 1A-1F are a series of schematic diagrams illustrating an array substrate process using six photolithography processes in the prior art to illustrate cross-sectional situations at each process stage. In this paper, each photolithography process includes resist coating, using a patterned photomask, resist exposure, resist development, film layer etching, and removing residual resist, etc., which are well known to those skilled in the art. The related steps of engraving are collectively referred to as "lithography process" here.

Referring to FIG. 1A , firstly, a first photolithography process is applied to define a metal layer formed on a substrate 104 to form a patterned gate 100 and wires 102 for TFT devices. The wire 102 can be used as a gate line (or scan line) or a data line (or signal line), which is formed on the substrate 104 in a continuous manner.

Referring to FIG. 1B, an insulating layer 106, a semiconductor layer 108, and an ohmic contact layer 110 are formed on the substrate 104, and a second photolithography process is applied to define a pattern on the insulating layer 106 above the gate 100. Thinned semiconductor layer 108 and ohmic contact layer 110.

Referring to FIG. 1C , a third photolithography process is then used to selectively form a via hole 112 penetrating through the insulating layer 106 on each corresponding wire 102 .

Referring to FIG. 1D , another metal layer is formed on the substrate 104 and then a fourth photolithography process is used to form a patterned conductive layer 114 located on the wire 102 and adjacent to the gate 100 . In the fourth photolithography process, the metal layer 114 adjacent to the gate 100 , the ohmic contact layer 110 and part of the semiconductor layer 108 are etched simultaneously to form the notch 116 . In this way, it is convenient to complete the fabrication of the thin film transistor on the substrate 104

Please refer to FIG. 1E, then cover a protective layer 118 on the icon structure in FIG. Contact areas in place.

Referring to FIG. 1F, a transparent conductive layer 122 is then covered in the protective layer 118 and the via hole 120, and a patterned transparent conductive layer 122 is formed on the protective layer 118 through the use of the sixth photolithography process, so as to Used as a pixel electrode. In this way, the fabrication of the array substrate comes to an end.

Generally speaking, the wires used as the scan lines and the signal lines existing on the surface of the substrate 104 are composed of a continuous single conductive layer. As the size of the liquid crystal display device increases, the lengths of the scan lines and the signal lines formed by the continuous conductive layer also increase accordingly, thus increasing the resistance of the scan lines and the signal lines. Such an increase in impedance may cause signal loss on these lines during the operation of the liquid crystal display device, which is not conducive to the manufacture of large-size liquid crystal display devices. In the active matrix substrate process as shown in FIGS. 1A˜1F , a conductive layer 114 is additionally formed on the wire 102 , so as to form a wire with a thicker thickness. In this way, the overall impedance of the wire can be reduced, and the signal loss on the wire can be improved. However, the above process requires six photolithography processes, which makes the fabrication of the array substrate time-consuming. Thus, there is a need for an array substrate process that is simpler in process and suitable for large-scale flat panel display devices.

Contents of the invention

The main purpose of the present invention is to provide a method for manufacturing a display device using relatively few photolithography steps, so as to save manufacturing cost and production time during manufacturing.

According to the above purpose, the present invention provides a method for manufacturing an array substrate, comprising the following steps:

forming a first metal layer on a substrate; performing a first photolithography process to pattern the first metal layer, forming a gate wire, a gate electrode connected to the gate wire, and a pad on the substrate forming an insulating layer, a semiconductor layer and an ohmic contact layer on the substrate, covering the gate wire, the gate electrode and the pad; and performing a second photolithography process to pattern the ohmic contact layer , the semiconductor layer and part of the insulating layer, forming a semiconductor structure on the substrate and forming a via hole in the insulating layer on the pad to expose part of the pad, wherein the semiconductor structure includes a substantially covered The insulating layer on the gate electrode, the patterned semiconductor layer and the patterned ohmic contact layer.

According to the above purpose, the present invention provides a method for manufacturing a thin film transistor array panel, comprising the following steps:

forming a first metal layer on a substrate; performing a first photolithography process to pattern the first metal layer, forming on the substrate at least one gate wire extending continuously along a first direction, and extending along a second A plurality of data wire segments extending in a direction, wherein the first direction is different from the second direction and the data wire segments and the gate wires are separated from each other at intersections; forming an insulating layer, a semiconductor layer and an ohmic The contact layer is on the substrate; a second photolithography process is performed to pattern the ohmic contact layer, the semiconductor layer and the insulating layer to form a plurality of semiconductor structures and a plurality of stack structures, and the stack structures span the data wire segments and the gate wires at intersections; forming a second metal layer on the substrate; performing a third photolithography process to pattern the second conductive metal layer to form a plurality of sources on the semiconductor structures electrode/drain electrodes and forming a plurality of continuous data wires extending on the bridging structures and electrically connecting the data wire segments; forming a protection layer on the substrate; performing a fourth photolithography process to pattern the protection layer, forming a plurality of via holes and exposing a plurality of contact pads of the data wires and the gate wires and one of the source/drain electrodes; and forming a transparent conductive layer on the substrate, and filling in the via holes; performing a fifth photolithography process to pattern the transparent conductive layer to form a plurality of pixel electrodes and storage capacitors, wherein the storage capacitors are partially overlapped on the gate wires.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the present invention will be described in more detail below with reference to the accompanying drawings and preferred embodiments.

Description of drawings

FIGS. 1A-1F are a series of schematic diagrams illustrating an array substrate process using six photolithography processes in the prior art to illustrate cross-sectional situations at each process stage.

FIGS. 2A , 3A, 4A, 5A and 6A are a series of schematic diagrams illustrating the top view of the manufacturing process of the active matrix substrate according to an embodiment of the present invention.

2B, 3B, 4B, 5B, and 6B are cross-sectional views illustrating the fabrication process of an array substrate according to an embodiment of the present invention, respectively showing 2B-2B, 3B-3B, and 4B in FIGS. 2A, 3A, 4A, 5A, and 6A. - Sections of line segments 4B, 5B-5B and 6B-6B.

2C, 3C, 4C, 5C, and 6C are cross-sectional views illustrating the fabrication process of an array substrate according to an embodiment of the present invention, respectively showing 2C-2C, 3C-3C, and 4C in FIGS. 2A, 3A, 4A, 5A, and 6A. Sections of -4C, 5C-5C, 6C-6C line segments.

FIGS. 3D to 3G are cross-sectional views of the manufacturing process of the array substrate according to an embodiment of the present invention, respectively showing the manufacturing process of the second photolithography process used in FIGS. 3A to 3C .

7A and 8A are top views illustrating the manufacturing process of an active matrix substrate according to another embodiment of the present invention.

7B and 8B are cross-sectional views of the fabrication process of the array substrate according to an embodiment of the present invention, respectively showing the cross-sections of the line segments 7B-7B and 8B-8B in FIG. 7A and FIG. 8A .

7C and 8C are cross-sectional views of the manufacturing process of the array substrate according to an embodiment of the present invention, respectively showing the cross-sections of the line segments 7C-7C and 8C-8C in FIGS. 7A and 8A .

FIGS. 7D to 7G are cross-sectional views of the manufacturing process of the array substrate according to another embodiment of the present invention, respectively showing the manufacturing process of the second photolithography and etching processes used in FIGS. 7A to 7C . simple notation

100～grid; 102～wire;

104, 204～substrate; 106, 300～insulation layer;

108, 302～semiconductor layer; 110, 304～ohmic contact layer;

112, 120～via hole; 114～conductive layer;

116～notch; 118～protective layer;

122～transparent conductive layer;

200, 700～thin film transistor array panel;

202～gate wire; 202a～gate electrode;

202b, 206b～pad; 206a～data wire segment;

208～the first notch; 210～the second notch;

306, 308～stack structure; 320～photoresist layer;

340, 304'～photomask; 340a～opaque area;

340b～translucent area; 340c～partially transparent area;

350, 360, 370～etching procedure; H1, H2～thickness of photoresist layer;

400, 402, 404, 406, 408, 410～metal layer;

308, 310, 312, 412～opening;

500～protective layer; 502, 504, 506～interposition hole;

600, 602, 604-transparent conductive layer.

Detailed ways

2 to 6 are a series of schematic diagrams illustrating the array substrate process according to an embodiment of the present invention to illustrate the manufacturing situation at each process stage, wherein FIGS. 2A, 3A, 4A, 5A, and 6A show a top view respectively. 2B-2C, 3B-3C, 4B-4C, 5B-5C, and 6B-6C respectively show the cross-sections corresponding to the B-B and C-C lines in the upper view. Each photolithography process described here includes resist coating, using a patterned photomask, resist exposure, resist development, film layer etching, and removal of residual resist, etc., which are well known to those skilled in the art. Each photolithography process can be performed by standard photolithography equipment commonly used in the industry, and the above process steps are collectively referred to as "photolithography process" hereinafter.

Please refer to FIG. 2A , which partially shows a top view of a TFT array panel 200 . The thin film transistor array panel 200 includes a substrate 204 on which a plurality of wires, such as gate wires 202 are disposed. In addition, a plurality of wire segments, such as the data wire segment 206a, are also disposed on the substrate 204 . The gate wire 202 and the data wire segment 206a include metal or other conductive materials, and are arranged in a specific pattern formed in the row and column directions shown in FIG. The arrangement is limited. Here, its pattern is formed through the first photolithography process.

In the first photolithography process, a metal layer formed and covered on the substrate 204 is defined and the gate wires 202 and the data wire segments 206 a are formed at the same time, which are generally arranged in a column direction. In addition, in this first photolithography process, other components are also formed on the substrate, such as a plurality of gate electrodes 202a connected to each gate wire 202, which are generally arranged in a row, as the structure of each thin film transistor device. For the gate electrode. In addition, a large-area pad 202 b connected to the gate wire 202 and a large-area pad 206 b connected to the data wire segment 206 are also formed for circuit connection.

As shown in FIG. 2A , a first notch 208 is formed at the intersection area of the data wire segment 206 a and the gate wire 202 to separate the data wire segment 206 a from the adjacent gate wire 202 . In addition, the gate electrode 202a is separated from the adjacent data wire segment 206a by the second notch 210 .

Please refer to FIG. 2B, which shows the cross-sectional situation of the 2B-2B line segment in FIG. 2A, wherein a gate wire 202, a gate electrode 202a for a thin film transistor device, and a segment between the gate electrode 202a and the adjacent data wire segment ( (not shown) the second notch 210 between. The thickness of the gate wire 202 and the gate electrode 202a is about 1500˜5000 angstroms, and its material is such as aluminum (Al), molybdenum (Mo), chromium (Cr), aluminum alloy (Al alloy) and other metal materials, and such as molybdenum With aluminum ruthenium (Mo/AlNd or AlNd/Mo), molybdenum and aluminum (Mo/Al), titanium and aluminum ruthenium (Ti/AlNd or AlNd/Ti), titanium and aluminum (Ti/Al or Ti/Al/Ti) , a composite metal formed of chromium and aluminum (Cr/Al), chromium and aluminum ruthenium (Cr/AlNd or AlNd/Cr), or other metal materials. 2C shows the cross-section of line segment 2C-2C in FIG. 2A , where the substrate 204 is formed with a data conductor segment 206a and a gate conductor 202 separated by a first notch 208, and a gate conductor 202 connected to the gate conductor 202. pad 202b. The thickness of the data wire segment 206a, the gate wire 202 and the contact pad 202b is about 1500-5000 angstroms, and the materials thereof are such as aluminum, molybdenum, chromium, aluminum alloy and other metal materials, and such as molybdenum and aluminum ruthenium ( Mo/AlNd or AlNd/Mo), molybdenum and aluminum (Mo/Al), titanium and aluminum ruthenium (Ti/AlNd or AlNd/Ti), titanium and aluminum (Ti/Al or Ti/Al/Ti), chromium and aluminum (Cr/Al), chromium and aluminum ruthenium (Cr/AlNd or AlNd/Cr) composite materials or other metal materials.

Please refer to FIG. 3A, which partially shows the top-view situation after forming a patterned insulating layer 300, a semiconductor layer 302, and an ohmic contact layer 304 on the thin film transistor array panel 200 in FIG. 2A. These patterned film layers Simultaneously formed by the second photolithography process. Wherein, the insulating layer 300 is formed on the gate electrode 202a and a part of the gate wire 202 adjacent to the gate electrode 202a, the data wire 206a and the substrate 204, and fills the first recess 208 between these components (see FIG. 3B for details. ) and the second notch 210 (see FIG. 3C for details). Here, the ohmic contact layer 304 is shown as an inverted L-shaped pattern and substantially covers the semiconductor layer 302, so the semiconductor layer 302 is not shown in FIG. 3A.

Please refer to FIG. 3B and FIG. 3C at the same time, which respectively show the cross-sections of the 3B-3B and 3C-3C line segments in FIG. Formed and stacked on the substrate 204, through the implementation of the second photolithography process, a photomask with different light-transmitting regions and a single photolithography are used to form on the ohmic contact layer 304. The case for various photoresist thicknesses. And through subsequent three consecutive etching procedures, the stacked structures 306 and 308 respectively stacked adjacent to the gate electrode 202 a, the first notch 208 and its adjacent substrate 204 as shown in FIG. 3B and FIG. 3C are defined. Wherein, the materials of the insulating layer 300, the semiconductor layer 302 and the ohmic contact layer 304 are, for example, silicon nitride or silicon oxynitride (SiO _x N _y ), α-Si:H material and n ⁺ α-Si:H material, respectively, and The thickness thereof is, for example, 2000˜5000 Å, 1000˜3000 Å, and 100˜1000 Å, respectively.

In this second photolithography process, the insulating layer 300 and the semiconductor layer 302 in the stacked structures 306 and 308 formed near the substrate 204 corresponding to the first notches 208 and the second notches 210 are formed simultaneously. A dielectric barrier is used to avoid electrical connection and short circuit between the adjacent gate wire 202 and the data wire segment 206 a and/or the adjacent data wire segment 206 a and the gate wire 202 . FIG. 3B shows a stack structure 306 composed of a patterned insulating layer 300, a semiconductor layer 302, and an ohmic contact layer 304 filled in the second cavity 210, while FIG. The stack structure 308 formed by the patterned insulating layer 300 , the semiconductor layer 302 and the ohmic contact layer 304 in the opening 208 .

Here, the photomask used in the second photolithography process and the subsequent etching process will be described in detail below with reference to FIGS. 3D-3G . Please refer to FIG. 3D, which only illustrates the manufacturing situation in the region adjacent to the gate electrode 202a and the contact pad 202b in the second photolithography process. Those skilled in the art should be able to understand the present invention, and can according to the actual Designed for use in manufacturing in other areas. First, a substrate 204 is provided, on which gate electrodes 202a and pads 202b are formed. The gate electrode 202 a and the pad 202 b are then covered by the gate insulating layer 300 , the semiconductor layer 302 , and the ohmic contact layer 304 sequentially formed on the substrate 204 . Then, a photoresist layer 320 is coated on the substrate 304, and a second photolithography process is performed by standard photolithography equipment commonly used in the industry, using a photomask 340 as shown in FIG. 3D. Here, the photomask 340 includes regions with different light transmittances, such as an opaque region 340a, a transparent region 340b, and a partially transparent region 340c. Wherein, the light transmittance of the opaque region 340a is 0%, and it is generally aligned above the gate electrode 202a, while the light transmittance of the light-transmitting region 340 is 100%, and it is generally aligned above the pad 202b. The light transmittance of the transparent area 340c is about 20-80%, and it is generally aligned with other specific areas. After performing the second photolithography process, through a single exposure process, and after developing the photoresist, the situation as shown in FIG. 3D is formed. The patterned photoresist layer 320 remains only on the gate electrode 202 a and its adjacent ohmic contact layer 204 . Due to the different factors of light transmittance in different regions, the photoresist layer 320 located under the transparent region 340b will be removed by development due to complete exposure, while the photoresist layer 320 located under the opaque region 340a and the partially transparent region 304c will The photoresist layer 320 will leave a photoresist layer 320 with different thicknesses after development due to no exposure or only partial exposure, wherein the photoresist layer under the opaque region 340a The resist layer 320 has a thickness H1 of about 15000˜30000 Å, and the photoresist layer 320 under the partially transparent region 304 c has a thickness H2 of about 3000˜20000 Å.

Please refer to FIG. 3E, and then perform an etching process 350, for example, use a dry etching process (please supplement) including sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), or other suitable reactive gases, by photoinduced The resist layer 320 is used as an etching protection layer to etch away the ohmic contact layer 304 , the semiconductor layer 302 and the insulating layer 300 not protected by the photoresist layer, and the etching stops at the substrate 204 and the pad 202 b.

Referring to FIG. 3F, another etching process 360 is then performed, for example, a dry etching process (please supplement) using oxygen (O ₂ ), sulfur hexafluoride and oxygen (SF ₆ /O ₂ ), or other appropriate reactive gases, The photoresist layer 320 is etched to expose a portion of the ohmic contact layer 304 adjacent to the gate electrode 202a. At this time, the photoresist layer 320 still remains in the area above the gate electrode 202a.

Referring to FIG. 3G, another etching process 370 is then performed, for example, using chlorine gas (Cl ₂ ), sulfur hexafluoride and chlorine gas (SF ₆ /Cl ₂ ), chlorine gas and boron trichloride (Cl ₂ /BCl ₃ ), The dry etching procedure of carbon tetrafluoride (CF ₄ ) or other reactive gases (please supplement) to etch the ohmic contact layer 304 and the semiconductor layer 302 below it that is not covered by the photoresist layer 320, and stop at the insulating layer on layer 300. Furthermore, a stack structure 360 and pads 202b as shown in FIG. 3B are formed.

Please refer to FIG. 4A, which partially shows the top-view situation after forming patterned metal layers 400, 402, 404, 406, 408, 410 and openings 412 on the thin film transistor array panel 200 in FIG. 3A. The metal layer is simultaneously formed through the third photolithography process. The metal layers 400 and 402 generally cover the data wire segments 206a (not shown), the ohmic contact layer 304 formed between the data wire segments 206a and the pads 206b (not shown) along the row direction, and connect the underlying The data wire segment 206a forms a data wire. The data wires with such a structure can have lower resistance than the traditional continuous data wires, and are more suitable for large-sized display devices, so as to reduce the signal loss on the wires. The metal layers 404 and 406 substantially cover part of the gate wire 202a (not shown) and the adjacent insulating layer 300 and the pad 202b along the column direction respectively. The metal layer 408 covers part of the substrate 204 , the insulating layer 300 and the ohmic contact layer 304 , and the metal layer 410 covers the ohmic contact layer 304 and is connected to the metal layer 400 . In the third photolithography process, an opening 412 exposing the semiconductor layer 302 is formed by etching through the ohmic contact layer 304 above the middle portion of the gate electrode 202 a and part of the semiconductor layer 302 .

Here, the metal layers 400, 402, 404, 406 are partially overlapped and directly connected to the previously formed gate wire 202, the data wire segment 206a, and the pads 202a and 202b, thus increasing part of the data wire 202 and the data wire segment 206a. thickness of. The thickness of these metal layers is about 2000˜4000 angstroms, and the material thereof is aluminum (Al), molybdenum (Mo), chromium (Cr) or other metal materials.

Please refer to FIG. 4B and FIG. 4C at the same time, respectively showing the cross-sections of the line segments 4B-4B and 4C-4C in FIG. 4A . 4B shows the patterned metal layers 408 and 410 separated by the opening 412 formed at the stack structure 306 in the third photolithography process. The opening 412 exposes the semiconductor layer 302 therein, and thus defines the source/drain regions of the TFT. So far, the stack structure 306 can be used as a thin film transistor, and the metal layers 408 and 410 formed directly on the ohmic contact layer 302 can be used as source/drain electrodes, wherein the metal layer 408 can be further extended to part of the substrate 204, and the metal layer 410 extends at the second notch 210 and is further connected to its adjacent metal layer 400 (not shown).

4B and FIG. 4C, the metal layers 400, 404 and 406 increase the thickness of the data wire segment 206a, the gate wire 200 and the pad 202b, which are discontinuously formed at the intersecting region and separated from each other to prevent short circuit conditions from occurring.

Please refer to FIG. 5A, which partially shows the top view after forming a patterned protective layer 500 on the thin film transistor array panel 200 in FIG. Vias 502, 504, and 506 are formed to expose portions of metal layers 402, 406, and 408, respectively. The thickness of the protection layer 500 is about 1000˜50000 angstroms, such as silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), organic materials or other materials.

Please refer to FIG. 5B and FIG. 5C at the same time, respectively showing the cross-sections of the line segments 5B-5B and 5C-5C in FIG. 5A . Wherein, the protective layer 500 is formed on the substrate 204 and covers the previously formed structure, and the via holes 502 and 504 are defined by the fourth photolithographic etching. The openings 502 and 504 respectively expose portions of the metal layers 408 and 406 .

Please refer to FIG. 6A, which partially shows the top view after forming a patterned transparent conductive layer 600, 602, and 604 on the thin film transistor array panel 200 in FIG. 5A, which is formed by the fifth photolithography process. The transparent conductive layer 600 is formed in the display area defined by the data wires and the gate wires, and is connected to the underlying metal layer 408 through the opening 506 to transfer current from the metal layer 408 therein. The transparent conductive layers 602 and 604 are electrically connected to the underlying metal layers 402 and 406 through the openings 502 and 504 respectively. The material of the transparent conductive layers 600, 602 and 604 is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), and the thickness thereof is about 400˜2000 angstroms. Here, the part of the transparent conductive layer 600 covering the passivation layer 500 can be used as a pixel electrode, and the part of the transparent conductive layer 600 covering the gate wire 204 can be used as a storage capacitor component. 6B and 6C respectively show the cross-sections of the line segments 6B-6B and 6C-6C in FIG. 6A . The transparent conductive layers 600 and 604 form electrical connections with the underlying metal layers 408 and 406 through the openings 502 and 504 respectively.

7 to 8 are a series of schematic diagrams illustrating the array substrate process according to another embodiment of the present invention. The process steps of the manufacturing situation in the process stage are generally similar to the previous embodiment, and only the two embodiments are shown here. For the difference, Fig. 7A and Fig. 8A respectively show a top-view situation, while Fig. 7B-7C and 8B-8C respectively show the cross-sectional situation corresponding to the B-B and C-C line segments in the top view.

Please refer to FIG. 7A , which partially shows a top view after forming a patterned gate insulating layer 300 , semiconductor layer 302 and ohmic contact layer 304 on a TFT array panel 700 . Before these film layers are formed, the thin film transistor array panel 700 is formed with the same structure as the thin film crystal array panel 200 in FIG. 2A , and these patterned film layers are formed simultaneously through a second photolithography process. Wherein, compared with FIG. 3A , the gate insulating layer 300 covers the entire substrate 204 (not shown), and fills the first notch 208 (see FIG. 7B ) and the first notch between these components. Two notches 210 (see FIG. 7C for details). The inverted L-shaped ohmic contact layer 304 is formed on the gate insulating layer 300 and generally covers the gate electrode 202a and the adjacent data wire segment 206a. Openings 308 , 310 and 312 are formed in the gate insulating layer 300 to expose part of the gate wire 202 and the pads 202 b and 206 b respectively. 7B and 7C respectively show the cross-sections of the line segments 7B-7B and 7C-7C in FIG. 7A, wherein the materials for forming the gate insulating layer 300, the semiconductor layer 302 and the ohmic contact layer 304 are first formed sequentially and covertly. And stacked on the substrate 204, through the implementation of the second photolithography process, a single photomask with different light-transmitting regions and a single photolithography are used to form a variety of photoresist on the ohmic contact layer 304. The thickness of the etchant. And through subsequent three consecutive etching procedures, the stacked structures 306 and 308 respectively stacked adjacent to the gate electrode 202a, the first notch 208 and adjacent to the gate insulating layer 204 as shown in FIG. 7B and FIG. 7C are defined. Wherein, the materials of the gate insulating layer 300, the semiconductor layer 302 and the ohmic contact layer 304 are, for example, silicon nitride, α-Si:H material, and n ⁺ α-Si:H material, respectively, and their thicknesses are, for example, 2000˜5000 A respectively. Angstroms, 1000-3000 Angstroms, and 100-1000 Angstroms.

Here, the photomask used in the second photolithography process and the subsequent etching process will be described in detail below with reference to FIGS. 7D-7G . Please refer to FIG. 7D, which only illustrates the manufacturing situation in the region adjacent to the gate electrode 202a and the pad 202b in the second photolithography process. Those skilled in the art should be able to understand the present invention, and can according to the actual Designed for use in manufacturing in other areas. First, a substrate 204 is provided, on which gate electrodes 202a and pads 202b are formed. The gate electrode 202 a and the pad 202 b are then covered by the gate insulating layer 300 , the semiconductor layer 304 , and the ohmic contact layer 306 sequentially formed on the substrate 204 . Then, a photoresist layer 320 is coated on the substrate 304, and a second photolithography process is performed by standard photolithography equipment commonly used in the industry, using a photomask 340' as shown in FIG. 7D. Here, the photomask 340' includes regions with different light transmittances such as an opaque region 340a, a transparent region 340b, and a partially transparent region 340c. The light transmittance of the opaque region 340a is 0%, and it is generally aligned above the gate electrode 202a, while the light transmittance of the light transmissive region 340 is 100%, and it is generally aligned above a part of the pad 202b. The light transmittance of the partially transparent area 340c is about 20-80%, which is generally aligned with other specific areas. After the second photolithography process is performed, a single exposure procedure is performed, and after the photoresist is developed, a situation as shown in FIG. 7D is formed. An opening 310 is formed in the photoresist layer 320 formed above the pad 202b, exposing the ohmic contact layer 304 therein. Due to the different factors of light transmittance in different regions, the photoresist layer 320 located under the transparent region 340b will be removed by development due to complete exposure, while the photoresist layer 320 located under the opaque region 340a and the partially transparent region 304c will The photoresist layer 320 will leave a photoresist layer 320 with different thicknesses after development due to no exposure or only partial exposure, wherein the photoresist layer under the opaque region 340a The resist layer 320 has a thickness H1 of about 15000-30000 angstroms, and the photoresist layer 320 under the semi-transparent region 304c has a thickness H2 of about 3000-15000 angstroms.

Please refer to FIG. 7E, and then perform an etching process 350, for example, use a dry etching process (please supplement) including sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), or other suitable reactive gases, through photoinduced The resist layer 320 is used as an etching protection layer to etch away the ohmic contact layer 304 , the semiconductor layer 302 and the gate insulating layer 300 exposed in the opening 310 , and stop on the pad 202 b.

Referring to FIG. 7F, another etching process 360 is then performed, for example, a dry etching process (please supplement) using oxygen (O ₂ ), sulfur hexafluoride and oxygen (SF ₆ /O ₂ ), or other appropriate reactive gases, The photoresist layer 320 is etched back to expose the ohmic contact layer 304 . At this time, the photoresist layer 320 remains only in the area above the gate electrode 202 a and covers a part of the adjacent ohmic contact layer 304 .

Referring to FIG. 7G, another etching process 370 is then performed, for example, using chlorine gas (Cl ₂ ), sulfur hexafluoride and chlorine gas (SF ₆ /Cl ₂ ), boron trichloride and chlorine gas (BCl ₃ /Cl ₂ ), Carbon tetrafluoride (CF ₄ ) or other reactive gas dry etching process (please supplement), to etch the ohmic contact layer 304 and the semiconductor layer 302 below it not covered by the photoresist layer 320, and stop at the gate on the insulating layer 300. Further, a stack structure 360 and pads 202b as shown in FIG. 7B are formed. Compared with the aforementioned prior art in FIGS. 1A-1F , two photolithography processes are required to fabricate structures such as pads 202b and stacked structures 306 as shown in FIG. 7G . The second photolithography process used in the present invention process, which saves the use of a photomask, and has the effect of saving manufacturing cost and photolithography process.

Subsequent processes are then carried out, such as the processes shown in FIGS. 4-6 , and finally a TFT array panel 700 with patterned transparent conductive layers 600 , 602 and 604 formed on the substrate as shown in FIG. 8 is formed. FIG. 8B and FIG. 8C respectively show the cross-sections of the line segments 8B-8B and 8C-8C in FIG. 8A , and the cross-sectional structures are generally the same as those in FIG. 6B and FIG. 6C .

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention It shall prevail as defined in the appended claims.

Claims (23)

1. A method for manufacturing an array substrate, comprising the following steps: forming a first metal layer on a substrate; performing a first photolithography process to pattern the first metal layer, forming a gate wire, a gate electrode connected to the gate wire, and a pad on the substrate; forming an insulating layer, a semiconductor layer and an ohmic contact layer on the substrate, covering the gate wire, the gate electrode and the pad; and performing a second photolithography process to pattern the ohmic contact layer, the semiconductor layer and part of the insulating layer, forming a semiconductor structure on the substrate and forming a via hole in the insulating layer on the pad to expose A part of the contact pad, wherein the semiconductor structure includes the insulating layer substantially covering the gate electrode, the patterned semiconductor layer and the patterned ohmic contact layer. 2. The method for manufacturing an array substrate according to claim 1, further comprising the following steps: forming a second metal layer on the substrate, covering the semiconductor structure and filling the via hole to electrically connect to the pad; and performing a third photolithography process to pattern the second metal layer and pattern the ohmic contact layer and semiconductor layer located in a middle portion of the semiconductor structure to define two source/drain regions and a second metal layer on the source/drain regions and the pad. 3. The method for manufacturing an array substrate as claimed in claim 1, wherein the second photolithography process comprises the following steps: forming a photoresist layer on the ohmic contact layer; performing a photolithography process to pattern the photoresist layer using a photomask having an opaque region, a transmissive region and a portion of the transmissive region, the photoresist layer substantially corresponding to the transmissive region forming an opening in the resist layer and exposing a part of the ohmic contact layer; forming a first photoresist layer with a first thickness in the photoresist layer substantially aligned with the opaque region; A second photoresist layer of a second thickness is formed in the photoresist layer substantially aligned with the semi-transparent layer, wherein the first thickness is greater than the second thickness, and the light-transmitting region is substantially aligned with the a pad, the opaque area is generally aligned with the grid electrode, and the part of the light-transmitting area is generally aligned with the pad and other areas outside the grid electrode; performing a first etching process, using the first photoresist layer and the second photoresist layer as etching masks, etching and removing the ohmic contact layer exposed by the opening and the semiconductor thereunder layer and the insulating layer, and stop at the pad; performing a second etching process to etch the first photoresist layer and the second photoresist layer, leaving only the first photoresist layer substantially covering the gate electrode and thin In other words, the ohmic contact layer not covered by the first photoresist layer is exposed; performing a third etching process to etch the ohmic contact layer and the underlying semiconductor layer not covered by the first photoresist layer; and removing the first photoresist layer to form a semiconductor structure on the substrate and the contact pad exposed by the opening, wherein the semiconductor structure includes the insulating layer substantially covering the gate electrode, a patterned A semiconductor layer and a patterned ohmic contact layer. 4. The method for manufacturing a thin array substrate as claimed in claim 3, wherein the first thickness is between 15000-30000 angstroms, and the second thickness is between 3000-20000 angstroms. 5. The method of manufacturing the array substrate as claimed in claim 1, wherein the insulating layer comprises silicon nitride or silicon oxynitride (SiO _{X NY} ). 6. The method of manufacturing the array substrate as claimed in claim 1, wherein the semiconductor layer comprises α-Si:H material. 7. The method of manufacturing an array substrate as claimed in claim 1, wherein the ohmic contact layer comprises n ⁺ α-Si:H material. 8. The method for manufacturing an array substrate as claimed in claim 3, wherein the first etching process is dry etching using a reactive gas including sulfur hexafluoride (SF ₆ ) or carbon tetrafluoride (CF ₄ ). 9. The method for manufacturing an array substrate as claimed in claim 3, wherein the second etching process is dry etching, and the reaction gas used includes sulfur hexafluoride and oxygen (SF ₆ /O ₂ ) or oxygen (O ₂ ) . 10. The method for manufacturing an array substrate as claimed in claim 3, wherein the third etching procedure is dry etching, and the reaction gases used include chlorine gas (Cl ₂ ), sulfur hexafluoride and chlorine gas (SF ₆ /Cl ₂ ) , boron trichloride and chlorine (BCl ₃ /Cl ₂ ) or carbon tetrafluoride (CF ₄ ). 11. The method for manufacturing an array substrate as claimed in claim 3, wherein the partially light-transmitting region has a light transmittance between 20% and 80%. 12. The manufacturing method of the array substrate as claimed in claim 3, wherein the opaque area has a light transmittance of approximately 0% and the light transmittance area has a light transmittance of approximately 100%. 13. A method for manufacturing a thin film transistor array panel, comprising the following steps: forming a first metal layer on a substrate; performing a first photolithography process to pattern the first metal layer, forming at least one gate wire extending continuously along a first direction and a plurality of data wire segments extending along a second direction on the substrate, wherein the The first direction is different from the second direction and the data wire segments and the gate wires are separated from each other at intersections; forming an insulating layer, a semiconductor layer and an ohmic contact layer on the substrate; performing a second photolithography process to pattern the ohmic contact layer, the semiconductor layer and the insulating layer to form a plurality of semiconductor structures and a plurality of stacked structures, and the stacked structures straddle the data wire segments and the gates conductors at junctions; forming a second metal layer on the substrate; performing a third photolithography process to pattern the second conductive metal layer, forming a plurality of source/drain electrodes on the semiconductor structures and forming the bridge structures extending on the bridge structures and electrically connecting the data wire segments a plurality of continuous data conductors; forming a protection layer on the substrate; performing a fourth photolithography process to pattern the protection layer, forming a plurality of via holes and exposing a plurality of contact pads of the data wires and the gate wires and one of the source/drain electrodes; as well as forming a transparent conductive layer on the substrate, and filling the via holes; A fifth photolithography process is performed to pattern the transparent conductive layer to form a plurality of pixel electrodes and storage capacitors, wherein the storage capacitors are partially overlapped on the gate wires. 14. The method for manufacturing a thin film transistor array panel as claimed in claim 13, wherein the second photolithography process comprises the following steps: forming a photoresist material on the ohmic contact layer; performing a photolithography process to pattern the photoresist material using a photomask having an opaque region, a transmissive region and a portion of the transmissive region, in the photoresist substantially corresponding to the transmissive region forming an opening in the resist layer and exposing a part of the ohmic contact layer; forming a first photoresist layer with a first thickness in the photoresist layer substantially aligned with the opaque region; A second photoresist layer of a second thickness is formed in the photoresist layer substantially aligned with the semi-transparent layer, wherein the first thickness is greater than the second thickness, and the light-transmitting region is substantially aligned with the A contact pad of some gate wires and data wires, the opaque area is generally aligned with the gate electrode, and the part of the light-transmissive area is generally aligned with the pad and other areas outside the gate electrode; performing a first etching process, using the first photoresist layer and the second photoresist layer as etching masks, etching and removing the ohmic contact layer exposed by the opening and the semiconductor thereunder layer and the insulating layer, and stop at the pad; performing a second etching process to etch the first photoresist layer and the second photoresist layer, leaving only the first photoresist layer substantially covering the gate electrode and thin In other words, the ohmic contact layer not covered by the first photoresist layer is exposed; performing a third etching process to etch the ohmic contact layer and the underlying semiconductor layer not covered by the first photoresist layer; and removing the first photoresist layer to form a semiconductor structure on the substrate and the contact pad exposed by the opening, wherein the semiconductor structure includes the insulating layer substantially covering the gate electrode, a patterned A semiconductor layer and a patterned ohmic contact layer. 15. The method for manufacturing a thin film transistor array panel as claimed in claim 14, wherein the first thickness is between 15000-30000 angstroms, and the second thickness is between 3000-20000 angstroms. 16. The method of manufacturing a thin film transistor array panel as claimed in claim 13, wherein the insulating layer comprises silicon nitride or silicon oxynitride ( _{SiOxNY )} . 17. The method of manufacturing a thin film transistor array panel as claimed in claim 13, wherein the semiconductor layer comprises α-Si:H material. 18. The method of manufacturing a thin film transistor array panel as claimed in claim 13, wherein the ohmic contact layer comprises n ⁺ α-Si:H material. 19. The method for manufacturing a thin film transistor array panel as claimed in claim 14, wherein the first etching process is dry etching, and the reactive gas used includes sulfur hexafluoride (SF ₆ ) or carbon tetrafluoride (CF ₄ ) . 20. The method for manufacturing a thin film transistor array panel as claimed in claim 14, wherein the second etching procedure is dry etching, and the reactive gas used includes oxygen (O ₂ ) or sulfur hexafluoride and oxygen (SF ₆ /O ₂ ). 21. The method for manufacturing a thin film transistor array panel as claimed in claim 14, wherein the third etching process is dry etching, and the reaction gases used include chlorine (Cl ₂ ), sulfur hexafluoride and chlorine (SF ₆ /Cl ₂ ) or boron trichloride and chlorine (BCl ₃ /Cl ₂ ). 22. The method for manufacturing a thin film transistor array panel as claimed in claim 14, wherein the partially light-transmitting region has a light transmittance between 20% and 80%. 23. The method of manufacturing a TFT array panel as claimed in claim 14, wherein the opaque area has a light transmittance of approximately 0% and the light transmittance area has a light transmittance of approximately 100%.

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