CN1645465A - Gate driving method and circuit of liquid crystal display - Google Patents

Abstract

A gate driving method and circuit of a liquid crystal display, wherein the liquid crystal display has a plurality of scanning lines. The method comprises the following steps: generating a gate driving signal; superposing a correction signal with the polarity opposite to that of the grid driving signal to generate a corrected grid driving signal so as to reduce the high potential level of the grid driving signal; and outputting a modified gate driving signal, and driving a corresponding one of the scan lines with the modified gate driving signal.

Description

Gate driving method and circuit of liquid crystal display

technical field

The invention relates to an improvement method of a liquid crystal display, and in particular to a method for reducing flickering of the liquid crystal display screen and increasing charging time.

Background technique

Liquid crystal displays have become more and more popular in recent years, not only can save space, but also can reduce power consumption, now gradually large-size, high-resolution liquid crystal displays are used to replace traditional displays, just like cathode ray tube displays (CRT display ), however, there is an important problem in large-size liquid crystal displays, that is, the larger the screen size of the liquid crystal display, the more serious the problem of flickering on the liquid crystal display screen.

Figure 1 shows the basic structure of a liquid crystal display (Liquid Crystal Display, LCD), the gate driver (Gate driver) 102 is responsible for turning on and off the thin film transistor (Thin Film Transistor, TFT), and the source driver (Source driver) 101 is responsible for outputting data For the liquid crystal capacitor, the voltage on the liquid crystal capacitor can reach the level it should have during the time when the thin film transistor is turned on.

Traditionally, the gate driver IC (Gate driver IC) 102a on the liquid crystal display outputs a start signal to turn on the thin film transistors one by one, so that the source driver IC (Source driver IC) 101a sends data into the liquid crystal capacitor. However, due to the inherent characteristics of the liquid crystal display relationship, it is easy to cause the screen to flicker (flicker).

As shown in FIG. 2 , FIG. 2 is a schematic diagram of a subpixel in a liquid crystal display panel. Generally speaking, each LCD sub-pixel is composed of a switching element (such as a transistor TFT), a liquid crystal capacitor CLC and a holding capacitor Cst connected to the drain (Drain, D) of the transistor TFT. A plurality of the aforementioned sub-pixels form an array arranged in rows and columns. The sub-pixels in the same column are connected to the scanning line by the transistor gate (Gate, G) of each sub-pixel, and the sub-pixels in the same row are connected to the scanning line by the gate of each sub-pixel. The source (Source, S) of the transistor is connected to the data line. As shown in Figure 2, when the Gnth scanning line is selected, the gate driver IC on the liquid crystal display outputs a start signal to the Gnth scanning line, that is, to the gate G of the transistor TFT; then the data signal waveform Transfer to the data line of the Snth line. At this time, the transistor TFT is turned on, and the data is transmitted to the drain D through the source S of the transistor TFT, thereby charging the liquid crystal capacitor C _LC and the holding capacitor Cst. According to the voltage across the liquid crystal capacitor C _LC , the sub-pixel can correspondingly display the gray scale of the sub-pixel to achieve the function of displaying images. The holding capacitor Cst can maintain the voltage across the liquid crystal capacitor C _LC during this display period.

The starting signal waveform of the output shown in Figure 2 is a square wave. Due to the semiconductor process of the panel, there will be stray capacitance and resistance on the scanning line, which will generate RC delay (RCdelay), resulting in waveform distortion. Figure 3A shows the start-up waveform signal output by the gate driver IC on the liquid crystal display, where V _GH and V _GL are the highest and lowest levels of the start-up signal waveform respectively, and ΔV _GH is the difference between the highest level and the lowest level, as shown in Fig. 3B is the waveform after a section of the scan line is affected by the stray resistance and capacitance on the scan line. Figure 3C is the waveform of the second half of the scan line, where V ₁ is the highest level after the waveform is distorted, and ΔV ₁ is the waveform distortion The difference between the highest level and the lowest level at the end, it can be clearly seen that the start signal waveform is affected by the RC delay on the scanning line, and the final waveform is different from the original waveform and the larger the panel size, the distortion The more serious it is, the more late the starting waveform signal on the scanning line is, the more time it takes to reach the level (that is, V _GH , V _GL ).

In addition, in order to ensure that all the thin film transistors on the Gnth scanning line are turned off when the Gn+1th scanning line is activated, generally the gate driver IC on the liquid crystal display will output enable through the output gate ( Gate Output Enable, GOE) signal to ensure that the upper and lower adjacent scan lines will not start at the same time, the timing relationship is shown in Figure 4, the original charging time of a scan line is t ₄ , which is the size of a clock, However, due to the addition of the gate output enable signal, the time is shortened by Δt, so the actual charging time of the scan line is t ₅ . If the panel resolution is higher, the time t ₄ of the clock cycle will be relatively smaller. , and the larger the panel size, the relatively longer scanning lines will become, and the RC delay will become more serious, so Δt must be larger to avoid simultaneous activation of adjacent scanning lines.

Because the size of liquid crystal displays is getting larger and the resolution is getting higher and higher, the length of the charging time _t4 is relatively shortened, and Δt must maintain a certain size under the dual influence of the actual charging time _t5 The length becomes shorter, which makes the charging time more insufficient, so this will have a non-negligible impact on the liquid crystal display towards the goal of large size and high definition.

Another disadvantage of the LCD driver is the effect of the feedthrough voltage (V _feedthrough ), which is defined as follows:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; feedthrough</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; GD</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; GD</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; LC</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; st</span>}}}\mathrm{<span\; class="notranslate">\; \&Delta;V</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; \&Delta;V</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; V</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GL</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Among them, C _GD is the stray capacitance between the gate and drain of the thin film transistor (TFT), C _LC is the liquid crystal capacitance, Cst is the holding capacitance, and ΔV is the voltage difference at the end of the start signal waveform.

As shown in Figure 5, Figure 5 is a schematic diagram of the positive field and the negative field. When the voltage on the liquid crystal capacitor is charged to the required level during the time when the thin film transistor is turned on, but when the signal is turned off, because the gate of the thin film transistor Due to the stray capacitance (C _GD ) between the drain and the drain, the voltage will drop by ΔV _a from the original level, resulting in a difference between the liquid crystal capacitance (C _LC ) and the common voltage V _com in the positive and negative fields. The pressure difference is different, and this will cause the flicker phenomenon in the picture. The current general solution is to adjust the common voltage V _com so that the voltage difference between the liquid crystal capacitor and the common voltage is the same in the positive and negative fields, as shown by the dotted line in Figure 5, which is the adjusted common voltage V' _com value, so that there will be no flickering of the screen.

The above situation is an ideal situation. If the feed-through voltage effect of each liquid crystal sub-pixel is the same, it is undoubtedly possible to effectively solve the phenomenon of flickering on the liquid crystal display by adjusting the common voltage V _com . However, due to other factors such as the process, the effect of the feed-through voltage of each liquid crystal sub-pixel is different, so that the effect is limited. As shown in Figures 3A, 3B, 3C and formula (1), the voltage difference ΔV at the end of the start signal waveform at the front end and back end of the same scan line is different, and the highest level V ₁ after waveform distortion is less than the start signal The highest level V _GH of the waveform, that is, the difference ΔV ₁ between the highest level and the lowest level of the start signal at the rear end of the scan line is less than the difference ΔV _GH between the highest level and the lowest level of the start signal at the front end of the scan line, causing the front end of the scan line to The generated feedthrough voltage V _feedthrough is not equal to the feedthrough voltage V _feedthrough generated at the rear end. At this time, the adjustment of the common voltage V _com cannot make the voltage on the liquid crystal capacitors at the front and rear ends of the same scanning line equal to the difference between the common voltage V _com The pressure difference between them is the same, so that the problem of screen flickering cannot be effectively solved.

Different from the above-mentioned second method to solve the screen flickering, in order to reduce the feed-through voltage effect, a waveform with a chamfering function can be used, as shown in Figure 6A, by this function, the voltage difference ΔV at the end of the startup signal waveform From the difference ΔV _GH between the highest level and the lowest level to the new difference ΔV′ _GH between the highest level and the lowest level, because the voltage difference ΔV at the end of the starting signal waveform becomes smaller, the effect of the feed-through voltage also becomes smaller small, but this method still cannot change the impact of the waveform distortion caused by the RC delay of the scan line, as shown in Figure 6B, because of the RC delay, the waveform at the rear end of the scan line will rise relatively slowly, causing when the start-up The voltage level is different when the angle is cut, that is to say, the highest level V _GH will be greater than the highest level V ₂ after the waveform is distorted, so the level after the angle is different, that is, the new highest level The difference ΔV′ _GH from the lowest level will be greater than the difference ΔV′ ₂ between the new highest level and the lowest level after waveform distortion. Therefore, it can be seen from Figures 6A and 6B that although the effect of the feed-through voltage is reduced, the front and rear ends of the scanning line The voltage difference to the common voltage V _com is still different, so the problem of screen flickering cannot be effectively solved.

From the above, it can be seen that there are still areas for improvement in liquid crystal displays. One is to increase the charging time of the liquid crystal capacitor, and the other is to reduce the influence of the scan line due to the RC effect, so that the feedthrough voltage V _feedthrough at the front and rear ends should be as close as possible .

Contents of the invention

The purpose of the present invention is to provide a driving method and circuit of a liquid crystal display, which can minimize the difference of the feed-through voltage between the front end and the rear end of the same scanning line, so as to reduce the flickering of the screen.

Another object of the present invention is to provide a driving method and circuit of a liquid crystal display, which can increase the charging time of the liquid crystal capacitor.

In order to achieve the above object, the present invention provides a gate driving method of a liquid crystal display, the liquid crystal display has a plurality of scanning lines. The gate driving method includes: generating a gate driving signal; superimposing a correction signal having a polarity opposite to the gate driving signal to the gate driving signal to generate a modified gate driving signal to reduce the high potential level of the gate driving signal and outputting a modified gate driving signal, and using the modified gate driving signal to drive one of the corresponding scanning lines.

In the foregoing gate driving method, the gate driving signal may be a positive voltage square wave, and the correction signal may be a negative voltage square wave. In addition, the superposition of the correction signal to the gate driving signal is performed near the falling edge of the gate driving signal.

According to an embodiment of the present invention, the present invention also provides a gate driving method of a liquid crystal display, the liquid crystal display has a plurality of scan lines. The gate driving method includes: generating a gate driving signal; performing a chamfering action on the gate driving signal to reduce the high potential level of the gate driving signal; The opposite correction signal is superimposed on the chamfered gate drive signal to generate a correction gate drive signal to reduce the high potential level of the gate drive signal again; and to output the correction gate drive signal, and to correct the gate drive signal to drive one of the corresponding scan lines.

In the foregoing gate driving method, the gate driving signal may be a positive voltage square wave, and the correction signal may be a negative voltage square wave. The aforesaid chamfering operation is performed near the falling edge of the gate driving signal. Preferably, superimposing the correction signal to the chamfered gate driving signal is performed immediately after the chamfering action is completed.

According to an embodiment of the present invention, the present invention provides a method for generating a gate driving signal of a liquid crystal display, so as to make the above gate driving signal drive a scan line of the liquid crystal display. The method includes: generating a positive voltage square wave signal having a high potential level and a low potential level; and superimposing a negative voltage on the positive voltage square wave signal at a first predetermined time point before a falling edge of the positive voltage square wave signal square wave signal to generate the gate drive signal.

In the foregoing method, it may further include performing a chamfering action on the gate drive signal at a second predetermined time point before the falling edge of the positive voltage square wave signal, so as to reduce the high potential level of the gate drive signal, wherein the first The point in time is after the second point in time. Preferably, the superimposition of the negative voltage square wave signal is performed immediately after the end of the corner cutting action.

According to an embodiment of the present invention, the present invention also provides a gate driver for generating gate drive signals for driving a plurality of scan lines of the liquid crystal display. The gate driver includes: a positive voltage square wave generating module for generating a positive voltage square wave signal with a high potential level and a low potential level; and a negative voltage square wave generating unit for generating a negative voltage square wave signal; and The superposition unit is coupled to the output of the positive voltage square wave generation module and the negative voltage square wave generation unit, and at the first predetermined time point before the falling edge of the positive voltage square wave signal, the negative voltage square wave signal and the positive voltage square wave signal Wave signals are superimposed to generate gate drive signals.

In the aforementioned gate driver, it may further include a chamfering processing unit, which may be coupled to the positive voltage square wave generating module, and at the second predetermined time point before the falling edge of the positive voltage square wave signal, the gate drive The signal is clipped to reduce the high potential level of the gate driving signal, wherein the first time point is after the second time point.

According to the method and structure proposed by the present invention, before the positive voltage square wave gate driving signal is provided to each scanning line, a negative voltage square wave signal is used for correction. The corrected gate driving signal is provided to the scan lines. Since the negative voltage square wave signal is also affected by the stray capacitance and resistance on the scan line, the high and low level voltages of the falling edge of the gate drive signal on the entire scan line from the front position to the rear position The drop will tend to be consistent. The associated feedthrough voltage V _feedthrough also tends to be equal, so the flickering problem of the picture can be effectively improved, and at the same time, the charging time of the liquid crystal capacitor can be increased.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below in conjunction with the accompanying drawings.

Description of drawings

Figure 1 is a basic structural diagram of a liquid crystal display;

FIG. 2 is a schematic diagram of sub-pixels in a liquid crystal display panel;

FIG. 3A is a starting waveform signal output by a gate driver IC on a liquid crystal display;

Fig. 3B is a waveform after a section of scanning line is affected by stray resistance and capacitance on the scanning line;

Figure 3C is the waveform of the second half of the scan line;

Fig. 4 is a sequence diagram;

Figure 5 is a schematic diagram of a positive image field and a negative image field;

Fig. 6A is a kind of waveform with chamfering function;

FIG. 6B is a waveform of a chamfering function in the second half of the scan line;

Fig. 7 is a schematic diagram of a negative square wave, and a schematic diagram of a negative square wave affected by RC delay;

Fig. 8 is a voltage schematic diagram when a negative square wave is added to the starting signal waveform;

Figure 9 is the waveform of adding negative voltage after adding the chamfering function;

FIG. 10 shows a timing diagram of the generation and output of the gate drive signal in the present invention.

Detailed description of the invention

The technical feature of the present invention is to minimize the difference of the feed-through voltage of each transistor on the same scanning line, so as to reduce the screen flicker phenomenon. The present invention assumes that C _GD /(C _GD +C _LC +C _st ) in the formula (1) is a constant value, and focuses on adjusting the part of ΔV, that is, adjusting the pressure difference at the end of the starting signal waveform.

Because the input positive voltage square wave signal (gate drive signal) will cause the above-mentioned known problems, the negative voltage square wave signal will also suffer the same effect when passing through the stray capacitance and resistance on the scanning line. Therefore, if a negative voltage square wave signal (correction signal) is superimposed on the positive voltage square wave signal to generate a modified gate drive signal, then only the front and rear end voltages of the scanning line generated when the positive voltage square wave signal is input The difference in drop will reduce the voltage drop at the front and rear ends due to the existence of the negative voltage square wave signal. Next, the function of adding this negative voltage square wave signal will be described in detail.

As shown in Figure 7, Figure 7 is a schematic diagram of a negative square wave, where it is assumed that the equivalent stray resistance and equivalent stray capacitance on the entire scanning line are R _equal and C _equal , as can be seen from the figure, this After the voltage is affected by the RC delay on the scanning line, the waveform at the rear end of the scanning line will become as shown on the right side of Figure 7. When the negative voltage square wave signal is applied to the liquid crystal capacitor on the scanning line, the voltage on the liquid crystal capacitor will drop, and due to the RC effect on the scanning line, the negative voltage square wave signal will be generated at the front and rear of the scanning line. The voltages at the terminals are different, that is, the lowest level |V _A | (front end) of the negative voltage square wave signal is greater than the lowest level |V _B | (back end) after the waveform is distorted. Therefore, when the negative voltage square wave signal is superimposed on the liquid crystal capacitance on the scan line, the voltage drop at the rear end of the scan line is smaller than the voltage drop at the front end, so the voltage drop at both ends of the scan line will be closer.

FIG. 8 shows the modified voltage waveform after the positive voltage square wave signal is added to the negative voltage square wave signal. As shown on the left side of Figure 8, it shows the front part of the scanning line. The time point to start adding the negative voltage square wave signal is when the positive voltage square wave changes from the highest level to the low level (V _GL , such as 0V ) before the time point. ΔV" _GH in the figure is the difference between the highest level and the lowest level of the negative voltage square wave signal. That is, when the negative voltage square wave signal as shown in Figure 7 is applied, the originally applied positive voltage square wave signal The highest level V _GH will be pulled down to V″ _GH by the negative voltage value of the negative voltage square wave signal (eg -V _A in FIG. 7 ). At this time, ΔV in the aforementioned formula (1) changes from V _GH −V _GL to V″ _GH −V _GL =ΔV″ _GH . In other words, ΔV is reduced by V _GH −V″ _GH .

Next, refer to the right diagram of Figure 8, which shows the rear end of the same scan line. The time point of starting to add the negative voltage square wave signal is still the time point before the positive voltage square wave changes from the highest level to the low level (V _GL , eg 0V). ΔV' ₃ in the figure is the difference between the highest level and the lowest level after adding a negative voltage square wave signal when the waveform is distorted. It can be seen from Figure 8 that when the negative voltage square wave signal shown in Figure 7 is applied, the highest level _V3 of the positive voltage square wave signal originally applied at the rear end of the scanning line will be replaced by the negative voltage value of the negative voltage square wave signal (eg -V _B in FIG. 7 ), pull down to V′ ₃ . At this time, ΔV in the aforementioned formula (1) changes from V ₃ −V _GL to V′ ₃ −V _GL =ΔV′ ₃ . In other words, ΔV is reduced by V ₃ −V′ ₃ .

Comparing the left and right of Figure 8, the negative voltage square wave signal will also be affected by the stray capacitance and resistance on the scanning line, resulting in different voltage drop values at the front end and the rear end of the scanning line, and due to the negative voltage square wave signal The polarity of the positive voltage square wave signal is opposite, so the amount of pulling down the voltage V _GH at the front end of the scan line and the amount of pulling down the voltage V ₃ at the rear end of the scan line are different. Therefore, the voltage drop V _GH -V″ _GH at both ends is also different from V ₃ -V' ₃ , but because the V _GH at the front end of the scanning line is greater than the V ₃ at the rear end, the front end and the rear end ΔV of the scanning line are almost close. That is, ΔV(front end)=ΔV″ _GH =V″ _GH −V _GL ≈ΔV′ ₃ =V′ ₃ −V _GL =ΔV(rear end).

In other words, when the starting voltage waveform is a square wave signal, after adding a negative square wave voltage signal, the difference between the highest level and the lowest level of the negative voltage square wave signal ΔV″ _GH (front end of the scanning line) tends to The difference ΔV′ ₃ between the highest level and the lowest level of the negative voltage (the rear end of the scanning line) is close to waveform distortion, and the feedthrough voltage V _feedthrough tends to be equal. At this time, adjusting the common voltage V _com can make The voltage difference between the voltage of the liquid crystal capacitors on the same scanning line and the common voltage V _com is the same in the positive and negative field, so the flickering of the LCD screen can be reduced.

The present invention is not necessarily limited to waveforms where only negative voltages are applied. FIG. 9 shows another implementation mode of the present invention, which is an implementation mode in which a clipping function is added to the positive voltage square wave of the gate driving signal. In the gate drive signal, adding the corner-cutting function to the positive voltage square wave signal is a known way to solve the flicker problem, but the liquid crystal capacitance at the front and rear ends of the scan line still has a large difference in voltage difference with respect to the common voltage, which cannot be solved. Effectively solve the flickering problem. However, after applying the concept of the negative voltage square wave signal of the present invention, the feedthrough voltages at the front and rear ends of the scanning line can be made closer, and the problem of screen flickering can be further solved.

As shown in Figure 9, it shows the waveform of adding a negative voltage after adding the chamfering function. The left side of Figure 9 shows the front-end waveform of the scanning line, and the right side shows the rear-end waveform. First look at the front-end waveform. First, cut the angle of the drive signal output by the gate driver, that is, the positive voltage square wave signal, so that the original high level is reduced from V _GH to V′ _GH . At the end of the chamfering effect, a negative voltage square wave signal is applied to lower the high level from V′ _GH to V _GH . That is, when the negative voltage square wave signal as shown in Figure 7 is applied, the highest level V' _GH of the originally applied positive voltage square wave after cutting the bevel angle will be replaced by the negative voltage value of the negative voltage square wave signal (such as shown in FIG. 7 of -V _A ), pull down to V _GH . At this time, ΔV in the aforementioned formula (1) changes from V′ _GH −V _GL to V _GH −V _GL =ΔV _GH . In other words, ΔV is reduced by ΔV ₄ =V' _GH -V _GH .

Next, refer to the right diagram of Figure 9, which shows the rear end of the same scan line. The time point of starting to add the negative voltage square wave signal is still the time point when the positive voltage square wave is cut off from the highest level and ends. ΔV″ ₅ in the figure is the difference between the highest level and the lowest level after adding the negative voltage square wave signal when the waveform is distorted. It can be seen from Figure 9 that when the negative voltage square wave signal shown in Figure 7 is applied, the original The highest level V′ ₅ of the positive voltage square wave applied at the rear end of the scan line after cutting the bevel angle will be pulled down to V″ ₅ by the negative voltage value of the negative voltage square wave signal (such as -V _B in Figure 7). . At this time, ΔV in the aforementioned formula (1) changes from V′ ₅ −V _GL to V″ ₅ −V _GL =ΔV″ ₅ . In other words, ΔV is reduced by ΔV ₅ =V′ ₅ −V″ ₅ .

Comparing the left and right of Figure 9, the negative voltage square wave signal will also be affected by the stray capacitance and resistance on the scanning line, resulting in different voltage drop values at the front end and the rear end of the scanning line, and due to the negative voltage square wave signal The polarity of the positive voltage square wave signal is opposite, so the amount of pulling down the beveled voltage V' _GH at the front end of the scan line and the amount of pulling down the beveled voltage V' ₅ at the rear end of the scan line are different . Therefore, the voltage drop ΔV ₄ and ΔV ₅ at both ends are also different, but because the V′ _GH at the front end of the scanning line is greater than the V′ ₅ at the rear end, the front end and the rear end ΔV of the scanning line are almost close. That is, ΔV(front end)= _ΔVGH = _VGH -V _GL≈ΔV " ₅ =V" ₅ - _VGL =ΔV(rear end).

In other words, when the starting voltage waveform is a square wave signal, after starting the bevel cutting and adding a negative square wave voltage, the difference between the highest level and the lowest level of the negative voltage _ΔVGH (front end of the scanning line) The difference between the highest level and the lowest level of the negative voltage is ΔV″ ₅ (at the back end of the scanning line), and the feedthrough voltage V _feedthrough tends to be equal. At this time, adjusting the common voltage V _com is The voltage difference between the voltage of the liquid crystal capacitor on the same scanning line and the common voltage V _com can be the same in the positive and negative field, so the screen flickering degree of the liquid crystal display can be reduced.

After the above description, after the negative voltage square wave signal is applied to the gate drive signal (start signal waveform) output by the gate driver, regardless of whether there is a step of chamfering the gate drive signal, at the end of the scanning line The voltage drop ΔV at the front and rear ends tends to be consistent. Also because the feedthrough voltage V _feedthrough is proportional to the voltage difference ΔV at the end of the start signal waveform, the feedthrough voltage V _feedthrough at the front and rear ends of the scan line is almost equal. Therefore, the problem of picture flickering can be effectively solved.

The aforementioned method can be implemented by adding a negative voltage square wave generator to the gate driver, and when there is an angle-cutting function, circuits related to the corner-cutting function can be added. For example, a circuit for generating the aforementioned negative voltage square wave signal and a circuit for generating the aforementioned angle-cutting effect are added to the originally known gate driver. In addition, a superposition circuit may be further included to superimpose the aforementioned positive and negative voltage square wave signals to generate a modified gate driving signal.

Another shortcoming of the liquid crystal display is the insufficient charging time, and the present invention can also achieve the effect of solving it. Next, the method for increasing the charging time of the present invention will be briefly described.

FIG. 10 shows a timing diagram of the generation and output of the gate drive signal in the present invention. As shown in Fig. 10, Fig. 10 is a schematic illustration of all the aforementioned waveform signals, where GCK is the clock waveform of the gate driver IC, X _n is the signal to start the chamfering function, and Y _n is the signal to start the negative voltage waveform. As shown in FIG. 10 , after the time T10 of the clock GCK, the gate driver outputs a gate driving signal on, for example, the n-th scanning line _Gn , and the highest level of the signal is V _GH . Afterwards, at time T11, according to the rising edge of the signal Xn that starts the clipping function, the gate drive signal starts to be clipped, and the highest level is pulled down from V _GH to V GH with a fixed slope. ' _GH . Then, at the time point T12, this is the falling edge of the signal Xn of the chamfering function, and the chamfering function ends at this time, and the signal Yn that starts the negative voltage square wave appears at the same time, so at the time point T12, the pair that has been chamfered The negative voltage square wave is added to the waveform, so that the level is pulled down from V′ _GH to V _GH . Therefore, at the time point of T20, the pressure difference is V _GH −V _GL . At time T20, the gate output enable signal GOE is output, and after the signal GOE ends, the above operation is repeated to drive the next scan line G _n+1 to output.

By the above method, the negative square wave voltage is controlled to be started when the signal _Xn that starts the chamfering function is about to end, and after the gate output enable signal GOE is started, the negative square wave voltage still continues to operate. In this way, when the voltage level of the thin film transistor on the scanning line is to return from the highest level V _GH of the start signal waveform to the lowest level V _GL of the start signal waveform, because the lowest level V _GL of the start signal waveform It is also a negative voltage value, and the current direction is the same as this negative voltage square wave, so this negative voltage square wave will accelerate the speed of the current, making its voltage level return to the lowest level V _GL of the start signal waveform faster, reducing the cause Delay phenomenon caused by RC delay. Therefore, in order to prevent two adjacent scanning lines from starting at the same time, the gate output enable GOE signal was added, so the length of the signal can be shortened. In this way, the charging time of the liquid crystal capacitor of the liquid crystal display increases, so the present invention can also solve the problem of insufficient charging time on the liquid crystal display.

To sum up, using a negative square wave voltage in the present invention can reduce the screen flicker of the liquid crystal display and increase the charging time of the liquid crystal capacitor.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art should be able to make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the appended claims.

Claims (12)

1. A gate driving method of a liquid crystal display, the liquid crystal display has a plurality of scanning lines, and the gate driving method of the liquid crystal display comprises: generate a gate drive signal; superimposing a modified signal having a polarity opposite to the gate driving signal to the gate driving signal to generate a modified gate driving signal to reduce the high potential level of the gate driving signal; and The modified gate driving signal is output, and the corresponding one of the scanning lines is driven by the modified gate driving signal. 2. The gate driving method of a liquid crystal display as claimed in claim 1, wherein the gate driving signal is a positive voltage square wave, and the correction signal is a negative voltage square wave. 3. The gate driving method of a liquid crystal display as claimed in claim 1, wherein superimposing the correction signal on the gate driving signal is performed near a falling edge of the gate driving signal. 4. A gate driving method of a liquid crystal display, the liquid crystal display has a plurality of scan lines, and the gate driving method of the liquid crystal display comprises: generate a gate drive signal; performing a chamfering action on the gate driving signal to reduce the high potential level of the gate driving signal; After the chamfering action is completed, a correction signal with a polarity opposite to the gate driving signal is superimposed on the chamfered gate driving signal to generate a modified gate driving signal to reduce the gate driving signal again The high potential level of ; and The modified gate driving signal is output, and the corresponding one of the scanning lines is driven by the modified gate driving signal. 5. The gate driving method of a liquid crystal display as claimed in claim 4, wherein the gate driving signal is a positive voltage square wave, and the correction signal is a negative voltage square wave. 6. The gate driving method of a liquid crystal display as claimed in claim 4, wherein the corner-cutting operation is performed near the falling edge of the gate driving signal. 7. The gate driving method of a liquid crystal display as claimed in claim 6, wherein superimposing the correction signal on the chamfered gate driving signal is performed immediately after the chamfering action is completed. 8. A method for generating a gate drive signal of a liquid crystal display, used to drive the gate drive signal to drive a scan line of the liquid crystal display, the method for generating a gate drive signal of a liquid crystal display comprising: generating a positive voltage square wave signal having a high potential level and a low potential level; and At a first predetermined time point before the falling edge of the positive voltage square wave signal, a negative voltage square wave signal is superimposed on the positive voltage square wave signal to generate the gate driving signal. 9. The gate driving method of a liquid crystal display as claimed in claim 8, further comprising performing an angle-cutting action on the gate driving signal at a second predetermined time point before the falling edge of the positive voltage square wave signal , to reduce the high potential level of the gate driving signal, wherein the first time point is after the second time point. 10. The gate driving method of a liquid crystal display as claimed in claim 9, wherein superimposing the negative voltage square wave signal is performed immediately after the corner-cutting action is completed. 11. A gate driver, used to generate gate drive signals for driving a plurality of scanning lines of the liquid crystal display, the gate driver comprising: A positive voltage square wave generating module, used to generate a positive voltage square wave signal, with a high potential level and a low potential level; and A negative voltage square wave generating unit, used to generate a negative voltage square wave signal; and a superposition unit, coupled to the output of the positive voltage square wave generating module and the negative voltage square wave generating unit, and at the first predetermined time point before the falling edge of the positive voltage square wave signal, the negative voltage square wave The signal is superimposed with the positive voltage square wave signal to generate the gate drive signal. 12. The gate driver of claim 11, further comprising: a corner-cutting processing unit, coupled to the positive voltage square wave generating module, performing a corner-cutting action on the gate drive signal at a second predetermined time point before the falling edge of the positive voltage square wave signal, to reduce the high potential level of the gate driving signal, wherein the first time point is after the second time point.

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