CN1607670A - Partially depleted SOI metal oxide semiconductor device - Google Patents

Abstract

A partially depleted SOI MOS device comprises a first conductive well isolated and insulated in a bulk film layer of an SOI substrate, the SOI substrate comprising the bulk film layer, a supporting substrate and a deep buried oxide layer between the bulk film layer and the supporting substrate; a gate dielectric layer disposed on the surface of the first conductive well; a polysilicon gate disposed on the gate dielectric layer, the polysilicon gate having a first gate block of a first conductivity type overlapping an extended well region extending from the first conductivity type well, and a second gate block of a second conductivity type crossing over the first conductivity type well, thereby forming a tunneling connection configuration between the first gate block of the first conductivity type and the extended well region; and a drain and source region of the second conductivity type respectively disposed in the first conductivity type well at two opposite sides of the second gate block.

Description

Partially depleted SOI metal oxide semiconductor device

technical field

The present invention relates to an SOI semiconductor element, in particular to a high-efficiency partially depleted (Partially-Depleted) SOI metal-oxide-semiconductor (Metal-Oxide-Semiconductor, MOS) element using a direct tunneling mechanism and a manufacturing method thereof . According to a preferred embodiment of the present invention, the high-efficiency partially depleted SOI metal oxide semiconductor device has relatively high current-driving capability.

Background technique

In today's metal oxide semiconductor (MOS) devices, basically only a few hundred nanometers (nm) of the top silicon single crystal is used to make the active layer of the device for electron transmission; The rest of the underlying silicon acts as a mechanical support. Such a structure is easy to cause the parasitic effect (Parasitic Effect) between the device and the substrate. In addition, it will be very difficult to use the semiconducting silicon substrate as a dielectric insulation (Dielectric Insulator). So a concept of "place an electrically insulating thin film under the surface thin silicon single crystal element layer, and separate the element layer and the silicon substrate" was proposed. Such a structure is "silicon layer (Silicon) on (On) insulating layer (Insulator)", so it is generally called silicon-on-insulator (SOI) technology. The insulating layer used in this technology is generally silicon dioxide (SiO2, Buried Oxide, BOX). The main reason is that silicon dioxide grown by silicon thermal growth has better characteristics and has high process integration with silicon wafers. . Due to the difference in the thickness of the epitaxial silicon on the BOX, it can be divided into partially depleted (Partially-Depleted SOI; PDSOI or Thin SOI) and fully depleted (Fully-Depleted SOI; FDSOI or Ultra thin SOI). PDSOI means that the depth of the depletion region of the element is smaller than the thickness of SOI; while FDSOI means that the thickness of SOI is exactly the depth of the depletion region of the element. The selection of the above-mentioned different SOIs also brings about different advantages of the SOI. Among them, the PDSOI device can operate at a lower voltage, and has lower power loss compared with traditional silicon wafers, and it is easy to completely transfer this PDSOI technology to the existing silicon technology.

However, in addition to the quality and manufacturing cost of the SOI substrate, the current SOI technology faces many difficulties in component and circuit design. At the manufacturing level, neither bonded (BESOI) nor oxygen-implanted (SIMOX) SOI substrates are mature enough for low-cost mass production. In terms of component and circuit design, the application of PDSOI components needs to overcome the so-called floating body effect and kink effect. The floating body effect is well known to the traveler. Simply put, its cause is that the PDSOI element is located on the well body (floating well body) that is completely isolated and not connected to any potential. When the element is in operation, due to hot carriers (hotcarrier) ) collisions generate electron-hole pairs. Assuming that the hot carriers are electrons, the holes will gradually accumulate in the low-potential region of the well in the floating state, gradually increasing the potential of the channel, thereby reducing the start-up of the MOS transistor element. The starting voltage (threshold voltage). Such a jumping change in the drain voltage-current characteristic of the MOS transistor is called a distortion effect.

In the prior art, such as the U.S. SIR Patent No. H1435 filed on October 21, 1991 by Cherne et al., the title is "SOI CMOS device with extended body to provide sidewall channel and main body connection (SOI CMOS device having body extension for providing sidewall channel stop and bodytie)” discloses an SOI thin film metal oxide semiconductor element structure, which has a body/channel region (body/channel region) extension, and a selected part within the body extension has a higher concentration of Doping, thereby providing the body/channel region to be continuous with a predetermined bias voltage to form the body, while forming a channel barrier can block leakage current or avoid parasitic N-channel formation that may occur along the sidewall surface.

Other previous documents in related fields, such as US Patent No. 5,343,051 filed by Yamaguchi et al. on May 10, 1993, disclosed a "thin-film SOI MOSFET". For example, US Patent No. 5,920,093 filed by Huang et al. on April 7, 1997 discloses an "SOI FET having gate sub-regions conforming to t-shape", The channel region has a uniform doping profile, which can effectively avoid distortion effects. Another example is U.S. Patent No. 5,920,093 filed by Tyson et al. on December 29, 1997, disclosing a "SOI combination body tie" that utilizes an H-type transistor structure and a body contact ), so that the main body is in a grounded state to avoid the floating body effect.

However, the disadvantage of the above-mentioned conventional technology is that the fabrication process of the SOI MOS field effect transistor no matter in the form of body tie, T-gate or H-gate is cumbersome and complicated. In addition, the SOI devices disclosed in the above-mentioned prior art occupy a relatively large chip area. This is due to the need for an extra body contact, and additional wiring circuit design to make the body electrically connected to a bias voltage or shorted to the source. Furthermore, since the purpose of the SOI devices disclosed in the above prior art is to eliminate the so-called floating body effect, it is inevitable to sacrifice the operating performance of the SOI device. From this we can see that the prior art is still not perfect and there is a need for further improvement.

Contents of the invention

Accordingly, the main purpose of the present invention is to provide a high-efficiency partially-depleted (Partially-Depleted) SOI metal oxide semiconductor device, which occupies a smaller chip area.

Another object of the present invention is to provide a high-efficiency partially depleted SOI metal oxide semiconductor device, which has higher current driving capability and higher kink triggering voltage.

Another object of the present invention is to provide a method for fabricating a high-efficiency partially depleted SOI metal oxide semiconductor device occupying a smaller chip area.

According to a preferred embodiment of the present invention, a partially depleted SOI metal-oxide-semiconductor field-effect transistor element includes a first conductivity type well isolated and insulated in a film body layer of an SOI substrate, and the SOI substrate includes the film body layer, a support substrate, and a deep-buried oxide layer between the film main layer and the support substrate; a dielectric layer, disposed on the surface of the first conductivity type well; a polysilicon gate, disposed on the dielectric On the electrical layer, the polysilicon gate pole has a first gate block of the first conductivity type, which overlaps with an extended well region extending from the well of the first conductivity type, and a second gate block of the second conductivity type , which passes over the well of the first conductivity type, thereby forming a tunnel connection configuration between the first gate region of the first conductivity type and the extended well region; and the drain of the second conductivity type The source region and the source region are respectively arranged in the well of the first conductivity type on opposite sides of the second gate block.

According to another preferred embodiment of the present invention, a partially depleted SOI metal oxide semiconductor device includes a silicon wafer, a thin film main layer, a supporting substrate, and a device that electrically isolates the thin film main layer from the supporting substrate. The deep-buried oxide layer, and the main film layer has a main surface; the insulating shallow trench extends downward from the main surface of the main film layer to the deep-buried oxide layer, and is used to electrically isolate the main film layer, thereby The main surface of the film body layer forms an isolated (isolated) well region; a dielectric layer is arranged on the isolated well region; a polysilicon gate electrode is arranged on the dielectric layer and is of the first conductivity type, and the polysilicon The gate electrode has corresponding two ends on the long side, including a first end above a first insulating shallow ditch passing over the insulating well region and then extending to a second end above a second insulating shallow ditch, wherein part of the The first end and the second end of the polysilicon gate are implanted with a second conductivity type dopant electrically opposite to the first conductivity type, thereby forming a polysilicon gate implanted with the second conductivity type dopant. A tunnel connection configuration between the gate portion and the insulating well region; and the drain and source regions of the first conductivity type are respectively arranged in opposite sides of the polysilicon gate. Wherein the dielectric layer can be a silicon dioxide layer or a silicon nitride layer with a thickness ranging from 5-120 angstroms.

Description of drawings

Fig. 1 is a top view layout diagram of a partially depleted SOI MOSFET device (PD SOI MOSFET device) according to a preferred embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a partially depleted SOI MOSFET device seen along the tangent line AA in FIG. 1, showing the direct tunneling region between the polysilicon gate and the floating body. .

FIG. 3 is a schematic cross-sectional view of the partially depleted SOI MOSFET device seen along the tangent line BB in FIG. 1 .

FIG. 4 is a schematic cross-sectional view of the partially depleted SOI MOSFET element seen along the tangent line CC in FIG. 1 .

FIG. 5 is a top layout diagram of a partially depleted SOI MOS field effect transistor element according to another preferred embodiment of the present invention.

Fig. 6 shows the measured drain current (ID) versus drain-source bias for the PD SOI PMOSFET element of the present invention (gate channel length L=0.12 micron) under different gate-source bias voltages (VGS) pressure (VDS) curve.

Symbol Description:

10 SOI substrate 12 Support substrate

13 N-type well 14 Deep buried oxygen insulating layer

15 Insulation body 16 Silicon film layer

21 Shallow trench insulation region 22 Shallow trench insulation region

32 Gate Dielectric Layer 33 Polysilicon Gate Structure

35 P+gate block 36 N+gate block

38 First end 39 Second end

40 Direct Tunneling Region 42 Drain/Source

44 Drain/Source 52 Extended N-type well body region

60 ion implant openings

Detailed ways

The present invention relates to a structure of an SOI metal oxide semiconductor field effect transistor, especially using a direct tunneling mechanism to form a transistor with high efficiency, high current-driving capability and high twist-trigger voltage Novel SOI metal oxide semiconductor field effect transistor structure.

Please refer to Fig. 1 to Fig. 4 for the first preferred embodiment of the present invention, wherein Fig. 1 is a top view layout diagram of a partially depleted SOI metal oxide semiconductor field effect transistor element (PD SOI MOSFET device) in a preferred embodiment of the present invention; 2. FIG. 3 and FIG. 4 are schematic cross-sectional views of the partially depleted SOI metal oxide semiconductor field effect transistor element seen along the tangent line AA, the tangent line BB and the tangent line CC in FIG. 1 . The first preferred embodiment of the present invention shown in FIGS. 1 to 4 is illustrated by disclosing a PMOS partially depleted SOI MOSFET device. However, those skilled in the art should be able to understand that the SOI integrated circuit and related manufacturing process of the present invention can also be applied to the structure of NMOS partially depleted SOI metal oxide semiconductor field effect transistor elements, and only need to make the corresponding elements electrically A configuration opposite to that of the first preferred embodiment will suffice. First, as shown in Figures 1 and 2, an SOI substrate 10 is provided, which can be purchased by the industry through various commercial channels, and the SOI substrate can be processed by any suitable method, such as oxygen planting Separation by implanted oxygen (SIMOX) or bonded-and-etch back (BESOI). For example, the SOI substrate 10 used in the first preferred embodiment of the present invention is a wafer substrate made by the SIMOX method, which has a thin P-type silicon layer 16 and a deep buried oxygen insulating layer 14, and the thin P-type silicon layer 16 It is located on the deep-buried oxygen insulating layer 14 , which is supported by the base substrate or support substrate 12 . The thickness of the deep-buried oxygen insulating layer 14 is, for example, between 1300 and 1800 angstroms, but not limited thereto. The partially depleted SOI metal oxide semiconductor field effect transistor element of the present invention is formed in the thin P-type silicon layer 16 .

Next, an N-type well 13 is defined on the thin P-type silicon layer 16 of the SOI substrate 10 by means of lithography and ion implantation. More specifically, the partially depleted SOI MOSFET element of the present invention is formed in the N-type well 13 of the thin P-type silicon layer 16 . After completing the ion implantation of the wells, the definition of active areas (AA) follows. Firstly, using lithography and etching processes, an insulating shallow trench is dug in the thin P-type silicon layer 16 of the SOI substrate 10, and its depth reaches the deep buried oxygen insulating layer 14 of the SOI substrate 10, and then an insulating material is filled in the shallow trench, namely Shallow trench isolation (STI) regions 21 and 22 are formed, as shown in FIG. 2 , thereby defining an insulating body 15 electrically isolated by the STI regions.

As shown in FIGS. 1 and 4 , the electrically isolated insulating body 15 includes an extended N-type well region 52 . Next, the upper surface of the insulating body 15 is covered with a gate dielectric layer 32 , which can be formed by thermal oxidation. The gate dielectric layer 32 can be made of any material suitable as a gate dielectric layer, such as silicon dioxide, silicon nitride, oxynitride, aluminum, zirconium, lanthanum, tantalum (tantalum), hafnium (hafnium), and high-k dielectric layers, etc., are not limited in the present invention. The thickness of the gate dielectric layer 32 needs to be thin enough to enable direct tunneling of electrons or holes. According to the first preferred embodiment of the present invention, if the gate dielectric layer 32 is formed by thermal oxidation of silicon dioxide as an example, its preferred thickness is about 5 to 120 angstroms. After the fabrication of the gate dielectric layer 32 is completed, a chemical vapor deposition process, such as a low pressure chemical vapor deposition (LPCVD) process, is performed to deposit a polysilicon layer on the gate dielectric layer 32 (not shown in the figure). Show). The polysilicon layer is then etched into a polysilicon gate structure 33 using lithography and etching methods. The polysilicon gate structure 33 is properly doped with high-concentration dopants to form a P+ gate block 35 and an extended N+ gate block 36 at one end of the polysilicon gate structure 33, wherein the extended N+ gate block at one end of the polysilicon gate structure 33 The gate block 36 overlaps with the aforementioned extended N-type well body region 52 . Formation of the extended N+ gate region 36 can be accomplished using a suitable mask having an opening 60 exposing the end of the polysilicon gate structure 33 directly above the extended N-type well region 52 through which high Dose N-type ion implantation. As seen in FIG. 2 , the overlap region 40 between the extended N-well region 52 and the extended N+ gate region 36 can operate as a direct tunneling region (as indicated by the arrow). In the first preferred embodiment, the extended N+ gate block 36 at one end of the polysilicon gate structure 33 provides a channel for conduction band electrons to tunnel directly through the gate dielectric layer 32 into the floating body.

As shown in FIG. 1 and FIG. 3, using a suitable implant shield, a high dose of P-type dopant such as boron ions of about 1019 to 1020 ions/cm3 is implanted into the electrically isolated P+ gate block 35 on opposite sides. Insulating body 15 to form P+ drain/source regions 42 and 44 . P+ drain/source regions 42 and 44 define the P-channel below P+ gate block 35 .

Please refer to FIG. 5 . FIG. 5 shows a top layout view of a partially depleted SOI MOSFET device according to a second preferred embodiment of the present invention. The partially depleted SOI MOSFET element of the second preferred embodiment of the present invention is also fabricated in the N-type well 13 of the silicon thin film layer 16 of an SOI substrate (not shown). The SOI substrate can be purchased by the industry through various commercial channels, and can be processed by any suitable method, such as separation by implanted oxygen (SIMOX) or bonded-and- etch back, BESOI). For example, the SOI substrate used in the second preferred embodiment of the present invention is a wafer substrate manufactured by the SIMOX method, which has a thin P-type silicon layer 16 and a deep buried oxygen insulating layer. The thin P-type silicon layer 16 is located on On top of the deeply buried oxygen insulating layer, it is supported by a base substrate. The thickness of the deeply buried oxygen insulating layer is, for example, between 1300 and 1800 angstroms, but not limited thereto. The second preferred embodiment of the present invention shown in FIG. 5 is illustrated by disclosing a PMOS partially depleted SOI MOSFET device. However, those skilled in the art should be able to understand that the SOI integrated circuit and related manufacturing process of the present invention can also be applied to the structure of NMOS partially depleted SOI metal oxide semiconductor field effect transistor elements, and only need to make the corresponding elements electrically A configuration opposite to that of the second preferred embodiment is sufficient.

The N-type well 13 is formed in the silicon thin film layer 16 of the SOI substrate (not shown) through lithography and ion implantation techniques. More specifically, the partially depleted SOI MOSFET element of the present invention is formed in the N-type well 13 of the thin P-type silicon layer 16 . After completing the ion implantation of the wells, the definition of active areas (AA) follows. Firstly, by using lithography and etching processes, an insulating shallow trench is dug in the thin P-type silicon layer 16 of the SOI substrate, and its depth reaches the deep-buried oxygen insulating layer (not shown) of the SOI substrate 10, and then an insulating trench is filled in the shallow trench. The material is to form a shallow trench isolation (STI), thereby defining an insulating body well electrically isolated by the shallow trench isolation, and has two oppositely extending N-type wells 52 . Next, the upper surface of the insulating body well is covered with a gate dielectric layer, which can be formed by thermal oxidation. The gate dielectric layer can be made of any suitable material for the gate dielectric layer, such as silicon nitride, which is not limited in the present invention. The thickness of the gate dielectric layer needs to be thin enough to enable direct tunneling of electrons or holes. As shown in the figure, an elongated P-type polysilicon gate structure 33 is then formed on the gate dielectric layer, which has two opposite ends on the long side, and the first end 38 on the first shallow trench insulation region respectively passes through the well on the insulating body. The square extends to the second end 37 on the second STI region. Parts of the first end 38 and the second end 39 of the polysilicon gate structure 33 are implanted with N-type dopants. The method of implanting N-type dopants in the first end 38 and the second end 39 of the polysilicon gate structure 33 can use a suitable mask, which has an opening 60 to expose the polysilicon gate structure 33 located in the extended N-type well. 52 directly above the first end 38 and the second end 39 , and perform high-dose N-type ion implantation through the opening 60 . The other part of the polysilicon gate structure 33, ie the gate part 35 between the first terminal 38 and the second terminal 39, is implanted with P-type dopants using another suitable shield. The overlapping region between the extended N-well 52 and the first end 38 and the second end 39 of the polysilicon gate structure 33 implanted with N-type dopants can operate as a direct tunneling region. Finally, using a suitable implant shield, high doses of P-type dopants such as boron ions of about 1019 to 1020 ions/cm3 are implanted into electrically isolated insulating body wells on opposite sides of the P+ gate block 35 to form P+ drain/source region. The P+ drain/source regions define the P-channel under the polysilicon gate structure 33 .

Please refer to FIG. 6. FIG. 6 shows curves of drain current (ID) versus drain-source bias (VDS) measured for the PDSOI PMOSFET device of the present invention under different gate-source bias voltages (VGS). Compared with the previous technology, the partially depleted SOI metal oxide semiconductor field effect transistor element of the present invention has higher efficiency, including higher current driving capability and improved twisting touch voltage, so that the floating body effect of the transistor element is suppressed, and the with low leakage current. In the partially depleted SOI metal oxide semiconductor field effect transistor device in the first preferred embodiment of the present invention, the direct tunneling of electrons is believed to be achieved through the direct tunneling mechanism of electron-conduction band (ECB) rather than through Electron-Valence Band direct tunneling mechanism (Electron-Valence Band, EVB), because the voltage drop of the gate dielectric layer does not exceed 1 volt during device operation, so the valence band electrons are not easy to tunnel directly. During operation, the partially depleted SOI MOS field effect transistor device of the present invention has a reduced channel electric field near the drain terminal, thereby suppressing the distortion effect.

Claims (12)

1. a partially depleted SOI metal-oxide-semiconductor (MOS) (MOS) element includes:

The first conductivity type well of one isolated insulation in the main film body layer of a SOI substrate, this SOI substrate include this main film body layer, the buried oxide layer of a supporting substrate and between this main film body layer and this supporting substrate;

One brake-pole dielectric layer is located on the surface of this first conductivity type well;

One polycrystalline silicon gate pole, be located on this brake-pole dielectric layer, this polycrystalline silicon gate pole has one first conductivity type, the first gate block, itself and an extended reach well region overlapping that extends from this first conductivity type well, and one second conductivity type, the second gate block, it passed through the aboveground side of this first conductivity type, formed wearing tunnel and link configuration between this first conductivity type first gate block and this extended reach well zone whereby; And

Second conductivity type drain and the source region is located at respectively in this first conductivity type well of relative both sides of this second gate block.

2. partially depleted SOI metal-oxide-semiconductor element according to claim 1, wherein this brake-pole dielectric layer is to be selected from one of following combination material person: silicon dioxide, silicon oxynitride (oxynitride) or contain arbitrary or more than one dielectric layer with high dielectric constant in aluminium, zirconium (zirconium), lanthanum (lanthanum), tantalum (tantalum), the hafnium (hafnium).

3. partially depleted SOI metal-oxide-semiconductor element according to claim 1, wherein the thickness of this dielectric layer is between 5-120 dust (angstrom).

4. partially depleted SOI metal-oxide-semiconductor element according to claim 1, wherein this main film body layer is a silicon layer.

5. partially depleted SOI metal-oxide-semiconductor element according to claim 1, wherein this first conductivity type is the N type, this second conductivity type is the P type.

6. partially depleted SOI metal-oxide-semiconductor element according to claim 1, wherein this first conductivity type is the P type, this second conductivity type is the N type.

7. partially depleted SOI metal-oxide-semiconductor element includes:

One Silicon Wafer have a main film body layer, a supporting substrate and with this main film body layer and the electrically isolated buried oxide layer of this supporting substrate, and this main film body layer has a first type surface;

Insulating channel extends downward this buried oxide layer by the first type surface of this main film body layer, and in order to electrically isolated this main film body layer, the first type surface in this main film body layer forms insulation (isolated) well area whereby;

One brake-pole dielectric layer is located on this insulated wells zone;

One polycrystalline silicon gate pole, be located on this brake-pole dielectric layer and be first conductivity type, this polycrystalline silicon gate pole has corresponding two ends on the long limit, comprise that passing through this top, insulated wells zone by first end above one first insulating channel extends to second end that is positioned at one second insulating channel top then, wherein this first end and second end of this polycrystalline silicon gate pole of part are the implanted electrically second conductivity type admixtures opposite with this first conductivity type, and constituting whereby between implantation has one between the polycrystalline silicon gate pole part of this second conductivity type admixture and this insulated wells zone to wear tunnel binding configuration; And

First conductivity type drain and the source region, be located at respectively this polycrystalline silicon gate pole relative both sides should in.

8. partially depleted SOI metal-oxide-semiconductor element according to claim 7, wherein this brake-pole dielectric layer is by being selected from one of following combination material person: silicon dioxide, silicon oxynitride (oxynitride) or contain arbitrary or more than one dielectric layer with high dielectric constant in aluminium, zirconium (zirconium), lanthanum (lanthanum), tantalum (tantalum), the hafnium (hafnium).

9. partially depleted SOI metal-oxide-semiconductor element according to claim 7, wherein the thickness of this dielectric layer is between the 5-120 dust.

10. partially depleted SOI metal-oxide-semiconductor element according to claim 7, wherein this main film body layer is a silicon layer.

11. partially depleted SOI metal-oxide-semiconductor element according to claim 7, wherein this first conductivity type is the P type, and this second conductivity type is the N type.

12. partially depleted SOI metal-oxide-semiconductor element according to claim 7, wherein this first conductivity type is the N type, and this second conductivity type is the P type.

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