CN1560911B - Manufacturing method of circuit carrier plate - Google Patents
Manufacturing method of circuit carrier plate Download PDFInfo
- Publication number
- CN1560911B CN1560911B CN 200410005942 CN200410005942A CN1560911B CN 1560911 B CN1560911 B CN 1560911B CN 200410005942 CN200410005942 CN 200410005942 CN 200410005942 A CN200410005942 A CN 200410005942A CN 1560911 B CN1560911 B CN 1560911B
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- circuit carrier
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract 4
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims 15
- 238000007747 plating Methods 0.000 description 13
- 238000009413 insulation Methods 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 9
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 6
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- QWNCDHYYJATYOG-UHFFFAOYSA-N 2-phenylquinoxaline Chemical compound C1=CC=CC=C1C1=CN=C(C=CC=C2)C2=N1 QWNCDHYYJATYOG-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PMPVIKIVABFJJI-UHFFFAOYSA-N Cyclobutane Chemical compound C1CCC1 PMPVIKIVABFJJI-UHFFFAOYSA-N 0.000 description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
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- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
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- -1 polyphenylene quinoxaline Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
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- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- 238000003466 welding Methods 0.000 description 1
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- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A method for manufacturing a circuit carrier is suitable for manufacturing a circuit carrier such as a package carrier or a printed circuit board. Firstly, providing a support substrate made of a conductive material, wherein the support substrate is divided into a first structural layer and a second structural layer which is mutually overlapped with the first structural layer; patterning the first structure layer to form a first conductive pattern having a plurality of first conductive contacts arranged in an array; forming an insulating pattern in a space enclosed between the second structure layer and the first conductive pattern; forming a multilayer interconnection structure on the insulating pattern and the first conductive pattern, wherein the multilayer interconnection structure has a high-density internal circuit which is connected with the first conductive contact, and the internal circuit is provided with a plurality of bonding pads which are positioned on the surface of the multilayer interconnection structure far away from the first conductive pattern; and finally, removing at least partial second structural layer to form the circuit carrier plate without the traditional Plated Through Hole (PTH) and consisting of the high-density wiring pattern and the contact array of the conductive material.
Description
Technical field
The present invention relates to a kind of manufacture method of circuit support plate, specifically, relate to supporting substrate (support substrate) that a kind of application made by electric conducting material as initiation layer and utilize supporting substrate to produce to have the manufacture method of the circuit support plate of many conductive junction points.
Background technology
Flip-chip interconnection technique (Flip Chip Interconnect Technology is called for short FC) is a kind of method for packing that chip (die) is electrically connected to bearing part (carrier).Flip-chip interconnection technique (FC) mainly is to utilize area to arrange the mode of (area array), a plurality of chip mats (die pad) are disposed on the active surface (active surface) of chip, and on chip mat, form projection (bump), then afterwards with chip upset (flip), utilize these projections to make the chip mat of chip electrically reach structural the connection respectively again with bump pads (bump pad) on the bearing part, make chip to be electrically connected to the bearing part, and be electrically connected to extraneous electronic installation via the internal circuit of bearing part via these projections.It should be noted that, because flip-chip interconnection technique (FC) is applicable to the chip packing-body of high pin number (High Pin Count), and have the Chip Packaging of dwindling area simultaneously and shorten plurality of advantages such as signal transmission path, make the flip-chip interconnection technique be widely used in the Chip Packaging field at present, the chip-packaging structure of common application flip-chip bond technology for example has flip chip ball grid array type (Flip Chip/BallGrid Array, FC/BGA) and flip-chip pin grid array type (Flip Chip/Pin Grid Array, the chip-packaging structure of form such as FC/PGA).
See also Fig. 1, this figure is the generalized section of existing flip chip ball grid array type electronic packing body.Electronic packing body 100 comprises circuit support plate (circuit carrier) 110, a plurality ofly protrudingly determines 120, chip 130 and a plurality of soldered ball 140.Circuit support plate 110 has end face 112 and bottom surface on the other side 114, and circuit support plate 110 also has a plurality of bump pads (bump pad) 116a and a plurality of solder ball pad (ballpad) 116b.In addition, chip 130 has active surface (active surface) 132 and opposing backside surface 134, the one side with active block (activedevice) (not shown) of the active surperficial 132 general reference chips 130 of its chips 130.In addition, chip 130 also has a plurality of chip mats 136, they be configured in chip 130 active surperficial 132 on, in order to the media as the output of the signal of chip 130, input, and the position of bump pads 116a is corresponding with the position of these chip mats 136 respectively.In addition, projection 120 makes pairing protruding one of the 116a that certainly fills up of one of chip mat 136 and its be electrically connected and structural the connection respectively.Moreover soldered ball 140 is configured in respectively on the solder ball pad 116b, in order to be electrically connected and structural the connection with extraneous electronic installation.
Please equally referring to Fig. 1; existing electronic package method is at the internal circuit of finishing circuit support plate 110 and contact 116a; after the 116b; again chip 130 is assembled on the surface of circuit support plate 110; then primer (underfill) 150 is filled the end face 112 of circuit support plate 110 and active surperficial 132 spaces that surrounded of chip 130; in order to protection bump pads 116a; chip mat 136 and projection 120, and alleviate the phenomenon that do not match of the thermal strain (thermal strain) that circuit support plate 110 and chip 130 produced between circuit support plate 110 and the chip 130 simultaneously when being heated.Therefore, the chip mat 136 of chip 130 can electrically reach the structural bump pads 116a that is connected to circuit support plate 110 via projection 120, coiling (routing) downwards electrically reaches the structural extraneous electronic installation that is connected at last to the solder ball pad 116b of the bottom surface 114 of circuit support plate 110 via the soldered ball on the solder ball pad 116b 140 via the internal circuit of circuit support plate 110 again.
With regard to the circuit support plate manufacture method of high-density circuit wiring, prior art normally utilizes Layer increasing method (build-up process) to form a single circuit layer respectively on the two sides of a dielectric sandwich layer (dielectric core), or form multiple circuit layer in regular turn, and (Plated Through Hole PTH) electrically connects two circuit layers that lay respectively at the two sides of dielectric sandwich layer to utilize plated-through-hole.Yet, owing to used thickness the circuit support plate of thin dielectric sandwich layer be easy to be heated warpage (warp) phenomenon take place, so the dielectric sandwich layer of circuit support plate must have enough thickness, so could provide enough structural strengths relatively, but this causes also the thickness of dielectric sandwich layer further to reduce.
In addition, in order on the dielectric sandwich layer, to make plated-through-hole (PTH), prior art is normally utilized the mode of boring (drilling), on the dielectric sandwich layer, form the through hole of fine sizes, then electroplate a metal level in through-hole wall, in order to electrically connect two circuit layers that lay respectively at the two sides of dielectric sandwich layer.Yet,, therefore cause the whole manufacturing cost of circuit support plate to increase because the manufacturing process of existing plated-through-hole (PTH) normally utilizes boring to form the through hole of fine sizes.In addition, because the manufacturing process of existing plated-through-hole (PTH) can't effectively reduce the external diameter of plated-through-hole (PTH), and the plated-through-hole (PTH) with big external diameter will have a negative impact electrically, thereby existing plated-through-hole (PTH) has become the bottleneck of present high wiring density (high layout density) circuit support plate design.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of manufacture method of circuit support plate, in order to producing the circuit support plate with high wiring density, and can effectively reduce the production cost of circuit support plate.
For this reason, circuit support plate manufacture method provided by the invention comprises: a supporting substrate of being made by electric conducting material is provided, this supporting substrate be divided into first structure sheaf and with the second overlapped structure sheaf of this first structure sheaf; To the first structure sheaf composition, has first conductive pattern of a plurality of first conductive junction points of arranging with array way with formation; The space that is surrounded between second structure sheaf and first conductive pattern forms an insulation patterns; On the insulation patterns and first conductive pattern, form interconnect architecture in the multilayer, interconnect architecture has the high density internal circuit in the described multilayer, it links to each other with described first conductive junction point, and internal circuit has a plurality of joint sheets away from the surface of first conductive pattern that are positioned at the multilayer interconnect architecture; Remove local at least second structure sheaf at last.
Because the manufacture method of circuit support plate of the present invention is to make interconnect architecture in the multilayer with high-density circuit on the supporting substrate with conductivity, hardness (high stiffness) height, low (the low CTE) of thermal coefficient of expansion and high thermal conductance (high thermal conductivity), then remove the partial support substrate, directly utilize remaining supporting substrate to form a plurality of conductive junction points, and become the circuit support plate that has high-density circuit but do not have the dielectric sandwich layer in the bottom of circuit support plate; In addition, the present invention need not form plated-through-hole, plating line and welding cover layer, so can effectively reduce the production cost of circuit support plate.
Description of drawings
For described and other purpose, feature and advantage of the present invention can be become apparent, hereinafter will be elaborated to a preferred implementation in conjunction with the accompanying drawings.In the accompanying drawing:
Fig. 1 is the generalized section of existing flip chip ball grid array type electronic packing body;
Fig. 2 A to Fig. 2 E is the generalized section of the circuit support plate manufacturing step of the present invention's one preferred implementation in regular turn;
Fig. 3 is the circuit support plate shown in Fig. 2 E and the generalized section of chips incorporate;
Fig. 4 A to Fig. 4 C schematically shows the section of the circuit support plate of the preferred embodiment for the present invention in regular turn, wherein, and the extra metal level that forms on the surface of joint sheet and conductive junction point;
Fig. 5 A and Fig. 5 B are the generalized section of the circuit support plate of the preferred embodiment for the present invention, and wherein, conductive junction point is made outstanding downwards.
Description of reference numerals
100 electronic packing bodies, 110 circuit support plates
112 end faces, 114 bottom surfaces
116a bump pads 116b solder ball pad
120 projections, 130 chips
132 active surperficial 134 back sides
136 chip mats, 140 soldered balls
150 primers, 200 circuit support plates
202 supporting substrates, 204 first structure sheafs
206 second structure sheafs, 208 first conductive patterns
210 first conductive junction points, 212 insulation patterns
Interconnect architecture 214a conductor layer in 214 multilayers
214b dielectric layer 214c conductive blind hole
216 joint sheets, 218 plating seed layers
220 mask graphs, 222 the first metal layers
224 second metal levels, 226 mask graphs
228 mask layers, 230 second conductive patterns
232 second conductive junction points 240 are buried the formula passive block underground
302 chips, 304 conductive stud are determined
306 primers, 308 supporting layers
310 fin
Embodiment
See also Fig. 2 A to Fig. 2 E, schematically show the circuit support plate manufacture method of the present invention's one preferred implementation among the figure in regular turn.
Shown in Fig. 2 A, one supporting substrate 202 is provided, but this substrate itself has conductivity, high rigidity (high stiffness), low thermal coefficient of expansion (low CTE) and high thermal conductance characteristics such as (high thermalconductivity), therefore, the material of supporting substrate 202 for example can be iron, cobalt, nickel, copper, aluminium, titanium, tungsten, zirconium, chromium and their alloy etc., and the surface of supporting substrate 202 must have the flatness (co-planarity) of higher level, is beneficial in the subsequent handling to make on the surface of supporting substrate 202 interconnect architecture (as Reference numeral 214 among Fig. 2 D) in the multilayer of fine circuits.In addition, in order to help to clearly demonstrate present embodiment, supporting substrate 202 can be divided into first structure sheaf 204 and second structure sheaf 206 overlapped with first structure sheaf 204.
Shown in Fig. 2 B, for example in photoetching modes such as (photolithography), first structure sheaf, 204 compositions (seeing Fig. 2 A) to supporting substrate 202, to form one first conductive pattern (conductivepattern) 208, wherein first conductive pattern 208 can constitute a plurality of first conductive junction points 210, and these conductive junction points for example can array way be arranged.
Shown in Fig. 2 C, for example in printing modes such as (print), insulating material is inserted between second structure sheaf 206 and first conductive pattern 208, thereby form insulation patterns (dielectric pattern) 212. in the present embodiment, insulating material can be inserted the space that is surrounded between second structure sheaf 206 and first conductive pattern 208, to form insulation patterns 212, this figure is the negative film figure of first conductive pattern 208, and it is chimeric mutually with first conductive pattern 208, wherein, insulating material can adopt the material with high glass transition temperature (Tg) and low thermal coefficient of expansion (CTE), epoxy resin (epoxy resin) for example, polyamide resin (PI resin), the BT resin, benzene (also) cyclobutane (BenzoCycloButene, BCB), polysilicate (poly (silsequioxane)), parylene (parylene), polyarylether (poly (aryl ether) s), polynorbornene (poly (norbornene)), polyphenylene quinoxaline (poly (phenyl quinoxaline) s).
Shown in Fig. 2 D, for example on first conductive pattern 208 and insulation patterns 212, form interconnect architecture 214 in the multilayer with Layer increasing method (build-up process).Interconnect architecture 214 comprises a plurality of conductor layer 214a of composition in this multilayer, at least one dielectric layer 214b and a plurality of conductive blind hole 214c, wherein, these conductor layers 214a is overlapped on first conductive pattern 208 and the insulation patterns 212 in regular turn, each dielectric layer 214b then is disposed between the two adjacent conductor layer 214a, and these conductive blind holes 214c runs through one of described dielectric layer 214b respectively, electrically connect at least two conductor layer 214a, the common formation of these conductor layers 214a and these conductive blind holes 214c one internal circuit, the surface of this circuit interconnect architecture 214 in multilayer forms a plurality of joint sheets 216, wherein these joint sheets 216 can be formed by conductor layer 214a, or formed by conductive blind hole 214c, 216 of the joint sheets of Fig. 2 D as representative, promptly are used as joint sheet 216 with conductive blind hole 214c with the latter.In addition, the material of conductor layer 214a for example is a copper, aluminium and their alloy, and the material of dielectric layer 214b can be silicon nitride (silicon nitride) and silica (silicon oxide) etc., or has a material of high glass transition temperature (Tg) and low thermal coefficient of expansion (low CTE), epoxy resin for example, polyamide resin (PI resin), the BT resin, benzene (also) cyclobutane (BenzoCycloButene, BCB), polysilicate (poly (silsequioxane)), parylene (parylene), polyarylether (poly (aryl ether) s), polynorbornene (poly (norbornene)), polyphenylene quinoxaline (poly (phenyl quinoxaline) s).
Shown in Fig. 2 D, for example, remove second structure sheaf 206, thereby expose described first conductive junction point 210, and finish the making of circuit support plate 200 to grind (polish) or etching modes such as (etching).
Please refer to Fig. 3, this figure is the circuit support plate shown in Fig. 2 E and the generalized section of chips incorporate.In the present embodiment, chip 302 is by the mode of flip-chip in conjunction with (flip chip bonding), promptly be connected to the joint sheet 216 of circuit support plate 200, and between circuit support plate 200 and chip 302, insert primer 306, and become chip packing-body via a plurality of conductive projections 304.It should be noted that, chip 302 is except being electrically connected to circuit support plate 200 by the flip-chip bond mode, the mode of also available wire bond (wire bonding) is electrically connected to circuit support plate 200, but the latter is not shown in the accompanying drawing of present embodiment.In addition, for the radiating effect that improves chip packing-body and increase its structural strength, also can on circuit support plate 200, additionally increase a supporting layer (stiffner) 308, and fin (heat spreader) 310 is attached on chip 302 and the supporting layer 308 around chip 302.
For the ease of IC chip or other electronic building brick with surface mount technology (Surface MountTechnology, SMT) mode is assembled on the circuit support plate 200 of present embodiment, or be convenient to circuit support plate 200 and be assembled on the circuit support plate (not shown) of next level in the mode of surface mount technology (SMT), please refer to Fig. 4 A to Fig. 4 C reaches hereinafter, wherein Fig. 4 A to Fig. 4 C has schematically drawn the circuit support plate of the preferred embodiment for the present invention in regular turn, the additional metal level section that forms on the surface of its joint sheet and conductive junction point.
Shown in Fig. 4 A, this figure after Fig. 2 D, for the usefulness of follow-up plating the first metal layer 222 is provided, second structure sheaf 206 (seeing Fig. 2 D) of removable part, and form a plating seed layer 218.It should be noted that herein also can directly remove second structure sheaf 206 fully, then, form a conductive layer all sidedly and be used as described plating seed layer 218 in the surface of first conductive pattern 208 and insulation patterns 212 more for example in the mode of plating.
Shown in Fig. 4 B, on plating seed layer 218, form a mask graph 402, it exposes described first conductive junction point 210, and on the surface of these first conductive junction points 210, electroplate to form a first metal layer 222 respectively via plating seed layer 218, wherein the first metal layer 222 for example is a solder layer (solder layer) or nickel-gold layer (Ni/Au layer).It should be noted that, in the present embodiment, when forming the first metal layer 222, also can on the surface of these joint sheets 216, electroplate respectively and form second metal level 224 via the internal circuit that is electrical connected of interconnect architecture 214 in plating seed layer 218 and the multilayer, wherein, second metal level 224 for example is a solder layer or nickel-gold layer.
Shown in Fig. 4 C, after forming the described the first metal layer 222 and second metal level 224, remove mask graph 402 and expose plating seed layer 218.
For first conductive junction point 210 of Fig. 2 E can be given prominence to downwards, see also Fig. 5 A and Fig. 5 B, they are generalized sections of the circuit support plate of the preferred embodiment for the present invention, wherein, conductive junction point is made outstanding downwards.
Shown in Fig. 5 A, hookup 2D, second structure sheaf 206 away from multilayer in the one side of interconnect architecture 214 form a mask graph 226, this mask graph 226 has a plurality of mask layers 228, wherein, the position of described mask layer 228 corresponds respectively to the position of described first conductive junction point 210.
Shown in Fig. 5 B, for example remove the part of not masked figure 226 coverings of second structure sheaf 206 in etched mode, and form second conductive pattern 230, this figure has a plurality of second conductive junction points 232, these second conductive junction points 232 connect the first corresponding conductive junction point 210 respectively, make described first conductive junction point 210 structurally to stretch out via these second conductive junction points 232 respectively, and described first conductive junction point 210 and second conductive junction point 232 also can constitute the conductive junction point of spheroidal respectively, in order to the contact as the electronic carrier board that connects next level to be provided.It should be noted that; for sealer is formed on the bottom at these second conductive junction points 232; can directly utilize previous mask layer 228 (being residual mask graph 226) to be used as sealer, thereby omit the step that existing multiple tracks is made sealer.
For the elasticity on the circuit design is provided, or the demand in the coincident circuit design, shown in Fig. 2 B, after forming first conductive pattern 208, also optionally one or more modes of burying formula passive block (embedded passive component) 240 underground, for example being adhered to second structure sheaf 206 with its back side are disposed in the space that is surrounded between second structure sheaf 206 and described first conductive junction point 210.Then, shown in Fig. 2 C, when the space that is surrounded between second structure sheaf 206 and first conductive pattern 208 forms insulation patterns 212, insulation patterns 212 is buried coating underground formula passive component 240, but expose a plurality of contacts of burying formula passive component 240 underground, these contacts will be electrically connected to the internal circuit of interconnect architecture 214 in the multilayer in the step of Fig. 2 D.Therefore, as shown in Figure 3, bury formula passive component 240 underground and will be present in the chip-packaging structure shown in the figure.
In sum, the manufacture method of circuit support plate of the present invention has the following advantages:
(1) the thin and higher supporting substrate of rigidity of utilization of the present invention replaces existing dielectric sandwich layer, thus the integral thickness of attenuate circuit support plate effectively, and directly utilize supporting substrate making conductive junction point, thus can produce the circuit support plate of no dielectric sandwich layer.
(2) the present invention forms interconnect architecture in the multilayer with Layer increasing method (build-up process) on a surface of supporting substrate, so can obtain to have the circuit support plate of higher density circuit and contact.
(3) form in the multilayer interconnect architecture respectively with existing two sides at the dielectric sandwich layer and compare, the present invention only forms interconnect architecture in the single multilayer on a surface of supporting substrate, thus can reduce the winding length of circuit effectively, thus can improve electric property.
(4) with existing utilize plating line (plating line) on the joint sheet of circuit support plate, to electroplate to form little space projection, solder layer or metal surface protection layer (for example nickel-gold layer) compare; the present invention can directly utilize the supporting substrate with conductivity as plating seed layer, so can improve the current densities of circuit support plate internal circuit in manufacture process.
(5) shown in Fig. 5 A and 5B, the present invention also can directly utilize mask layer 228 to be used as the sealer of second conductive junction point, and need not form the concerned process steps of sealer extraly.
(6) when the present invention extends first conductive junction point by second conductive junction point, can directly utilize second conductive junction point circuit support plate to be connected to the circuit support plate of next level, a printed circuit board (PCB) for example, and need not additionally make conducting sphere or conductive projection again on the surface of first conductive junction point.
Though the present invention discloses as above with preferred implementation; yet described explanation is not to be limitation of the invention; any those skilled in the art are under the prerequisite that does not exceed design of the present invention and protection range; can make multiple change and retouching; therefore, protection scope of the present invention should be as the criterion with the claimed scope of appending claims.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410005942 CN1560911B (en) | 2004-02-23 | 2004-02-23 | Manufacturing method of circuit carrier plate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410005942 CN1560911B (en) | 2004-02-23 | 2004-02-23 | Manufacturing method of circuit carrier plate |
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| CN1560911A CN1560911A (en) | 2005-01-05 |
| CN1560911B true CN1560911B (en) | 2010-05-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200410005942 Expired - Lifetime CN1560911B (en) | 2004-02-23 | 2004-02-23 | Manufacturing method of circuit carrier plate |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7468545B2 (en) | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
| US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
| JP4183199B2 (en) * | 2005-12-28 | 2008-11-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor package and manufacturing method thereof |
| CN101557682B (en) * | 2008-04-07 | 2011-09-21 | 旭德科技股份有限公司 | Manufacturing method of electronic component carrier board |
| CN102915995B (en) * | 2012-11-02 | 2015-12-16 | 日月光半导体制造股份有限公司 | Semiconductor package, substrate and manufacturing method thereof |
| TWI515841B (en) * | 2013-08-02 | 2016-01-01 | 矽品精密工業股份有限公司 | Semiconductor package and method of manufacture |
| TW201931532A (en) * | 2018-01-08 | 2019-08-01 | 鈺橋半導體股份有限公司 | Leadframe substrate with electronic component incorporated therein and semiconductor assembly using the same |
| TWI703689B (en) * | 2018-07-26 | 2020-09-01 | 鈺橋半導體股份有限公司 | Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1119342A (en) * | 1994-04-26 | 1996-03-27 | 国际商业机器公司 | Electronic packages with multilayer connections |
| CN1338119A (en) * | 1999-03-11 | 2002-02-27 | 爱特梅尔股份有限公司 | Apparatus and method for an integrated circuit having high Q reactive components |
-
2004
- 2004-02-23 CN CN 200410005942 patent/CN1560911B/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1119342A (en) * | 1994-04-26 | 1996-03-27 | 国际商业机器公司 | Electronic packages with multilayer connections |
| CN1338119A (en) * | 1999-03-11 | 2002-02-27 | 爱特梅尔股份有限公司 | Apparatus and method for an integrated circuit having high Q reactive components |
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| CN1560911A (en) | 2005-01-05 |
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