CN1549451A - Fast frequency locking method and structure realized by adaptive asymmetric charge pump current mechanism - Google Patents
Fast frequency locking method and structure realized by adaptive asymmetric charge pump current mechanism Download PDFInfo
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Abstract
The invention discloses a fast frequency locking method and a structure realized by an adaptive asymmetric charge pump current mechanism, which comprises a circuit formed by a pair of frequency-dependent main current sources, a pair of (ascending and descending) frequency-dependent auxiliary current sources, a digital control circuit, a voltage control oscillator, an impedance, a frequency sampled from the output of the voltage control oscillator, a fixed reference frequency, a phase detector and the like. The difference of the present invention from the traditional charge pump circuit is that at least more than one pair of frequency dependent auxiliary current sources are added, and the auxiliary power sources are used to increase the current sources, so as to quickly raise or lower the control voltage of the voltage controlled oscillator to the frequency predetermined by the user under different power supply voltages, and then the digital control circuit of the present invention is used to achieve the purpose of quick frequency locking.
Description
Technical field
The present invention relates to fast frequency locking means and framework that the asymmetric electric charge pump of a kind of adaptability electric current mechanism realizes.
Background technology
In today that circuit design and manufacturing technology progress greatly, the processing speed of electronic circuit also with speed, therefore require a quick lock in and have between of short duration lockup period and the phase lock circuitry between return period, and when designing this quick lock in phase lock circuitry, must consider quick lock in and low noise two opposed problems, when the frequency lock of phase-locked loop is handled when becoming comparatively fast, its filter frequency range also with increase, relatively, the noise that is produced in the circuit also with increase; Otherwise, if solve aforementioned disappearance, the frequency range of filter is narrowed down in the hope of reducing noise, make that just the processing speed of phase-locked loop is relatively slack-off.
Conventional charge pump circuit as shown in Figure 1, the master current source that comprises a pair of frequency dependent, one voltage-controlled oscillator, one impedance, one sampling frequency, the circuit that assembly constituted such as one fixed frequency and phase detectors, one charging current source is provided, and be identical size with the discharging current source, so just, can make the control voltage of a voltage controlled oscillator (VCO) can be when control overtension and output frequency are too fast, one pipeline that effectively discharges is provided, control voltage is reduced, and frequency is reduced, in the process of the frequency lock of circuit integral body, produce the transient phenomenon of locking process, this frequency replaces the high and low back and forth, reaches a stationary value in a period of time rear.This is the operating principle of general conventional charge pump circuit.If the variation size of hypothesis frequency is a unknown state, imitate attitude for obtaining a best frequency locking, thereby must set charging current and the size of discharging current for equating, so just can be unlikely too fast when upwards increasing in frequency, and frequency is unlikely slow excessively when downgrading downwards.But in this traditional frequency locking structure, because of circuit still produces leakage current partly in the process of frequency locking, this leakage current has also produced interference noise to this circuit, and makes the process required time lengthening of frequency locking.
Summary of the invention
The purpose of this invention is to provide a kind of fast frequency locking means and framework of realizing with the asymmetric electric charge pump of adaptability electric current mechanism, utilize a numerical frequency lifting decision circuitry and to add that by constant current source a class frequency changes the auxiliary current source of its numerical value soon, slowly; This auxiliary current source is formed by filling auxiliary current source on one and filling auxiliary current source once, under the situation that original integrated circuit member does not significantly increase, with the locking time of minimizing frequency.
The present invention is described in detail with instantiation below in conjunction with accompanying drawing, so that the present invention is had more deep understanding.
Description of drawings
Fig. 1 is the composition Organization Chart of traditional charge pump circuit;
Fig. 2 is the composition Organization Chart of charge pump circuit of the present invention;
Fig. 3 is the control flow chart of digital control circuit of the present invention;
Fig. 4 is that clock control signal of the present invention is by the zero view that converts enable signal to;
Fig. 5 is the action of main power source of the present invention and auxiliary current source and the graph of a relation that clock control changes.
Description of reference numerals: 10～current source; 11～fixed frequency; 12～phase detectors; 13～impedance; 14～voltage-controlled oscillator; 15～sampling frequency; 20～master current source; 21～auxiliary current source; 211～upward auxiliary current source; 212～following auxiliary current source; 22～fixed frequency; 23～phase detectors; 231～upward holding wires; 232～following holding wire; 24～digital control circuit; 25～impedance; 26～voltage-controlled oscillator; 27～sampling frequency; The activation of 31～circuit; Whether 32～rising triggering signal produces; The M/N ratio A of 33～storage distributor; 34～storage (t-1) M/N ratio B the during time; Whether 35～relatively A, B value equate; 36a～reach Preset Time not? 36b～auxiliary current source (UAFDCS﹠amp about closing; DAFDCS) and counter reset; 37～relatively A＞B or A＜B; The control of 38～firing current source I (UAFDCS) goes up holding wire, and the switch of current source I (UAFDCS) cuts out; The control of 39～firing current source I (UAFDCS) is descended holding wire, and the switch of current source I (UAFDCS) cuts out; 40～when the timer timing to the scheduled time, keep timer in this scheduled time.
Embodiment
Fig. 2 is the composition Organization Chart of charge pump circuit of the present invention.This circuit comprises the master current source 20 of a pair of frequency dependent, a pair of (rising, decline) auxiliary current source 21 of frequency dependent (comprising: auxiliary current source 211 reaches auxiliary current source 212 on), one digital control circuit 24, one voltage-controlled oscillator 26, one impedance 25, one sampling frequency 27, one fixed frequency 22 and phase detectors 23, be to have increased at least the auxiliary current source 21 (present embodiment is a group) of the frequency dependent more than at least one pair of with the conventional charge pump circuit difference, and utilize this auxiliary current source 21 to make electric current strengthen (be generally the several times of master current source or tens of times more than), reaching the power supply fast rise or to drop to the frequency that the user is scheduled to, and then utilize the set digital control circuit of the present invention 24 to reach the purpose of quick lock in.And framework of the present invention comprises:
One voltage-controlled oscillator 26, in order to produce an AC signal, its frequency is proportional to the magnitude of voltage of its input control signal usually;
One master current source 20, this master current source 20 are master current source of a pair of frequency dependent;
One auxiliary current source 21, but the supply of current amount of this auxiliary current source 21 is at least greater than master current source 20;
One impedance 25, the resistance value of this impedance is according to the size setting of current source;
One digital control circuit 24 is done a judgement to incoming frequency and circuit activation, and the lock out action of control frequency; And
One phase detectors 23 can compare at a fixed frequency 22 and a sampling frequency 27 values, obtain a comparison value, and this comparison value is sent to the parameter value that a digital control circuit 24 is done action.
Please consult Fig. 2 and shown in Figure 3 simultaneously, Fig. 3 is the control flow chart for digital control circuit of the present invention, wherein a digital control circuit 24 is controlled two auxiliary current source 21 of rise and fall, no matter make frequency when circuit start, or all can be by after judging frequency change in the switching between frequency, be directed to the needed electric current of frequency change again, and lock the frequency preset value apace, again when reaching preset frequency, close this auxiliary current source 21, reaching the effect of stabilized frequency, and this digital control circuit 24 includes following treatment step:
The activation of 31～circuit;
Whether 32～rising triggering signal produces;
The M/N ratio A of 33～storage phase detectors;
34～storage (t-1) M/N ratio B the during time;
Whether do 35～relatively A, B value equate? if when equating, then execution in step 36; Otherwise, when unequal, execution in step 37;
36～whether reach Preset Time, if not, again relatively up to reaching Preset Time; If then close upper and lower auxiliary current source (UAFDCS ﹠amp; And counter reset DAFDCS);
37～relatively A＞B or A＜B, if A＞during B, then execution in step 38; If A＜and during B, execution in step 39;
The control of auxiliary current source I (UAFDCS) goes up holding wire in 38～unlatching, and the switch that will go up auxiliary current source I (UAFDCS) cuts out;
The control of auxiliary current source I (UAFDCS) is descended holding wire in 39～unlatching, and the switch that will go up auxiliary current source I (UAFDCS) cuts out;
40～when the timer timing to the scheduled time, keep timer in this scheduled time.
By above-mentioned step, the processing detailed step division of this digital control circuit is as follows:
(1) after clock (Clock) continues to be sent to circuit, comparing numerical value in fixed frequency (N) 22 with two of sampling frequency (M) 27 is under the state of fixed value, circuit by the shutdown state to enabled status, digital control circuit 24 detects this activation signal, thereby determination frequency numerical value rises by 0, digital control circuit 24 thereby the switch control that will go up auxiliary current source I (UAFDCS) 211 are given holding wire 231, and the switch that will go up auxiliary current source I (UAFDCS) 211 cuts out (Turn On), at this moment, frequency begins quick lock in; After treating that auxiliary current source I (UAFDCS) 211 affacts the Preset Time end, digital control circuit 24 just the switch open of current source I (UAFDCS) 211 (Turn Off), stablizes frequency more.
(2) when frequency stabilization, if this frequency values is F1, we select a new frequency value F 2 at desire, and during F2＞F1, must go to change fixed frequency (N) 22 and sampling frequency (M) 27, and the numerical value that makes sampling frequency (F2)/fixed frequency (F2) is greater than sampling frequency (F1)/fixed frequency (F1), whether digital control circuit 24 is risen by the comparison numerical value determination frequency of fixed frequency (N) 22 with sampling frequency (M) 27, and the control that open to go up auxiliary current source I (UAFDCS) 211 goes up holding wire 231, and the switch that will go up auxiliary current source I (UAFDCS) 211 cuts out.At this moment, frequency begins quick lock in, treats that auxiliary current source I (UAFDCS) 211 acts on to scheduled time end, and digital control circuit 24 is about to go up the switch open (Turn Off) of auxiliary current source I (UAFDCS) 211, and frequency is stablized more.
(3) when frequency stabilization, if this frequency values is F1, we select a new frequency value F 3 at desire, and during F1＞F3, must go to change fixed frequency (N) 22 and sampling frequency (M) 27, and the numerical value that makes sampling frequency (F3)/fixed frequency (F3) is less than sampling frequency (F1)/fixed frequency (F1), whether digital control circuit 24 is descended by the comparison numerical value determination frequency of fixed frequency (N) 22 with sampling frequency (M) 27, and the control that open to go up auxiliary current source I (UAFDCS) 211 is descended holding wire 232, and the switch that will go up auxiliary current source I (UAFDCS) 211 cuts out.At this moment, frequency begins quick lock in, treats that auxiliary current source I (UAFDCS) 211 acts on to scheduled time end, and digital control circuit is about to go up the switch open (Turn Off) of auxiliary current source I (UAFDCS) 211, and frequency is stablized more.
Fig. 4 and Fig. 5 are that clock control signal of the present invention is by the zero view that converts enable signal to, and the graph of a relation of the action of main power source of the present invention and auxiliary current source and clock control variation, in each n-th-trem relation n comparison diagram, circuit is done signal triggering when high logic, in the scheduled time of timer, under the dual-action by master current source and auxiliary current source, and frequency can be climbed or drop near the preset frequency point fast, go up auxiliary current source I (UAFDCS) by digital control circuit control again, and reach the purpose of quick lock in preset frequency.
The above only is preferred embodiment of the present invention, and when not limiting scope of the invention process, all equalizations of doing according to claim of the present invention change and modify, and all should still belong to protection scope of the present invention.
Claims (8)
1. the framework of the fast frequency locking that realizes of the asymmetric electric charge pump of adaptability electric current mechanism comprises:
One voltage-controlled oscillator is in order to produce an AC signal;
One master current source, this master current source are the master current source of a pair of frequency dependent;
At least one auxiliary current source, but the supply of current amount of this auxiliary current source is at least greater than master current source;
One impedance, the resistance value of this impedance is according to the size setting of current source;
One digital control circuit is judged incoming frequency and circuit activation, and the lock out action of control frequency; And
One phase detectors compare at a fixed frequency and a sampling frequency value, obtain a comparison value, and this comparison value is sent to the parameter value of a digital control circuit as action.
2. the framework of the fast frequency locking that the asymmetric electric charge pump of adaptability as claimed in claim 1 electric current mechanism realizes, wherein the ratio relation formula of the fixed frequency of these phase detectors and sampling frequency is:
(sampling frequency)/(fixed frequency)
And obtain the parameter value of digital control circuit action with above-mentioned relational expression.
3. the framework of the fast frequency locking that the asymmetric electric charge pump of adaptability as claimed in claim 1 electric current mechanism realizes, wherein these phase detectors also comprise on one holding wire and holding wire once, in order to the rising and the down maneuver of control frequency.
4. the framework of the fast frequency locking that the asymmetric electric charge pump of adaptability as claimed in claim 1 electric current mechanism realizes, wherein this auxiliary current source comprises that auxiliary current source reaches auxiliary current source on one.
5. the framework of the fast frequency locking that the asymmetric electric charge pump of adaptability as claimed in claim 1 electric current mechanism realizes, wherein this auxiliary current source size be master current source several times to tens times.
6. the method for the fast frequency locking that realizes of the asymmetric electric charge pump of adaptability electric current mechanism, wherein this digital control circuit is to comprise the following steps:
(a) circuit activation;
(b) whether the rising triggering signal produces;
(c) fixed frequency (N)/sampling frequency (M) ratio of storage distributor;
(d) store (t-1) fixed frequency (N)/sampling frequency (M) ratio the during time;
Does (e) ratio in the comparison step (c) equate with ratio in the step (d)?
(f) whether reach Preset Time, if not, again relatively up to reaching Preset Time; If then close upper and lower auxiliary current source (UAFDCS ﹠amp; And counter reset DAFDCS);
(g) ratio in the ratio＞step (d) in the comparison step (c) or the ratio in the ratio＜step (d) in the step (c);
(h) control of auxiliary current source I (UAFDCS) goes up holding wire in the unlatching, and the switch that will go up auxiliary current source I (UAFDCS) cuts out;
(i) control of auxiliary current source I (UAFDCS) is descended holding wire in the unlatching, and the switch that will go up auxiliary current source I (UAFDCS) cuts out; And
(j) when the timer timing to the scheduled time, keep timer in this scheduled time.
7. the method for the fast frequency locking that the asymmetric electric charge pump of adaptability as claimed in claim 6 electric current mechanism realizes, wherein the execution result of this step (e) is judged, if when the result equates, execution in step (f) then; Otherwise, when the result is unequal, execution in step (g).
8. the method for the fast frequency locking that the asymmetric electric charge pump of adaptability as claimed in claim 6 electric current mechanism realizes, wherein the execution result of this step (g) is judged, if when the result equates, execution in step (h) then; Otherwise, when the result is unequal, execution in step (i).
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| Application Number | Priority Date | Filing Date | Title |
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| CNA031234526A CN1549451A (en) | 2003-05-17 | 2003-05-17 | Fast frequency locking method and structure realized by adaptive asymmetric charge pump current mechanism |
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| CNA031234526A CN1549451A (en) | 2003-05-17 | 2003-05-17 | Fast frequency locking method and structure realized by adaptive asymmetric charge pump current mechanism |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101369450B (en) * | 2007-08-17 | 2011-03-16 | 财团法人工业技术研究院 | Sensing circuit and sensing method of phase change memory |
| US7933147B2 (en) | 2007-06-25 | 2011-04-26 | Industrial Technology Research Institute | Sensing circuit of a phase change memory and sensing method thereof |
| CN101719767B (en) * | 2009-11-17 | 2011-11-16 | 中国航天科技集团公司第九研究院第七七一研究所 | Phase-locked loop with quick response |
| CN102006058B (en) * | 2009-08-31 | 2012-08-29 | 安凯(广州)微电子技术有限公司 | PLL (Phase-Locked Loop) leakage current compensation circuit and PLL circuit |
| CN103078636A (en) * | 2012-12-27 | 2013-05-01 | 四川和芯微电子股份有限公司 | Phase-locked loop system |
| CN103546139A (en) * | 2012-07-12 | 2014-01-29 | 联咏科技股份有限公司 | Bias and load circuit and fast bias circuit and method |
-
2003
- 2003-05-17 CN CNA031234526A patent/CN1549451A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7933147B2 (en) | 2007-06-25 | 2011-04-26 | Industrial Technology Research Institute | Sensing circuit of a phase change memory and sensing method thereof |
| CN101369450B (en) * | 2007-08-17 | 2011-03-16 | 财团法人工业技术研究院 | Sensing circuit and sensing method of phase change memory |
| CN102006058B (en) * | 2009-08-31 | 2012-08-29 | 安凯(广州)微电子技术有限公司 | PLL (Phase-Locked Loop) leakage current compensation circuit and PLL circuit |
| CN101719767B (en) * | 2009-11-17 | 2011-11-16 | 中国航天科技集团公司第九研究院第七七一研究所 | Phase-locked loop with quick response |
| CN103546139A (en) * | 2012-07-12 | 2014-01-29 | 联咏科技股份有限公司 | Bias and load circuit and fast bias circuit and method |
| CN103078636A (en) * | 2012-12-27 | 2013-05-01 | 四川和芯微电子股份有限公司 | Phase-locked loop system |
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