CN1538524A - Split-gate flash memory unit and manufacturing method thereof - Google Patents
Split-gate flash memory unit and manufacturing method thereof Download PDFInfo
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- CN1538524A CN1538524A CNA031104762A CN03110476A CN1538524A CN 1538524 A CN1538524 A CN 1538524A CN A031104762 A CNA031104762 A CN A031104762A CN 03110476 A CN03110476 A CN 03110476A CN 1538524 A CN1538524 A CN 1538524A
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Abstract
The invention provides a flash memory unit with a separated grid and a manufacturing method thereof. The separated grid flash memory unit is characterized in that the separated grid flash memory unit is provided with a floating grid in a circular arc shape and a control grid of a side wall substructure. The arc-shaped floating gate can provide stable erasing voltage when the flash memory unit is subjected to data erasing so as to improve the reliability of the flash memory element.
Description
Technical field
The present invention relates to a kind of Frash memory in separate grids unit and preparation method thereof, relate in particular to a kind of Frash memory in separate grids unit and preparation method thereof with circular shape floating grid.
Background technology
Flash memory roughly can be divided into two types of piled grids (stacked gate) flash memory and separated grid (split gate) flash memories according to the difference of grid structure.The stack type grid flash memory cell includes floating grid (floating gate), a dielectric layer and that is used for store charge and is used for the control grid (control gate) of control data access, be stacked in regular turn on the tunnel oxide from the bottom to top, and the sidewall of above-mentioned each layer all is roughly to trim mutually.Generally speaking, though the piled grids flash memory cell does not more account for area, yet has excessively the shortcoming of erase (over erase).Frash memory in separate grids then can solve the problem of excessively erasing of piled grids flash memory.
See also Fig. 1, Fig. 1 is the cross-sectional view of an existing split gate flash cell 10.As shown in Figure 1, existing split gate flash cell 10 includes semi-conductive substrate 12, a tunnel oxide 14, a floating grid 24, a control grid 30, a drain electrode 19 and an one source pole 17.Control grid 30 extends and is located on the Semiconductor substrate 12 between floating grid 24 and the drain electrode 19 to source electrode 17 directions, forms a selection raceway groove (select channel) 20.Generating in addition between control grid 30 and the floating grid 24 has a dielectric layer 28, is generally one oxide layer/nitration case/silica layer (oxide/nitride/oxide, ONO) composite dielectric layer.Frash memory in separate grids unit 10 is when writing data, utilize hot electron (channel hot electrons, CHE) effect, to control grid 30 earlier and be connected to a high voltage, and with source ground (grounded), and then drain electrode is connected to a fixed voltage, and produce hot electron by this to inject floating grid 24 by tunnel oxide 14, reach the purpose of storage data.And carrying out data when erasing, then be to utilize Fule nuohan tunnelling (Fowler Nordheimtunneling) technology, to control grid 30 ground connection earlier or connect a negative voltage (negative biased), 19 be located at a high-voltage state and will drain, to remove the electronics that is stored in floating grid 24.
Please refer to Fig. 2 to Fig. 5, Fig. 2 to Fig. 5 is the existing method schematic diagram of making a Frash memory in separate grids unit 10.As shown in Figure 2, the manufacture method of Frash memory in separate grids unit 10 at first provides semi-conductive substrate 12, and forms a tunnel oxide 14 on Semiconductor substrate 12.
As shown in Figure 3, form a photoresist layer 16 then in the surface of tunnel oxide 14, and carry out a photoetching process,, be used for defining the position of doped region in photoresist layer 16, to form a plurality of openings.Then carry out an ion implantation technology, utilize photoresist layer 16, in Semiconductor substrate 12, to form two doped regions 22 as hard mask (hardmask).Afterwards photoresist layer 16 is removed fully, and (rapid thermal processing RTP) is activated (activation) with the dopant in the doped region 22 to utilize a rapid thermal treatment.Wherein, doped region 22 is used as the drain electrode and the source electrode of split gate flash cell respectively, and the Semiconductor substrate 12 between two doped regions 22 then is defined as the channel region 20 of split gate flash cell.
As shown in Figure 4, (low pressure chemicalvapor deposition, LPCVD) technology form a polysilicon layer (not shown) in tunnel oxide 14 surfaces next to carry out a low-pressure chemical vapor deposition.Form a photoresist layer 26 in the polysilicon layer surface then, and utilize photoetching process in photoresist layer 26, to form the pattern of a floating grid.Photoresist layer 26 with patterning carries out an anisotropic etching process as mask again, to remove polysilicon layer vertically downward up to tunnel oxide 14 surfaces, forms the floating grid 24 of Frash memory in separate grids unit.
As shown in Figure 5, after photoresist layer 26 removed fully, carry out a thermal oxidation technology subsequently, to form an ONO dielectric layer 28 of being formed by oxide layer/nitration case/silica layer in floating grid 24 surfaces.Then carry out a low-pressure chemical vapor deposition process, form a polysilicon layer (not shown) in semiconductor wafer 10 surfaces.Form another photoresist layer (not shown) in the polysilicon layer surface then, and utilize methods such as photoetching and etching to define the pattern of control grid,, form the control grid 30 of Frash memory in separate grids unit to remove the polysilicon layer of part.
Though Frash memory in separate grids can solve the problem of excessively erasing of piled grids flash memory, the shortcomings such as incomplete or the spread of voltage of erasing yet existing Frash memory in separate grids is erased.Control grid and floating grid overlapping region can be exposed the influence of aligning equipment contraposition deviation in this external manufacturing process, make to produce unsettled channel current when reading of data, influence the reliability of flash memory.
Summary of the invention
Therefore Frash memory in separate grids unit that provides a kind of tool circular shape floating grid and preparation method thereof is provided main purpose of the present invention, to solve above-mentioned prior art problems.
According to an aspect of the present invention, the stable of the voltage of erasing can be kept because of having the floating grid of a circular shape in this Frash memory in separate grids unit, and then improves the reliability of flash memory.This Frash memory in separate grids unit comprises semi-conductive substrate, includes two doped regions in this Semiconductor substrate, as the source electrode and the drain electrode of this flash memory cells; One tunnel oxide is positioned on this Semiconductor substrate; One floating grid is positioned on this tunnel oxide, and two sides of this floating grid have the profile of circular shape; One dielectric layer is covered in this floating grid surface, is used for completely cutting off this floating grid and other conductive layers; And a control grid, and this control grid is one to be positioned at the spacer structure of a side of this floating grid.
Because flash memory cells of the present invention has the floating grid of a circular shape, can make the capacitance of floating grid and control gate interpolar be difficult for change, so when carrying out the data erase operation for use, can provide uniform erasing speed, it is stable to keep the voltage of erasing, control grid of the present invention can utilize the mode of etch-back to form spacer structure simultaneously, the inaccurate problem of aligning equipment contraposition so do not expose can effectively be improved the shortcoming of prior art.
Description of drawings
Fig. 1 is the cross-sectional view of existing split gate flash cell;
Fig. 2 to Fig. 5 is the existing method schematic diagram of making a separated grid electrode type quick flashing memory cell; And
Fig. 6 to Figure 12 makes a method schematic diagram with Frash memory in separate grids unit of circular shape floating grid for the present invention.
Description of reference numerals in the accompanying drawing is as follows:
10 Frash memory in separate grids unit
12 Semiconductor substrate, 14 tunnel oxides
16 photoresist layers, 17 source electrode
19 drain electrodes, 20 channel regions
22 doped regions, 24 floating grids
26 photoresist layers, 28 ONO dielectric layer
30 control grids
100 Frash memory in separate grids unit
101 Semiconductor substrate, 102 first dielectric layers
103 second dielectric layers, 104 memory cell area
105 tunnel oxides, 106 floating grids
107 oxide layers 108 the 3rd dielectric layer
110 drain electrodes of 109 control grids
111 source electrodes
Embodiment
Please refer to Fig. 6 to Figure 12.Fig. 6 to Figure 12 makes the method schematic diagram of the Frash memory in separate grids unit 100 of a circular shape floating grid for the present invention.As shown in Figure 6, at first provide semi-conductive substrate 101, then on Semiconductor substrate 101, form one first dielectric layer 102 and second dielectric layer 103 in regular turn.Wherein Semiconductor substrate 101 is a P type silicon substrate, and first dielectric layer 102 is made up of silica, and second dielectric layer 103 is made up of silicon nitride.
As shown in Figure 7, then form a photoresist layer (not shown) in second dielectric layer surface, utilize the photoresist layer to carry out a dry ecthing and a wet etching process in regular turn as mask, remove the part of first dielectric layer 102 and second dielectric layer 103, on Semiconductor substrate 101, define a memory cell area 104, afterwards the photoresist layer is removed fully.
As shown in Figure 8, carry out a wet etching process subsequently, remove the part of first dielectric layer 102 of memory cell area 104 both sides, make remaining first dielectric layer 102 produce the side wall profile of circular shape, and carry out a UV-irradiation, to remove etching solution or moisture remaining on the Semiconductor substrate 101.Then utilize a thermal oxidation technology on Semiconductor substrate 101, to form the tunnel oxide 105 of flash memory.
As shown in Figure 9, and then utilize a low-pressure chemical vapor deposition process on tunnel oxide 105, to form a polysilicon layer (not shown), with the floating grid 106 that defines a circular shape, carry out an etch-back (etching back) technology simultaneously, remove unnecessary polysilicon layer (not shown).Wherein the circular shape of floating grid 106 can make the capacitance of floating grid and control gate interpolar be difficult for change, so have the function of the stable voltage of erasing when carrying out the data erase operation for use.
As shown in figure 10, then utilize a high density plasma CVD (HDPCVD) technology, on floating grid 106, form an oxide layer 107, to be used for isolated floating grid 106 and other conductive layers, carry out a chemico-mechanical polishing (CMP) technology simultaneously and remove partial oxidation layer 107, with the thickness of controlled oxidation layer 107.Simultaneous oxidation layer 107 also provides the control grid of definition spacer structure in the subsequent technique.
As shown in figure 11, carry out a dry etching process and remove second dielectric layer 103 of memory cell area both sides, carry out a two-stage etching technology again, at first utilize a dry etching process to remove first dielectric layer 102 of floating grid 106 both sides, and then utilize a wet etching process, semiconductor substrate 101 is soaked in the hydrofluoric acid of dilution to remove first dielectric layer 102 of tunnel oxide 105 both sides, avoids floating grid 106 and tunnel oxide 105 to cause the situation of excessive undercutting (undercut) and influence the flash memory normal operation.
As shown in figure 12, utilize oxide layer 107 as a platform, deposit in regular turn one by oxide layer/nitration case/silica layer the 3rd dielectric layer 108 and the polysilicon layer (not shown) jointly formed, carry out an etch back process subsequently and remove the polysilicon layer of part, define the control grid 109 of a spacer structure with a side, and make rough the trimming of height of spacer structure in the height of oxide layer 107 in floating grid 106 and oxide layer 107.After control grid 109 is finished, utilize an ion implantation technology again and on Semiconductor substrate 101, form two n type doped regions, and utilize a rapid thermal treatment that the dopant in the doped region is activated, define the drain electrode 110 and source electrode 111 of flash memory cells 100 respectively, finish the making of flash memory cells 100.
Compared to existing Frash memory in separate grids unit and preparation method thereof, Frash memory in separate grids of the present invention unit has the floating grid of a circular shape, the floating grid of this circular shape not only has the characteristic of easy control on technology, and when carrying out more providing uniform erasing speed when data are erased action, the function of voltage of erasing of playing stably is effectively improved the shortcoming of existing Frash memory in separate grids.In addition, Frash memory in separate grids manufacture method provided by the invention utilizes an insulating oxide to define the pattern of the control grid of spacer structure, can solve the inaccurate problem of prior art exposure aligning.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (17)
1. Frash memory in separate grids unit with circular shape floating grid includes:
Semi-conductive substrate includes two doped regions in this Semiconductor substrate, as the source electrode and the drain electrode of this flash memory cells;
One tunnel oxide is positioned on this Semiconductor substrate;
One floating grid is positioned on this tunnel oxide, and two sides of this floating grid have the profile of circular shape;
One dielectric layer is covered in this floating grid surface, is used for completely cutting off this floating grid and other conductive layers; And
One control grid, this control grid is one to be positioned at the spacer structure of a side of this floating grid.
2. flash memory cells as claimed in claim 1, wherein this Semiconductor substrate is a P type silicon substrate.
3. flash memory cells as claimed in claim 1, wherein those doped regions are n type doped regions.
4. flash memory cells as claimed in claim 1, wherein this dielectric layer comprises an ONO layer of being made up of jointly native oxide/nitration case/silica layer and is located between this floating grid and this control grid.
5. flash memory cells as claimed in claim 1, wherein this dielectric layer comprises an oxide layer and is covered in this floating grid top, and the rough height that trims in this oxide layer of the height of this spacer structure.
6. method of making the Frash memory in separate grids unit of circular shape floating grid, this method includes the following step:
Semi-conductive substrate is provided;
On this Semiconductor substrate, form one first dielectric layer and one second dielectric layer in regular turn;
Remove this first dielectric layer of part and this second dielectric layer, on this Semiconductor substrate, to define a memory cell area;
Carry out an etch process and remove this first dielectric layer of part of these memory cell area two sides, so that remaining this first dielectric layer has the circular shape side wall profile;
On this Semiconductor substrate of this memory cell area, form a tunnel oxide;
Deposition one first polysilicon layer on this tunnel oxide;
Carry out an etch back process and remove this first polysilicon layer of part, in this memory cell area, to form a circular shape floating grid;
On this floating grid, form an oxide layer;
Remove this second dielectric layer and this first dielectric layer of these memory cell area two sides in regular turn;
Deposit one the 3rd dielectric layer and one second polysilicon layer in regular turn; And
This second polysilicon of removing part is to define the control grid of a spacer structure in this memory cell area one side.
7. method as claimed in claim 6, wherein this Semiconductor substrate is a P type silicon substrate.
8. method as claimed in claim 6, wherein this first dielectric layer is silicon dioxide (SiO
2).
9. method as claimed in claim 6, wherein this second dielectric layer is silicon nitride (SiN).
10. method as claimed in claim 6, wherein this etch process is an isotropism wet etching process.
11. method as claimed in claim 10, wherein this method includes in addition after this wet etching process and carries out a UV-irradiation to remove on this Semiconductor substrate remaining moisture content or etching solution.
12. method as claimed in claim 6, wherein this tunnel oxide utilizes a thermal oxidation technology to finish.
13. method as claimed in claim 6, wherein this method includes in addition and utilizes an ion implantation technology and a rapid thermal treatment (RTP) to form two n type doped regions on this Semiconductor substrate, as the source electrode and the drain electrode of this flash memory cells.
14. method as claimed in claim 6, wherein this oxide layer utilizes a high density plasma CVD (HDPCVD) technology to form.
15. method as claimed in claim 6, the wherein rough height that trims in oxide layer of the height of this spacer structure.
16. method as claimed in claim 14, wherein this method is after this high density plasma CVD technology, and other comprises and utilizes a chemico-mechanical polishing (CMP) technology to remove this oxide layer of part.
17. method as claimed in claim 6, wherein this method utilizes a two-stage etching technology to remove this first dielectric layer of these memory cell area two sides, and this two-stage etching technology comprises a dry etching process and a wet etching process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031104762A CN1302553C (en) | 2003-04-16 | 2003-04-16 | Split gate flash memory cell and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031104762A CN1302553C (en) | 2003-04-16 | 2003-04-16 | Split gate flash memory cell and manufacturing method thereof |
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| CN1538524A true CN1538524A (en) | 2004-10-20 |
| CN1302553C CN1302553C (en) | 2007-02-28 |
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| CNB031104762A Expired - Fee Related CN1302553C (en) | 2003-04-16 | 2003-04-16 | Split gate flash memory cell and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101303889B (en) * | 2007-05-09 | 2010-06-02 | 旺宏电子股份有限公司 | Memory cell and method for manufacturing nonvolatile device thereof |
| CN108648777A (en) * | 2018-05-10 | 2018-10-12 | 上海华虹宏力半导体制造有限公司 | The program timing sequence circuit and method of double separate gate flash memories |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6133098A (en) * | 1999-05-17 | 2000-10-17 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic flash memory |
| US6313498B1 (en) * | 1999-05-27 | 2001-11-06 | Actrans System Inc. | Flash memory cell with thin floating gate with rounded side wall, and fabrication process |
| KR100311049B1 (en) * | 1999-12-13 | 2001-10-12 | 윤종용 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| US6403494B1 (en) * | 2000-08-14 | 2002-06-11 | Taiwan Semiconductor Manufacturing Company | Method of forming a floating gate self-aligned to STI on EEPROM |
| TW480676B (en) * | 2001-03-28 | 2002-03-21 | Nanya Technology Corp | Manufacturing method of flash memory cell |
| JP2002324859A (en) * | 2001-04-26 | 2002-11-08 | Nec Kansai Ltd | Flash memory and its manufacturing method |
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2003
- 2003-04-16 CN CNB031104762A patent/CN1302553C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101303889B (en) * | 2007-05-09 | 2010-06-02 | 旺宏电子股份有限公司 | Memory cell and method for manufacturing nonvolatile device thereof |
| CN108648777A (en) * | 2018-05-10 | 2018-10-12 | 上海华虹宏力半导体制造有限公司 | The program timing sequence circuit and method of double separate gate flash memories |
| CN108648777B (en) * | 2018-05-10 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Programming sequential circuit and method of double-separation gate flash memory |
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| CN1302553C (en) | 2007-02-28 |
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Granted publication date: 20070228 Termination date: 20100416 |