CN1523763A - Method and system capable of synchronizing clock signal sources of semiconductor components - Google Patents

Abstract

A method for synchronizing clock signal source of each semiconductor module includes assigning a semiconductor module with clock signal source with lowest frequency as main module, calibrating each clock signal source in it to zero, outputting the lowest clock signal source of main module calibrated to zero to each slave module for synchronizing output of clock signal source of each slave module, setting a phase checker in each semiconductor module for ensuring clock synchronization between each semiconductor module and in each semiconductor module by using said phase checker.

Description

Method and system capable of synchronizing clock signal sources of semiconductor components

technical field

The present invention relates to a clock synchronization mechanism, in particular, a method and system for synchronizing the clock signal sources of each semiconductor component, which uses a master-slave configuration and cooperates with the use of a phase checker to make the clocks of each semiconductor component synchronized and correct Output the required multiplied clock signals to ensure the reliability of the system operation.

Background technique

At present, most of the clock synchronization designs are designed for the clock of a single chip. For example, in U.S. Patent No. 5,999,025 and U.S. Patent No. 6,304,582, the former synchronizes an external clock signal with a voltage-controlled oscillator clock signal in a chip, while the latter synchronizes each multiplied clock signal in a chip with a The oscillator clock signal is synchronized. Therefore, there is a lack of processing mechanism for clock synchronization between multiple chips, especially for the processing mechanism of clock synchronization between semiconductor components, wherein the clock signal source is a DLL (delay locked loop, delay locked loop) circuit or DCM (digital clockmanager, digital clock manager).

Contents of the invention

Therefore, an object of the present invention is to provide a method and system capable of synchronizing clock signal sources of various semiconductor components, which uses a master-slave configuration configuration to accurately align each clock signal source generated by a DLL or DCM. ), so that each semiconductor component or chip can be synchronized at the same time.

The present invention provides a method capable of synchronizing clock signal sources of various semiconductor components, comprising the following steps:

(a) The clock generators inside multiple semiconductor components generate multiple clock signal sources; (b) When the multiple clock signal sources generated by each clock generator are stable, specify the clock signal source with the lowest frequency among the multiple semiconductor components A semiconductor component of the main component is used as a main component, and the remaining semiconductor components are slave components; (c) specifying the lowest frequency clock signal source of the main component as a reference clock signal source; (d) according to the reference clock signal source, to Each clock signal source inside the main component performs a phase alignment check, so that each clock signal source inside the main component generates clock synchronization with the reference clock signal source to output a return-to-zero signal; (e) according to the return-to-zero signal, to The lowest clock signal source inside the slave device performs a phase alignment check so that the lowest clock signal source of the master device is clocked synchronously with the lowest clock signal source of each slave device to output a calibration signal respectively; and (f) according to each slave device Calibration signal, each internal clock signal source is checked for phase alignment, so that each clock signal source inside each slave component is clock-synchronized with the corresponding lowest clock signal source inside each slave component, thus completing each semiconductor component clock synchronization.

The present invention also provides a system capable of synchronizing clock signal sources of various semiconductor components, comprising: a first semiconductor component having a phase checker and a clock capable of generating multiple clock signal sources including the lowest frequency clock signal source generator, wherein the phase checker performs phase alignment according to the lowest frequency clock signal source, so that the multiple clock signal sources of the first semiconductor component generate clock synchronization, thereby outputting a return-to-zero signal; and a plurality of second semiconductor components Components respectively having an external phase checker, an internal phase checker and a clock generator capable of generating a multi-clock signal source including an alignment clock signal source, wherein the external phase checker performs according to the return-to-zero signal phase alignment, so that the lowest clock signal source is synchronized with the phase of the alignment clock signal source, and output a calibration signal to the internal phase checker to perform phase alignment, so that multiple clock signals in each second semiconductor device The sources respectively generate clock synchronization, thus achieving clock synchronization of all semiconductor components.

The method and system for synchronizing the clock signal sources of each semiconductor component provided by the present invention uses a master-slave configuration, designates a semiconductor component with the lowest rate clock signal source as the main component, and checks the clock signal in it using a phase After the calibration and zeroing of the device, the lowest clock signal source of the main component that has been calibrated and zeroed is output to the external phase checker of each slave component to obtain the clock synchronization of the clock signal source of each semiconductor component. Then, use The internal phase checker of each slave component obtains the clock synchronization of each internal clock signal source, so as to correctly output the required multiplied clock signals to the internal circuits of each semiconductor component.

Description of drawings

In order to make the above-mentioned and other purposes, features, and advantages of the present invention more obvious, a preferred embodiment is specifically cited below, together with the accompanying drawings, and described in detail as follows:

Fig. 1 is the block diagram that the present invention has the semiconductor component clock synchronization configuration mode of master-slave configuration;

Figure 2 is an internal block diagram of the main components specified in Figure 1 of the present invention;

Fig. 3 is the internal block diagram of any slave assembly in Fig. 1 of the present invention;

Fig. 4 is the internal block diagram of the delay locked loop clock generator in Fig. 2 and Fig. 3;

Fig. 5 is an example of a phase checker of the present invention;

Fig. 6 is a sequence diagram of an external phase checker of the present invention;

Fig. 7 is a timing diagram of an internal phase checker of the present invention;

Fig. 8 is a flowchart of the operation of the present invention;

Fig. 9 is a further flow chart of clock synchronization generated by each clock source inside the main components in Fig. 8 according to the present invention;

FIG. 10 is a further flow chart of generating clock synchronization between the slave component and the master component in FIG. 8 according to the present invention;

FIG. 11 is a further flowchart of clock synchronization generated by each clock source inside the slave component in FIG. 8 according to the present invention.

[Symbol Description]

10: Internal circuit of semiconductor components;

11-14: Semiconductor component clock circuit;

31: external phase checker;

32: internal phase checker;

41: variable delay line;

43: control logic circuit;

42: Clock distribution network;

51, 52: D-type flip-flop;

53: state machine;

111, 121, 131, 141: clock generating circuits;

112, 122, 132, 142: phase checker;

331, 332: DLLs.

Detailed ways

The same symbol system refers to the same component throughout.

FIG. 1 is a block diagram of a clock synchronization configuration of semiconductor components with a master-slave configuration according to the present invention. Here, four Field Programmable Gate Arrays are used as an example for illustration. However, the applicable semiconductor components and the quantity are not limited to four Field Programmable Gate Arrays, and can be any number of other semiconductor components, for example, ten an application specific integrated circuit.

As shown in FIG. 1 , the clock circuit of each FPGA includes two main functional block diagrams, which are phase checkers 111 , 121 , 131 , 141 and clock generators 112 , 122 , 132 , 142 . The clock generators 112 , 122 , 132 , and 142 respectively include some delay-locked loops or digital clock managers as required clock signal sources. In addition, the phase checker will check whether the rising or falling edges of the above clocks are aligned, and when the clocks are found to be misaligned (unsynchronized), a reset signal, here reset11-reset14, is issued to reset the clock generator , reissue the clock output signal. Among them, the FPGA that will contain the lowest rate clock signal source will be designated as the primary component, here 11, and the remaining FPGA components will be designated as slave components, here 12-14, to use the zeroed primary component to output the reference clock CLKREF, to synchronize the clocks of the various semiconductor components. Now citing the delay locked loop, it will be further explained below.

FIG. 2 is an internal block diagram of the main components 11 in FIG. 1 of the present invention. In FIG. 2 , the clock generator 112 of the main component 11 is further composed of multiple DLL components. As shown in FIG. 2, in the main component 11, the zeroing operation must be performed first, that is, the phase checker 111 is first used to determine the rising edge of the output clock signal source CLKREF of the clock generator 112, clkf ₁ -clkf _n or Whether the falling edge has been aligned, if it is found that it is not aligned, the phase checker 111 will send a reset signal reset11, so that the clock generator 112 re-sends each clock signal source to obtain the rising or falling edge of the phase alignment, and completes the reset. zero action. After the clock signal sources in the main component 11 have been aligned, the phase checker 111 will send out a reset clock signal (aligned clock signal) Phase-OK, and the aligned lowest frequency clock signal source will be regarded as each slave component The reference clock signal source CLKREF for calibration is output to the phase checkers 121, 131, 141 of the slave components 12-14, so as to obtain the clock synchronization of each component. The remaining frequency clocks are provided to the FPGA internal circuit 10 connected thereto.

Similarly, FIG. 3 is an internal block diagram of any slave component in FIG. 1 of the present invention. In FIG. 3 , any slave component 12, 13 or 14 includes a clock generator 33 composed of a plurality of DLL components and a clock generator 33 composed of an external phase checker 31 and an internal phase checker 32. Phase checker 121 , 131 or 141 . As shown in Figure 3, each of the slave components 12, 13 or 14 has two checkers 31, 32: first use the external phase checker 31 to obtain the local lowest frequency clock signal source clkf _lowest and the lowest frequency clock signal from the master component 11 The source CLKREF clock is synchronized, and then the external phase checker 31 sends a calibration signal Phase-In-OK to the internal phase checker 32, so that the calibration signal Phase-In-OK is aligned with other local clock signal sources clkf ₁ -clkf _n , Generate clock synchronization to correctly provide each clock signal source generated by each DLL for use by the connected FPGA internal circuit. In addition, if the local lowest frequency clock signal source clkf _lowest is not synchronized with the lowest frequency clock signal source CLKREF clock from the main component 11, the external phase checker 31 will send a reset signal Reset31 to the local lowest frequency clock signal source clkf The clock generator 331 of _{the lowest} is to regenerate the clock signal, and if the calibration signal Phase-In-OK does not produce clock synchronization with other local clock signal sources f ₁ -f _n , the internal checker 32 will send a reset The signal Reset32 is sent to the clock generator 332 of other local clock signal sources clkf ₁ -clkf _n to regenerate the clock signal.

The internal block diagram of the DLL components shown in Figures 2 and 3 is further shown in Figure 4 . As shown in FIG. 4 , a DLL component is basically composed of a variable delay line 41 , a clock distribution network 43 and a control logic circuit 42 . The variable delay line 41 delays an external input clock CLK for a period of time and outputs CLKOUT, and the clock distribution network 42 converts the clock CLKOUT into the required frequency clock signal source Base-fn, transmits it to the required related circuits and feeds it back to the control logic circuit 43 . The control logic circuit 43 compares whether the clock rising edges of the signals CLK and CLKFB are aligned, and outputs the comparison result CMP to the variable delay line 41, so as to adjust the delay line to align the clock rising edges of the signals CLK and CLKFB and DLL is until locked. In this way, the clock delay phenomenon between the input clock CLK and the load can be eliminated, thereby achieving clock synchronization. The above-mentioned variable delay line can be configured using a voltage-controlled delay circuit.

Fig. 5 is an example of a phase checker of the present invention. In FIG. 5 , for convenience of illustration, the phase checker only includes two D-type flip-flops 51 , 52 and one FSM (finite state machine, finite state machine) 53 . In practice, the number of configurations of D-type flip-flops depends on the required clock signal frequency. Basically, one D-type flip-flop is required for one clock signal frequency. As shown in Figure 5, when the clock line is logic 0, a frequency clock signal fn and a minimum frequency clock signal flowest are respectively input and transmitted to the output terminals of components 51 and 52 to output sampling signals CLKSAMPLE1 and CLKSAMPLE2 to the components 53 to perform a phase check. Wherein, in the phase checker of the main component, the lowest frequency clock signal flowest represents the signal CLKREF, and the signal phase-ok represents the zero return signal Phase-OK; in the external phase checker of a slave component, the lowest frequency clock The signal flowest represents the signal CLKREF, and the signal phase-ok represents the calibration signal Phase-In-OK; and in the internal checker of the slave component, the lowest frequency clock signal flowest represents the local lowest frequency clock signal clkf _lowesr of the slave component The signal phase-ok represents the zeroing signal Phase-OK. The timing of the internal and external phase checker is further described below.

Figure 6 is a timing diagram of an external phase checker. Fig. 7 is a timing diagram of an internal phase checker. As shown in Figure 6, in each falling edge of the local input clock CLK, the phase checker checks whether the lowest frequency clocks (marked with a circle) CLKREF and clkf _lowest of both the slave component and the master component have the same value, If the values of the two are found to be different, a reset signal Reset is output to re-input the lowest clock signal source of the two to recalibrate the two clock signal sources. When the values of the two lowest clock signal sources are the same, it means that the master device 11 has been zeroed or the phase of the connected slave device has been calibrated. At this time, as shown in FIG. 7 , the external checker will take the calibrated local lowest clock signal source (aligned clkf _lowest ) as a calibration signal Phase-In-OK, and input it to the internal phase checker to perform the operation described in FIG. 6 . The calibration steps mentioned above make the local frequency clock signal sources provided to the internal circuits of the FPGA calibrated, here f ₁ -f ₃ , so as to obtain the clock synchronization of the semiconductor components.

Fig. 8 is a flowchart of the operation of the present invention. As shown in Figure 8, the clock generators inside a plurality of semiconductor components generate multiple clock signal sources (S1); when the multiple clock signal sources generated by each clock generator are stable, specify the one with the lowest frequency among the multiple semiconductor components A semiconductor component of the clock signal source is used as a main component, and all the other components are slave components (S2); the lowest frequency clock signal source of the main component is designated as a reference clock signal source (S3); according to the reference clock signal source , performing a phase alignment check on each clock signal source inside the main component, so that each clock signal source inside the main component is synchronized with the reference clock signal source to generate a return-to-zero signal (S4); according to the return-to-zero signal , perform a phase alignment check on the lowest clock signal source inside the slave components, so that the lowest clock signal source of the master component and the lowest clock signal source of each slave component generate clock synchronization to generate an alignment signal respectively (S5); The alignment signal of the slave component performs a phase alignment check on each clock signal source inside it respectively, so that each clock signal source inside each slave component is clock-synchronized with the lowest clock signal source inside each corresponding slave component ( S6), thus completing the clock synchronization of the semiconductor components.

In the above-mentioned step S4, the step shown in FIG. 9 is further included: the phase checker of the main component is triggered by the rising edge or falling edge of an external input clock signal source, and each internal clock signal source is sampled for alignment comparison (S41 ); if all the phases are aligned, then send the reset signal Phase-OK to notify each slave component (S42); otherwise, send a reset signal reset to regenerate the multi-clock signal source and re-execute the above Step of phase alignment (S43).

In above-mentioned step S5, further comprise the step shown in Figure 10: whether the external phase checker of slave component checks the lowest frequency clock signal source of main component has sent this return-to-zero signal (S51); When receiving this return-to-zero signal and When the corresponding clock signal sources from each slave component are stable, the external phase checkers perform phase alignment checks (S52); if all phases are aligned, the calibration signal Phase-In-OK is sent out respectively to Notify the corresponding slave components that the lowest clock signal source of the main component is aligned with the lowest clock signal source of the corresponding slave component to generate clock synchronization (S53); otherwise, a reset signal reset is sent respectively to Regenerate the lowest clock signal source multi-clock signal source corresponding to the slave component and re-execute the above step of phase alignment (S54).

In the above-mentioned step S6, the steps shown in Fig. 11 are further included: when the internal phase checkers in each slave assembly receive the calibration signal and each clock signal source is stable (S61), the internal phase checkers perform phase alignment respectively. Alignment check (S62); if all phases are all aligned, then send out the reset signal Phase-OK respectively, to notify each clock signal source phase in the corresponding slave component that the phases are aligned, and clock synchronization is generated, thus achieving The clock synchronization of each semiconductor component (S63); otherwise, then send a reset signal reset respectively, to regenerate multiple clock signal sources outside the lowest clock signal source in each slave component and re-execute the above-mentioned step of phase alignment (S64) .

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make changes and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined in the appended claims.

Claims (9)

1. a method capable of synchronizing clock signal sources of different semiconductor components comprises the following steps:

(a) a plurality of semiconductor subassembly clock internal generators produce the multi-clock signal source;

(b) when stablize in the multi-clock signal source that each clock generator produced, to specify in these a plurality of semiconductor subassemblies, the semiconductor assembly with low-limit frequency signal source of clock is as a primary clustering, and all the other semiconductor subassemblies then are the subordinate assembly;

(c) specify the low-limit frequency signal source of clock of this primary clustering as a reference clock signal source;

(d) according to this reference clock signal source, each signal source of clock excute phase of primary clustering inside is aimed at inspection, make each signal source of clock of primary clustering inside and this reference clock signal source produce clock synchronization, to export a rz signal;

(e) according to this rz signal, the minimum signal source of clock excute phase of subordinate component internal is aimed at inspection, make the minimum signal source of clock of primary clustering and the minimum signal source of clock of each subordinate assembly produce clock synchronization, to export a calibrating signal respectively; And

(f) according to the calibrating signal of each subordinate assembly, respectively each signal source of clock excute phase of its inside is aimed at and checked, make each signal source of clock and the corresponding minimum signal source of clock of each subordinate component internal of each subordinate component internal produce clock synchronization, thereby finish the clock synchronization of each semiconductor subassembly.

2. method capable of synchronizing clock signal sources of different semiconductor components as claimed in claim 1, wherein, these a plurality of semiconductor subassemblies use FPGA (Field Programmable Gate Array, field programmable gate array) or ASIC (Application Specific Integrated Circuit, application-specific integrated circuit (ASIC)).

3. method capable of synchronizing clock signal sources of different semiconductor components as claimed in claim 1, wherein, this clock generator uses DLL (delay locked loop, delay lock loop) or DCM (digital clockmanager, digital dock manager).

4. method capable of synchronizing clock signal sources of different semiconductor components as claimed in claim 1, wherein, in step (d), further comprise the following steps: (d1) via the rising edge in an outside input clock signal source or the phase detector of trailing edge triggering primary clustering, each inner signal source of clock of sampling carries out phase alignment; (d2) if all phase places are all aimed at, then send described rz signal, to notify each subordinate assembly; (d3) otherwise, if the phase place misalignment is arranged, then send a reset signal, to produce the multi-clock signal source again and to re-execute the phase alignment step of above-mentioned (d1).

5. method capable of synchronizing clock signal sources of different semiconductor components as claimed in claim 1, wherein, in step (e), comprise the following steps: that further the outside phase detector in (e1) each subordinate assembly checks whether the low-limit frequency signal source of clock of primary clustering has sent described rz signal; (e2) when receiving described rz signal and having stablized from corresponding each signal source of clock of each subordinate component internal, outside phase detector excute phase is separately aimed at and is checked; (e3) if all phase places are all aimed at, then send described calibrating signal respectively, to notify corresponding each subordinate assembly, the minimum signal source of clock of its primary clustering is aimed at the minimum signal source of clock phase place of corresponding subordinate assembly, produces clock synchronization; (e4) otherwise, if the phase place misalignment is arranged, then send a reset signal respectively, with minimum signal source of clock multi-clock signal source that produces corresponding subordinate assembly again and the phase alignment step that re-executes above-mentioned (e1).

6. method capable of synchronizing clock signal sources of different semiconductor components as claimed in claim 1, wherein, in step (f), further comprise the following steps: in (f1) each subordinate assembly an inner phase detector inspection whether the described visual examination device of each subordinate assembly sent described calibrating signal; (f2) when receiving flexible calibrating signal and stablize from corresponding each signal source of clock of each subordinate component internal, inner phase detector excute phase is separately aimed at inspection; (f3) if all phase places are all aimed at, then send described rz signal respectively, aim at, produce clock synchronization, thereby reach the clock synchronization of each semiconductor subassembly to inform each the signal source of clock phase place in the corresponding subordinate assembly separately; (f4) otherwise, if the phase place misalignment is arranged, then send a reset signal respectively, to produce the outer multi-clock signal source of minimum signal source of clock in each subordinate assembly again and to re-execute the phase alignment step of above-mentioned (f1).

7. system capable of synchronizing clock signal sources of different semiconductor components comprises:

One first semiconductor subassembly, it has the clock generator that a phase detector and can produce the multi-clock signal source that comprises the low-limit frequency signal source of clock, wherein, described phase detector carries out phase alignment according to this low-limit frequency signal source of clock, make the multi-clock signal source of this first semiconductor subassembly produce clock synchronization, thereby export a rz signal; And

A plurality of second semiconductor subassemblies, has an outside phase detector respectively, one inner phase detector and one can produce the clock generator of a pair of punctual clock signal source in interior multi-clock signal source, wherein, this outside phase detector carries out phase alignment according to this rz signal, make this minimum signal source of clock aim at the Phase synchronization of signal source of clock with this, and export a calibrating signal to this inside phase detector, to carry out phase alignment, the multi-clock signal source in each second semiconductor subassembly that makes produces clock synchronization respectively, thereby reaches the clock synchronization of all semiconductor subassemblies.

8. system capable of synchronizing clock signal sources of different semiconductor components as claimed in claim 7, wherein, described semiconductor subassembly is a field programmable gate array or an application-specific integrated circuit (ASIC).

9. method capable of synchronizing clock signal sources of different semiconductor components as claimed in claim 1, wherein, described clock generator is a delay lock loop or a digital dock manager.

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