CN1505248A - Charge pumping circuit with clock pulse voltage doubling and method thereof - Google Patents

Abstract

A charge pumping circuit comprising: at least one booster circuit, the booster circuit is connected in series, and the booster circuit has a power supply end, a boost end and an output end separately; and at least one voltage doubling circuit, which is respectively provided with an input end, a first output end and a second output end, wherein the voltage doubling circuits are connected in series through the second output ends, the input end of the first voltage doubling circuit is electrically connected with a clock pulse signal, the first output end outputs a first clock pulse signal, the second output end outputs a second clock pulse signal, the first clock pulse signal is a voltage doubling signal of the second clock pulse signal, and the first output ends of the voltage doubling circuits are respectively electrically connected with the boosting ends of the boosting circuits. The invention utilizes the voltage doubling circuit to convert and output the voltage of a clock pulse signal, and increases the voltage of the clock pulse signal so as to improve the voltage of a node of a connecting node of the booster circuit, so that the charge pumping circuit can provide a stable output voltage.

Description

Electric charge pumping circuit and method with clock pulse multiplication of voltage

(1) technical field

The present invention is about a kind of electric charge pumping circuit and method with clock pulse multiplication of voltage.

(2) background technology

Electric charge pumping circuit is to produce a higher output voltage under normal input voltage.And electric charge pumping circuit is applied in some non-volatile (Non-Volatile) memories usually, for example flash memory (Flashmemory), EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM memory), storage capacity by electric charge in the control floating gate (FloatingGate), to determine transistorized opening or closing, make flash memory (Flash memory) can finish three kinds of basic manipulation modes, that is read (byte or word), write the operator scheme of (byte or word) and erase (one or more storage space).

Seeing also Fig. 1, is the circuit diagram of the gloomy electric charge pumping of known level Four Dick circuit (four-stage Dickson chargepump circuit).As shown in Figure 1, this electric charge pumping circuit 100 comprises four booster circuits 101,102,103,104, this booster circuit 101,102,103,104th, have a power source supply end, a boost terminal 110,111 respectively, 112,113 and one output, and this booster circuit 101,102,103,104th, be connected in series with an input node 105 and an output node 109, the mutual point of contact of this booster circuit forms four voltage nodes 106,107,108 respectively.In addition, this booster circuit 101,102,103,104 comprise passage CMOS (Complementary Metal Oxide Semiconductor) (MOS) transistor, and a base stage of this passage CMOS transistor is to be electrically connected a collector electrode to form a diode-coupled transistor (diode-coupledtransistor) 118,119,120,121.

In the gloomy electric charge pumping of this Dick circuit 100, this booster circuit 101 comprises an electric capacity 114, and an end of this electric capacity 114 is to receive a clock pulse signal CLK for this boost terminal 110, and the other end is to be electrically connected to this input node 105.This booster circuit 102 comprises an electric capacity 115, and an end of this electric capacity 115 is inversion signals that receive this clock signal CLK for this boost terminal 111, and the other end is to be electrically connected to this input node 106.This booster circuit 103 comprises an electric capacity 116, and an end of this electric capacity 116 is to receive this clock signal CLK for this boost terminal 112, and the other end is to be electrically connected to this input node 107.This booster circuit 104 comprises an electric capacity 117, and an end of this electric capacity 117 is these inversion signals that receive this clock signal CLK for this boost terminal 113, and the other end is to be electrically connected to this input node 108.And this diode-coupled transistor 118 is to be operating as a single-way switch, the store charge of this electric capacity 114 is sent to this electric capacity 115, in like manner, this diode-coupled transistor 119 is operating as a single-way switch, the store charge of this electric capacity 115 is sent to this electric capacity 116, this diode-coupled transistor 120 is operating as a single-way switch, the store charge of this electric capacity 116 is sent to this electric capacity 117, this diode-coupled transistor 121 is operating as a single-way switch, and the store charge of this electric capacity 117 is sent to an output capacitance Cout.

The gloomy electric charge pumping of this Dick circuit 100 also comprises a diode-coupled transistor 122, and this diode-coupled transistor 122 is to be electrically connected on an input voltage V _DDAnd between this input node 105, this diode-coupled transistor 122 is to be operating as a single-way switch, with this input voltage V _DDElectric charge be sent to this electric capacity 114.

Yet whether electric charge can be sent to next stage depends on that whether a voltage difference of this power source supply end and this output in this booster circuit is greater than the transistorized critical voltage of this diode-coupled (thresholdvoltage) value.In addition, this electric charge pumping circuit is to utilize the inversion signal of this clock signal CLK and this clock signal CLK to increase the size of this node voltage of this node.For the gloomy electric charge pumping of n level Dick circuit, one output voltage V out is represented by following equation:

$V_{\mathrm{out}}=V_{\mathrm{DD}}+\mathrm{n\ΔV}-\underset{k=1}{\overset{n}{\mathrm{\Σ}}}{V}_{\mathrm{th}}\left(V_k\right)$

$\mathrm{\ΔV}=V_{\mathrm{DD}}\frac{C}{C+C_s}-\frac{I_{\mathrm{out}}}{f(C+C_s)}$

Wherein, V _DDBe a voltage swing of this clock signal, Cs is a stray capacitance value of each node, and f is a frequency values of clock signal, and Iout is an output current value of this electric charge pumping circuit.

Therefore, be Δ V＞V for the necessary condition that makes this electric charge pumping circuit normal operation _Th

Yet because transistorized pedestal effect (Body Effect) can increase the size of this critical voltage, and when the voltage swing of input voltage was lower than 1.8V, this clock signal can't increase this enough node voltage to overcome critical voltage.

(3) summary of the invention

Main purpose of the present invention is to provide a kind of electric charge pumping circuit and a kind of method of controlling electric charge pumping circuit with clock pulse multiplication of voltage, so that clock signal increases this enough node voltage to overcome critical voltage.

Electric charge pumping circuit according to an aspect of the present invention is characterized in, comprising: at least one booster circuit, and this booster circuit is to be connected in series, and this booster circuit is to have a power source supply end, a boost terminal and an output respectively; And at least one voltage-multiplying circuit, have an input, one first output and one second output respectively, this voltage-multiplying circuit is to be connected in series by this second output, this input of this first voltage-multiplying circuit is to be electrically connected a clock pulse signal, this first output is exported one first clock signal, this second output is exported one second clock signal, this first clock signal is the multiplication of voltage signal for this second clock signal, and this of this voltage-multiplying circuit first output is this boost terminal that is electrically connected this booster circuit respectively.

Electric charge pumping circuit of the present invention comprises at least one booster circuit and at least one voltage-multiplying circuit, this voltage-multiplying circuit is that a clock pulse voltage of signals size conversion is output as the double voltage size, increasing the node voltage between this booster circuit junction nodes, and make this electric charge pumping circuit that a stable output voltage can be provided.

According to above-mentioned conception, wherein this first clock signal is anti-phase with this clock signal.

According to above-mentioned conception, wherein this second clock signal is anti-phase with this clock signal.

According to above-mentioned conception, wherein this booster circuit comprises: one switches circuit, has one first signal end, a secondary signal end and a control end, and this secondary signal end is this first signal end that is electrically connected this commutation circuit of next stage; And an electrical power storage circuit, having one first end is to be electrically connected this secondary signal end, and one second end is this boost terminal for this booster circuit.

According to above-mentioned conception, wherein this commutation circuit comprises a N type passage CMOS transistor.

According to above-mentioned conception, wherein this electrical power storage circuit comprises an electric capacity.

According to above-mentioned conception, wherein this at least one booster circuit comprises that a base stage of passage CMOS (Complementary Metal Oxide Semiconductor) (MOS) transistor and this passage CMOS transistor is to be electrically connected a collector electrode to form a diode coupling transistor (diode-coupled transistor).

According to above-mentioned conception, wherein this voltage-multiplying circuit is to be one or two times of voltage-multiplying circuits.

According to above-mentioned conception, wherein this voltage-multiplying circuit comprises: an inverting amplifier have an input and be this input for this voltage-multiplying circuit, and an output is this second output for this voltage-multiplying circuit; One the one p type passage CMOS (Complementary Metal Oxide Semiconductor) (PMOS) transistor has a base terminal, one first conducting end and one second conducting end, and this first conducting end is to be electrically connected a power supply; One the 2nd P type passage CMOS transistor, have a base terminal, one first conducting end and one second conducting end, this first conducting end is this first conducting end that is electrically connected a P type passage CMOS transistor, this base terminal is this input that is electrically connected this voltage-multiplying circuit, and this second conducting end is this first output for this voltage-multiplying circuit; One electric capacity is electrically connected this second conducting end of a P type passage CMOS transistor and this output of this inverting amplifier; One N type passage CMOS transistor, have a base stage, one first conducting end and one second conducting end, this base stage is this input that is electrically connected this voltage-multiplying circuit, and this first conducting end is to be electrically connected this base terminal of a P type passage CMOS transistor and this second conducting end of the 2nd P type passage CMOS transistor.

The method of the present invention's control one electric charge pumping circuit on the other hand, make an output node of this electric charge pumping circuit that one booster voltage is provided, and this electric charge pumping circuit has an input node and is electrically connected a voltage, this electric charge pumping circuit comprises: at least one booster circuit, this booster circuit is to be connected in series between this input node and this output node, and this booster circuit has a power source supply end, a boost terminal and an output respectively; This method comprises the following steps: to provide a clock pulse signal; This clock signal conversion is produced one first clock signal, and this is connected to this boost terminal of corresponding this booster circuit with this first clock signal; This clock signal conversion is produced one second clock signal; And this boost terminal that this second clock signal conversion generation, one the 3rd clock signal is connected to corresponding this booster circuit.

According to above-mentioned conception, wherein this first clock signal is anti-phase with this clock signal multiplication of voltage.

According to above-mentioned conception, wherein this second clock signal is anti-phase with this clock signal.

According to above-mentioned conception, wherein the 3rd clock signal is anti-phase with this second clock signal multiplication of voltage.

For clearer understanding purpose of the present invention, characteristics and advantage, preferred embodiment of the present invention is elaborated below in conjunction with accompanying drawing.

(4) description of drawings

Fig. 1 is the circuit diagram of the gloomy electric charge pumping of known level Four Dick circuit (four-stage Dickson charge pumpcircuit).

Fig. 2 is the circuit block diagram with clock pulse multiplication of voltage electric charge pumping circuit of preferred embodiment of the present invention.

Fig. 3 is the circuit diagram of the clock pulse voltage-multiplying circuit of preferred embodiment of the present invention.

(5) embodiment

See also Fig. 2, it is the circuit block diagram with clock pulse multiplication of voltage electric charge pumping circuit of preferred embodiment of the present invention.As shown in Figure 2, a level Four electric charge pumping circuit 200 comprises four booster circuits 201,202,203,204, this booster circuit 201,202,203,204 have a power source supply end, a boost terminal 210,211 respectively, 212,213 and one output, and this booster circuit 201,202,203,204th, be connected in series with an input node 205 and an output node 209, the mutual point of contact of this booster circuit forms four voltage nodes 206,207,208 respectively.In addition, this booster circuit 201,202,203,204 comprise that a base stage of passage CMOS (Complementary Metal Oxide Semiconductor) (MOS) transistor and this passage CMOS transistor is to be electrically connected a collector electrode to form a diode-coupled transistor (diode-coupled transistor) 218,219,220,221.

In this electric charge pumping circuit 200, this level Four electric charge pumping circuit 200 comprises four voltage-multiplying circuits 223,224,225,226, be to have an input respectively, one first output and one second output, this voltage-multiplying circuit 223,224,225, the 226th, be connected in series by this second output, this input of this voltage-multiplying circuit 223 is to be electrically connected a clock pulse signal CLK, this first output is exported one first clock signal, and this second output is exported one second clock signal, and this first clock signal is the multiplication of voltage signal for this second clock signal, this first output of this voltage-multiplying circuit 223 is this boost terminal 210 that is electrically connected this booster circuit 201, this first output of this voltage-multiplying circuit 224 is this boost terminal 211 that is electrically connected this booster circuit 202, and this first output of this voltage-multiplying circuit 225 is this boost terminal 212 that is electrically connected this booster circuit 203, and this first output of this voltage-multiplying circuit 226 is this boost terminal 213 that is electrically connected this booster circuit 204.

In addition, this booster circuit 201 comprises an electric capacity 214, and an end of this electric capacity 214 is the inversion signals that receive a multiplication of voltage clock signal for this boost terminal 210, and the other end is to be electrically connected to this input node 205.This booster circuit 202 comprises an electric capacity 215, and an end of this electric capacity 115 is this multiplication of voltage clock signal CLK2 that receive this clock signal CLK for this boost terminal 211, and the other end is to be electrically connected to this input node 206.This booster circuit 203 comprises an electric capacity 216, and an end of this electric capacity 216 is the inversion signals that receive this multiplication of voltage clock signal for this boost terminal 212, and the other end is to be electrically connected to this input node 207.This booster circuit 204 comprises an electric capacity 217, and an end of this electric capacity 217 is to receive this multiplication of voltage clock signal CLK2 for this boost terminal 213, and the other end is to be electrically connected to this input node 208.And this diode-coupled transistor 218 is operating as a single-way switch, the store charge of this electric capacity 214 is sent to this electric capacity 215, in like manner, this diode-coupled transistor 219 is operating as a single-way switch, the store charge of this electric capacity 215 is sent to this electric capacity 216, this diode-coupled transistor 220 is operating as a single-way switch, the store charge of this electric capacity 216 is sent to this electric capacity 217, this diode-coupled transistor 221 is operating as a single-way switch, and the store charge of this electric capacity 217 is sent to an output capacitance Cout.

This electric charge pumping circuit 200 also comprises a diode-coupled transistor 222, and this diode-coupled transistor 222 is to be electrically connected on an input voltage V _DDAnd between this input node 205, this diode-coupled transistor 222 is to be operating as a single-way switch, with this input voltage V _DDElectric charge be sent to this electric capacity 214.

Therefore, according to conception of the present invention, utilize a voltage-multiplying circuit to increase the size of node voltage to overcome the size of a critical voltage that is increased because of transistorized pedestal effect (Body Effect), even when the voltage swing of input voltage is lower than 1.8V, also can smoothly this input voltage be sent to this output voltage.

Seeing also Fig. 3, is the circuit diagram of the clock pulse voltage-multiplying circuit of preferred embodiment of the present invention.As shown in Figure 3, one or two voltage-multiplying circuit 300 comprises: an inverting amplifier 301, one the one PMOS transistor 302, one the 2nd PMOS transistor 303, an electric capacity 304 and a nmos pass transistor 305.

Wherein, this inverting amplifier 301 have an input and be this input for this voltage-multiplying circuit, and an output is this second output for this voltage-multiplying circuit.The one PMOS transistor 302 has a base terminal, one first conducting end and one second conducting end, and this first conducting end is to be electrically connected this input voltage VDD.The 2nd PMOS transistor 303, have a base terminal, one first conducting end and one second conducting end, this first conducting end is this first conducting end that is electrically connected a PMOS transistor 302, this base terminal is this input that is electrically connected this voltage-multiplying circuit, and this second conducting end is this first output for this voltage-multiplying circuit.This electric capacity 304 is electrically connected this second conducting end of a PMOS transistor 302 and this output of this inverting amplifier 301.This nmos pass transistor 305, have a base stage, one first conducting end and one second conducting end, this base stage is this input that is electrically connected this voltage-multiplying circuit 300, and this first conducting end is to be electrically connected this base terminal of a PMOS transistor 302 and this second conducting end of the 2nd PMOS transistor 303.

If this input of this voltage-multiplying circuit is to receive this clock signal CLK, then this second output is exported an inversion signal of this clock signal, and the voltage swing when this clock signal is V again _DDThe time, this moment these nmos pass transistor 305 conductings and 303 not conductings of the 2nd PMOS transistor, and make a PMOS transistor 302 conductings, this input voltage V _DDTo these electric capacity 304 chargings; When the voltage transition of this clock signal was 0V, this moment was because this electric capacity 304 has a voltage V _DD, and can produce the inversion signal of this multiplication of voltage clock signal at this first output by this inversion signal that this inverting amplifier 301 is exported.

Comprehensively above-mentioned, the invention provides a kind of electric charge pumping circuit and method with clock pulse multiplication of voltage, utilize a voltage-multiplying circuit to increase the size of a clock pulse signal to improve enough node voltages to overcome the size of a critical voltage that is increased owing to a transistorized pedestal effect (Body Effect), therefore solved known electric charge pumping circuit engineering disappearance, and then reached research and development purpose of the present invention.

Claims (13)

1. A charge pumping circuit, characterized in that, comprising: At least one boosting circuit, the boosting circuit is connected in series, and the boosting circuit has a power supply terminal, a boosting terminal and an output terminal respectively; and At least one voltage doubler circuit has an input terminal, a first output terminal and a second output terminal respectively, the voltage doubler circuit is connected in series through the second output terminal, the input terminal of the first voltage doubler circuit It is electrically connected to a clock signal, the first output terminal outputs a first clock signal, and the second output terminal outputs a second clock signal, and the first clock signal is a double voltage of the second clock signal signal, the first output end of the voltage doubling circuit is respectively electrically connected to the boosting end of the boosting circuit. 2. The charge pumping circuit as claimed in claim 1, wherein the first clock signal is an inverse phase of the clock signal. 3. The charge pumping circuit as claimed in claim 1, wherein the second clock signal is an inverse phase of the clock signal. 4. The charge pumping circuit according to claim 1, wherein the boost circuit comprises: A switching circuit has a first signal terminal, a second signal terminal and a control terminal, the second signal terminal is electrically connected to the first signal terminal of the switching circuit at the next stage; and An electric energy storage circuit has a first terminal electrically connected to the second signal terminal, and a second terminal which is the boost terminal of the boost circuit. 5. The charge pumping circuit as claimed in claim 4, wherein the switching circuit comprises an N-channel CMOS transistor. 6. The charge pumping circuit as claimed in claim 4, wherein the energy storage circuit comprises a capacitor. 7. The charge pumping circuit as claimed in claim 1, wherein the at least one boost circuit comprises a channel CMOS transistor and a base of the channel CMOS transistor is a voltage A collector is connected to form a diode-coupled transistor. 8. The charge pumping circuit as claimed in claim 1, wherein the voltage doubling circuit is a double voltage doubling circuit. 9. The charge pumping circuit according to claim 1, wherein the voltage doubling circuit comprises: an inverting amplifier having an input terminal being the input terminal of the voltage doubler circuit, and an output terminal being the second output terminal of the voltage doubler circuit; A first p-channel CMOS transistor having a base terminal, a first conductive terminal and a second conductive terminal, the first conductive terminal is electrically connected to a power supply; A second P-channel CMOS transistor has a base terminal, a first conductive terminal and a second conductive terminal, and the first conductive terminal is electrically connected to the first P-channel CMOS transistor. The first conductive terminal of the semiconductor transistor, the base terminal is electrically connected to the input terminal of the voltage doubler circuit, and the second conductive terminal is the first output terminal of the voltage doubler circuit; a capacitor electrically connected to the second conductive terminal of the first P-channel CMOS transistor and the output terminal of the inverting amplifier; and An N-channel complementary metal-oxide-semiconductor transistor has a base, a first conductive terminal, and a second conductive terminal, the base is electrically connected to the input terminal of the voltage doubler circuit, and the first conductive terminal is The base terminal of the first P-channel CMOS transistor is electrically connected to the second conductive terminal of the second P-channel CMOS transistor. 10. A method for controlling a charge pumping circuit, so that an output node of the charge pumping circuit provides a boosted voltage, and the charge pumping circuit has an input node electrically connected to a voltage, the charge pumping circuit comprising: At least one boost circuit, the boost circuit is connected in series between the input node and the output node, and the boost circuit has a power supply terminal, a boost terminal and an output terminal respectively; it is characterized in that the The method includes the following steps: providing a clock signal; converting the clock signal to generate a first clock signal, and connecting the first clock signal to the corresponding boost terminal of the boost circuit; converting the clock signal to generate a second clock signal; and Converting the second clock signal to generate a third clock signal is connected to the corresponding boost terminal of the boost circuit. 11. The method as claimed in claim 10, wherein the first clock signal is voltage multiplied and inverted to the clock signal. 12. The method of claim 10, wherein the second clock signal is inversely phased to the clock signal. 13. The method of claim 10, wherein the third clock signal is doubled and out-phased with the second clock signal.

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