CN1498470B - Method and device for data alignment - Google Patents

Abstract

A method of distributing data manipulation of irregular data streams in multiple circuit stages (404, 406, 704, 706) of a data aligner (400, 700) whereby regular data having consecutively filled byte positions is generated flow. In a particular embodiment, the number of misaligned data episodes can be reduced through the use of data flow element maps. Only multiplexers (460, 470, 760, 770, 775) and simple logic circuits need to be added to the data aligner, and complex data streams can be mapped (835) to simple data streams. Hardware implementations associated with network protocols (where data streams are encoded and decoded for error detection and correction) allow for faster and more efficient pipeline design of checkers and generators, Then it is suitable for the design of higher frequency and higher bandwidth.

Description

Method and device for data alignment

〔Technical field〕

The present invention relates to the field of network systems. In particular, the present invention relates to data aligners used in network systems.

〔Background technique〕

Simply put, the Internet (Internet) is a collection of computer systems interconnected via a network (such as transmission lines, switches, routers), so as to transmit data between these computer systems. Generally speaking, data is transmitted along a data path in the network in the form of data packets. An important characteristic of the data path is the bit width (bit width). Bit width is the number of bits that are simultaneously processed or passed on this data path. The bit width of a data path determines its bandwidth and clock speed. Bandwidth is a measure of how fast data can flow on the data path. In digital systems, bandwidth can be expressed as data speed in bits per second (bps).

At one time, data was carried exclusively on the traditional Plain Old Telephone System (POTS), or the Public Switched Telephone Network (PSTN), using copper transmission lines with limited bandwidth capabilities. Subsequently, other types of networks were developed using transmission lines with higher bandwidth, for example: Integrated Services Digital Network (ISDN), which can transmit a larger amount of data (higher bandwidth) in a given time bits per second (bps). The Integrated Services Digital Network (ISDN) provides digital transmission over ordinary Public Switched Telephone Network (PSTN) copper wires over a narrow band local loop.

When the Internet (Internet) is experiencing explosive growth and data traffic is increasing exponentially, the most urgent need at present is the increase of bandwidth. Generally speaking, there are two ways to meet the requirement of increased bandwidth, namely: increasing the clock speed and widening the data path. System designers are advancing the technology by implementing data paths at higher clock speeds. In addition, system designers will also increase the bit width (bit width) to widen the data path (data path). Despite having widened data paths, these systems still need to support legacy systems, ie older systems that have previously been designed on narrower data paths. Therefore, the utilization of widened data paths can lead to irregularities in data flow.

Other parameters associated with the data path (data path) include: the type of network and the protocol for transmitting data on this data path (data path). Computer systems can use various networks, such as: Internet (Internet) and Synchronous Optical Network (SONET), to communicate with each other. Specifically, Synchronous Optical Network (SONET) is an American standard for synchronous data transmission over optical media. In addition, the corresponding international standard of Synchronous Optical Network (SONET) is Synchronous Digital Hierarchy (SDH). At the same time, the two standards must ensure that digital networks can be interconnected internationally and that existing legacy transmission systems can utilize optical media.

In addition, the computer system uses circuits related to network protocols, such as network adapters, to encode and decode data transmitted over the network for the purpose of error detection and correction. Selective bit removal and addition is common in various protocol implementations and interconnection network specifications. These two factors may lead to the generation of arbitrarily arranged data streams, from the heretofore obtained regular data streams, which must be collected and aligned in advance for efficient and convenient processing. The generation of regular data flow can effectively utilize the bandwidth, thereby obtaining faster data transmission time. In addition, the regular data flow is easier to process, more suitable for pipeline operation, and easier to capture and store. In networking circuits and systems, these factors are of utmost importance as they can affect key differentiating parameters for consumers and markets.

A class of circuits that map arbitrary data streams to regular data streams is known as a "data aligner". In particular, the data aligner takes misaligned data of various byte sizes and aligns this data to get the packed byte size. One problem with existing partial data aligners is that these aligners contain a large amount of logic in the first stage of a multi-circuit level design to handle as many misaligned data instances as possible. Another problem with existing partial data aligners is that these aligners feed back the output of the output selection multiplexer to the intermediate buffer, thereby creating logic circuit congestion in the first stage circuit design. This is because such methods, upon knowing that there is not enough data in a particular packet to pass as output, may keep connection data in this intermediate buffer instead of executing and restoring it. Such approaches are not only difficult to design, but also lead to more processing time in the first-stage circuit design of the data aligner, thereby limiting the frequency at which such data aligners can operate.

[Content of invention]

The invention relates to a byte rotation method and device. In a particular embodiment, the method may include receiving a plurality of bytes in a first buffer having a size of the plurality of bytes containing data. Additionally, the method includes determining, with the controller, the state of the plurality of bytes at least one clock cycle prior to rotating the plurality of bytes; and based on the state, predictively rotating the plurality of words in a rotator. The amount of rotation of the knot.

In another particular embodiment, the method may include predicting, in a subsequent clock cycle, the first number of bytes located in the first buffer. Additionally, the method may further include: based on the prediction, calculating a rotation amount for the second number of bytes received by the second buffer, and the calculation is performed in a current clock cycle.

In a particular embodiment, such an apparatus includes a first buffer coupled to receive a clock signal having a plurality of clock periods; a controller; and a rotator coupled to the controller and the first buffer. The rotator may include a first rotator circuit coupled to receive an input and generate a first output. Additionally, the rotator may also include a first multiplexer coupled to receive the input and the first output of the rotator circuit. The first multiplexer selects one of the input or the first output based on the first rotation amount control signal received by the controller. The first rotation amount control signal can be determined by predicting a number of bytes in the first buffer in subsequent clock cycles.

Other features and advantages of the invention will be apparent from the accompanying drawings and the following detailed description.

The invention relates to a data alignment method and device. Such a device may have multiple circuit stages coupled between multiple buffers. The downstream circuits and their corresponding buffers can be used to distribute the generation of the alignment data packets, so as to reduce the operation time of the preceding circuits.

In a particular embodiment, such an apparatus may include a first stage circuit coupled to a first buffer. The first stage circuit may include a rotator coupled to the first buffer; a controller coupled to the rotator; and a first multiplexer coupled to the controller. Additionally, such an apparatus can further include: a second buffer coupled to the rotator; and a second stage circuit coupled to the second buffer. The second stage of circuitry may include a second multiplexer. Additionally, a third buffer may also be coupled to the second stage circuit.

In one embodiment, such a method may include: receiving a first data component having a plurality of bytes; and determining to contain a first number of bytes of data. Additionally, the method may include passing through the first data component without manipulating the first data component (if all bytes contain data), and maintaining the data component (if not all bytes contain data).

In another embodiment, such a method may include: receiving a header component having a blank byte position beyond a number of bytes; and receiving a first subsequent body component. In addition, the method may further include: combining the header element and the first successor body element to fill the empty byte positions of the header element with the data of the first successor body element, thereby operating the header element to generate the first packet component. The first packet element may have the plurality of byte locations. In addition, the method may further include: transmitting the first packet element (if multiple byte positions of the first packet element are filled by the operation).

In yet another embodiment, the method may include receiving a discontinuous data stream of a first number of bytes, and passing the first number of bytes through the first and second buffers to a third buffer. The first number of bytes may be less than the predetermined number of bytes. The first buffer can be coupled to the second buffer, and the second buffer can be coupled to the third buffer. Additionally, the method can include receiving a second number of bytes and passing the first number of bytes from the second buffer to the third buffer. In addition, the method may further include: feeding back the third buffer to the second buffer (if the sum of the first number of bytes and the second number of bytes is less than the predetermined number).

Other features and advantages of the invention will be apparent from the accompanying drawings and the following detailed description.

[Description of drawings]

The present invention is described (not limited) by way of examples in conjunction with the accompanying drawings, wherein:

Figure 1 shows a digital processing system including an embodiment of a data aligner;

Figure 2 shows a network interface device including an embodiment of a data aligner;

Figure 3 represents an embodiment of the packet structure and its corresponding typical byte enabling;

Figure 4 shows an embodiment of a data aligner;

Figure 5 shows an embodiment of a data alignment method;

Figure 6 represents an embodiment of a method for mapping complex data streams to simple data streams;

Figure 7 shows another embodiment of the data aligner;

Fig. 8 shows another embodiment of the data alignment method;

Figure 9 shows an embodiment of a spinner;

Fig. 10 shows an embodiment of the relationship between rotation amount and multiplexer control vector value;

Fig. 11 shows an exemplary embodiment of the output of the rotator based on the input and the amount of rotation.

〔Detailed ways〕

In the following description of the invention, numerous specific details are set forth as examples of specific components, devices, methods, etc., in order to help provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the present invention may not necessarily be practiced with these specific details. In other instances, well known materials or methods have not been described in detail to avoid unnecessarily obscuring the present invention.

A method of distributing data operations of irregular data streams in multiple circuit stages of a data aligner, thereby generating regular data streams with consecutive fill bytes. The allocation of data operations can use the downstream circuit to perform part of the data operation, so as to release the previous circuit to perform the reception of other data bytes, so that the data aligner can operate at a higher frequency.

In a particular embodiment, the number of misaligned data episodes can be reduced through the use of dataflow component maps. In this data aligner, only a multiplexer and a combinational logic gate need to be added, and the complex data flow can be mapped (835) to a simple data flow.

It should be noted that although the method is based on sixteen-byte data elements, this method can also be applied to other byte sizes of data elements, such as: thirty-two bytes, eight bytes, and quadwords Festival. In another embodiment, this method can also be implemented with a variable data width, wherein the data width is a configurable parameter. It should be noted that, in the present invention, a "wire" connecting the respective components may be a single-bit wire, a multi-bit wire, or a bus.

FIG. 1 shows one embodiment of a digital processing system 100 , such as a workstation, personal computer, or server, etc., that implements data aligner 150 . The digital processing system 100 includes a bus or other communication device 105 for carrying information; and a processing device such as a processor 110 coupled to the bus 105 to process information and control the movement of data packets to and from a network interface device 140 . Processor 110 may represent one or more processors, such as: general-purpose processors (e.g., Motorola's PowerPC processor or Intel's Pentium (Pentium) processor), special-purpose processors (e.g., digital signal processing device (DSP)), and controller.

Digital processing system 100 further includes system memory 120 , which may include random access memory (RAM) or other dynamic storage devices, coupled to bus 105 to store information (eg, packets) and instructions to be executed by processor 110 . In addition, the system memory 120 can also be used to store temporary variables or other intermediate information when the processor 110 executes instructions. System memory 120 may also include read-only memory (ROM) and/or other static storage devices coupled to bus 105 to store static information and instructions to be executed by processor 110 .

One or more network interface devices (eg, network interface device 140 through network interface device N) may be coupled to bus 105 . In another embodiment, network interface device 140 may be located external to digital processing system 100 . The network interface device 140 may include circuits related to network protocols for encoding and decoding data transmitted over the network 160 for error detection and correction purposes. In one embodiment, the network interface device 140 includes circuitry to generate regular data streams. The network interface device 140 includes a data aligner 150 . Data aligner 150 operates to map arbitrary data streams to regular data streams, as described below.

According to specific design environment implementation, this network interface device 140 can be a synchronous optical network (SONET) card, an Ethernet (Ethernet) card, a symbol ring (tokenring) card, or other types of interfaces, so as to provide the interface with the network 160. communication link. Synchronous Optical Networks (SONET) and Ethernet Networks (Ethernet) are known in the art and therefore will not be described in detail.

It should be appreciated that this digital processing system 100 is merely representative of one example of a system that can have many different architectures and structures and that can be used with the present invention. For example, some systems usually have multiple buses, such as peripheral buses, dedicated cache buses, and so on. As another example, digital processing system 100 may also include a controller (not shown) coupled to bus 105 to assist processor 110 in effecting the movement of data packets to and from network interface device 140 . In another embodiment, the digital processing system may be an intermediate node (eg, a switch or router) in a network that provides a network-to-network interface. Such intermediate nodes can provide interfaces between similar networks or different networks. For example, the network medium 160 can be fiber optic medium, and the network medium N can be transmission line medium.

Figure 2 shows one embodiment of a network interface device that includes a data aligner. The network interface device 210 may be the network interface device 140 shown in FIG. 1 . Data, in the form of packets, travels through network interface device 210 and along a data path from system 205 to network 295 . The data path is the structural part of the network interface device 210 that processes and transfers data from one side (eg line 211 ) to the other side (eg line 236 ) under the influence of controls. The network interface device 210 will format the data into a packet protocol structure, so as to facilitate transmission on the network 295 . This packet protocol is used to specify the arrangement of information within a packet. In one embodiment, for example, the system 205 can be a client or a server, and the network 295 can be a Synchronous Optical Network (SONET) or Ethernet, as previously described.

In addition, the packets are transmitted according to an egress direction, which is from the system 205 , through the network interface device 210 , to the network 295 . Additionally, packets are received according to an ingress direction, from the network 295 , through the network interface device 210 , to the system 205 . In one embodiment, the network interface device 210 may have first-in-first-out (FIFO) memories 220 and 240, data aligners 230 and 250, packet check generator 235, packet error checker 245, encapsulator 225, and decapsulator device 255.

On line 211 , first in first out (FIFO) memory 220 receives packets from system 205 . However, transmission packets larger than the processing capability of the network interface device 210 may cause transmission drops. Accordingly, FIFO memory 220 operates to buffer data streams received from the side of system 205 to handle packet overload of the data streams. Likewise, first-in-first-out (FIFO) memory 240 operates to buffer data streams received via network 295 . In another embodiment, buffering can also be achieved using other devices, for example, using memory (eg, random access memory (RAM), first-in-first-out (FIFO) memory), which is coupled to the network interface device 210 or located at Memory within the system 205 (for example: the system memory 120 shown in FIG. 1 ).

On line 224 , the packet is transmitted via first-in-first-out (FIFO) memory 220 to encapsulator 225 . The encapsulator 225 framing the envelope according to the framing specification. This framing specification is the specification of "protocol bits", which surround the "data bits", so that the data can be "framed" into several paragraphs. In addition, this framing specification also enables receivers to synchronize processing at various points along the data stream.

This data stream packet is output by encapsulator 225 to data aligner 230 on line 229 . The data aligner 230 operates to timely collect received packets arriving at any time. The data aligner 230 receives unaligned data of various byte sizes and aligns the data to obtain a packet of bytes. Additionally, the data aligner 230 outputs alignment data to the packet inspection generator 235 on line 234 . Within a packet, the byte component output to the packet error checker may not have the correct data due to the packet operation. Therefore, on the line 233, the data aligner 230 also needs to transmit a control signal to the packet check generator 235 to indicate that the bytes in the packet are correct. In addition, the data aligner 230 also needs to transmit other control signals to the packet inspection generator 235, such as start-of-packet (SOP) and end-of-packet (EOP) control signals. The operation of the data aligner 230 will be described in detail as follows.

In one embodiment, the packet inspection generator 235 is used to confirm the correctness of the data flow. In addition to the data stream that may be used by the receiving system's PEC (eg, PEC 245 ), the PEC generator 235 also produces an output to determine whether the packets are good or whether the data stream has errors. On line 236 , this data stream is sent to network 295 . For example, some packets (such as Ethernet packets) have a 32-bit cyclic redundancy check (CRC). In one embodiment, an error detection code (such as a 32-bit cyclic redundancy check (CRC) code) may be appended at the end of the packet to provide automatic error detection. It should be noted, however, that the thirty-two bits of cyclic redundancy check (CRC) data can be placed anywhere in the packet. An error detection code (such as a cyclic redundancy check (CRC) code) is a number derived from a data block to detect corruption. In another embodiment, error detection codes and methods other than cyclic redundancy checking (CRC) may be used.

With packet error checking, a receiver system (not shown) coupled to network 295 can recalculate a checksum from a data packet and compare the checksum with the checksum of the original transmission to detect transmission errors. It should be noted that the packet error generator 235 does not need to be placed at the end of the transmission stage circuit, but can also be placed at any position in the data flow path.

The packets from network 295 are input to decapsulator 255 on line 256 . The decapsulator 255 is used to remove the framing data encapsulated in the data stream. When data stream framing data is removed, the data stream becomes irregular (ie, discontinuous). The data stream is input to data aligner 250 on line 251 . Data aligner 250 operates to collect discontiguous bytes of a received data stream and pack (or align) these packed bytes into a continuous data stream.

The input to data aligner 250 is provided to packet error checker 245 on line 246 . Packet error checker 245 can be used to confirm the correctness of this data stream. The packet error checker 245 uses the received data stream to generate a code and compares the generated code with the received code embedded in the data stream to determine whether the packet is good or whether the data stream has errors. Additionally, the output of packet error checker 245 is sent to first-in-first-out (FIFO) memory 240 on line 241 . First in first out (FIFO) memory 240 operates to buffer the data stream output to the system 205 on line 242 .

First-in-first-out (FIFO) memory, packet error checkers, encapsulators, and decapsulators are all known techniques, and therefore details of the operation of these devices are not provided. It should be noted that in Fig. 2, although each part of the network interface device 210 is shown in a separate manner, this representation is only used to introduce data flow operations in the ingress and egress directions. . In another embodiment, various components of the network interface device 210 may be combined into one or more integrated circuits (ICs).

FIG. 3 shows an embodiment of a packet structure and its corresponding example byte enables. Package 310 may have one or more components 320 , 330 , 340 , and 350 . Each packet element may have one or more bytes, for example, sixteen bytes. Although the following description utilizes a packet element size of sixteen bytes as an example, other packet element byte sizes may be used, for example, thirty-two bytes, eight bytes, and four bytes.

Packet 310 includes a single header element 320, a single trailer element 350, and a body 335, which may include one or more body elements (eg, elements 330 and 340). The header element 320 represents the start of the packet, and its byte position can be partially or completely filled with data bits. The header 320 may be determined by assertion of a start-of-packet (SOP) control signal 325 , which partially or fully fills the bytes of the header element 320 with data bits.

End element 350 represents the end of the packet and its byte position may be partially or fully filled with data bits. The end element 350 can be determined by the acknowledgment of an end-of-packet (EOP) control signal 355 , which partially or fully fills the bytes of the end element 350 with data bits. All byte positions of the body element are filled with data bits (eg: body element 340). A partial body refers to a body element (eg, body element 330 ) that is partially filled with data bits, which is neither the header element 320 nor the trailer element 350 . A hole is a blank component within the packet 310 or between the packet 310 and other packets (not shown).

FIG. 3 also shows example byte enables 321, 331, 341, and 351, which may correspond to these packet elements. A byte enable of "1" indicates that the corresponding byte position has data. Byte enable "0" means: the corresponding byte position has no data. These bytes enable transfer to the control portion of the buffer, which will be described below in conjunction with FIGS. 4 and 7 .

Figure 4 shows an embodiment of a data aligner. In one embodiment, the data aligner 400 has two-level circuit (first-level circuit 404 and second-level circuit 406 ) streamlines, which are separated by an intermediate buffer 420 . The intermediate buffer 420 operates to store all failed data between the first stage circuit 404 and the second stage circuit 406 . Data aligner 400 also includes buffers 410 and 430 coupled to the input of first stage circuit 404 and the output of second stage circuit 406, respectively. In one embodiment, the buffers 410, 420, and 430 may be registers. Buffers 410, 420, and 430 operate to store data received by previous circuit stages. Additionally, data aligner 400 may have control buffers 415, 425, and 435 that operate to store byte enables for these packed elements, as described below. Buffers and registers are known technologies, therefore, their detailed description will not be provided.

In one embodiment, buffers 410, 420, and 430 have a size of sixteen bytes, for example. In alternative embodiments, buffers 410, 420, and 430 may have other sizes of byte numbers, for example, thirty-two bytes, eight bytes, and four words, depending on the particular byte method used by the system. Festival.

Buffers 410 , 420 , and 430 each have a clock input coupled to receive a clock signal via line 481 . The clock signal can be recovered from the data signal, or can be generated by a clock generator (not shown). The clock signal includes a plurality of clock periods to implement the operation sequence of the data aligner 400 .

Buffer 410 has an input coupled to receive data packets on line 411 . Buffer 410 outputs these data packets to rotator 440 and controller 450 on lines 412 and 413, respectively. The output of rotator 440 is coupled to intermediate buffer 420 and multiplexer 460 via line 441 . The output of intermediate buffer 420 is coupled to the data output of multiplexer 470 on line 421 . The output of multiplexer 470 is coupled to buffer 430 via line 471 .

The controller 450 can be used to control the operation of the multiplexers 460 and 470, thereby passing byte data, controlling the operation of the rotator 440, generating external control signals, such as: start-of-packet (SOP) and end-of-packet (EOP), and generating Byte enable control signal (as shown in Figure 3). Controller 450 also has control outputs coupled on lines 452 and 459 to the control inputs of rotator 440 and multiplexer 460 , respectively, and to the control input of multiplexer 470 on line 453 .

Rotator 440 operates to rotate one or more bytes to different byte slots (or positions) of the component under the control of this controller 450 . In one embodiment, the controller 450 may apply a rotation amount control signal to the rotator 440 on the line 452 . In addition, the output of the rotator 440 is used as the input data of the buffer 420 and the input of the multiplexer 460 via the multiplexer 480 . The function of this rotation amount control signal determines the amount of rotation of the buffer 410 contents, thereby connecting the rest of the buffer 410 (if present) and the rest of the buffer 420 (if present), and allowing the contents of the buffer 420 to be properly rotated. Byte aligned. To determine this amount of rotation, the controller 450 must identify the various byte states one clock cycle before the actual rotation occurs.

In the first byte state, the contents of buffer 410 are written to buffer 420 using a pass-through method. No byte lanes are interleaved, whereby byte 0 of buffer 410 advances to byte 0 of buffer 420; byte 1 of buffer 410 advances to byte 1 of buffer 420; and so on. This byte state may occur when the controller 450 determines that the buffer 420 is empty, or the buffer 420 has an end-of-packet (EOP) signal, where packet level granularity must be maintained. This byte state may also occur when buffer 410 has a start-of-packet (SOP) signal, regardless of what state buffer 420 has. In this way, the buffer 410 and the buffer 420 will not have correlation. In any case, no data bytes need to be aligned, and byte data is written using pass-through. The amount of rotation for the next cycle can be predicted as sixteen minus the number of bytes in buffer 410 .

In the second byte state, all sixteen bytes of buffer 410 are written into buffer 420, which means that buffer 420 will be completely filled in the next cycle. In this case, this rotation amount can be predicted to be zero, which also means that byte-way crossings will not occur.

In the third byte state, bytes from buffer 410 will not be written to buffer 420 . Such states indicate that buffer 410 contains an end-of-packet (EOP) signal, and the states of buffers 410 and 420 indicate that this data can be transferred directly between buffers 410 and 420 to buffer 430, thereby precluding subsequent translation of data into the buffers. device 410 needs. In this case, this amount of rotation can be predicted to be zero.

In the fourth byte state, the net correct byte counts of buffer 410 and buffer 420 exceed sixteen and the remainder of buffer 410 is written to buffer 420 with appropriate byte lane interleaving. In this case, subsequent inputs to buffer 410 must be predicted. In this case, the rotation amount can be predicted to be thirty-two minus the net number of bytes of buffer 410 and the number of bytes of buffer 420 .

For example, buffer 420 may have fourteen correct bytes (with data), and buffer 410 may have six correct bytes. In the next clock cycle, sixteen bytes are transferred to the buffer 430 and the remaining four bytes are stored in the buffer 420 . In this way, the rotation amount of the next set of inputs can be predicted as 32-20=12. For vectors {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0}, a rotation of "12" will result in a vector {11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12}, thus ensuring that the next input will start with the fourth byte from the left. In addition, the function of calculation can be completed in the previous clock cycle by advancing one clock cycle.

The multiplexers 460, 470, 480 select a data input between two data inputs based on control signals applied to their control inputs. Multiplexers are known technology, therefore, a detailed description thereof will not be provided. The output of multiplexer 460 is coupled on line 461 to the data input of multiplexer 470 . The output of multiplexer 470 is coupled to buffer 430 on line 471 . The output of multiplexer 480 is coupled to buffer 420 . Multiplexers 460, 470, and 480 receive control signals from the control input of controller 450 on lines 452, 453, and 455, respectively. It should be noted that these multiplexers are separated from other components for ease of discussion. These multiplexers can be located in other component blocks, for example, the multiplexer 480 can be located in the buffer 420 .

The function of these control signals applied to multiplexers 460 and 470 via the content of buffer 420 and the rotated content of buffer 410 selects the output of this multiplexer. In one embodiment, the applied control signal may be a sixteen-bit control signal that is a function of the rotation amount, which is associated with a sixteen-byte spanning operation, as shown in FIG. 10 . A position with a "1" means: select the rotation amount of the rotator 440 , and a position with a "0" means: select the output of the buffer 420 . The value of the rotation amount represents the number "1" of the multiplexer control signal vector starting from position 0.

Controller 450 also has a control output coupled to buffer 420 via line 459 . In one embodiment, the control signal output of the buffer 420 via line 459 may be sixteen bits wide and may be byte-by-byte after selecting the contents of this buffer based on the previously discussed rotation amount. Write buffer 420 . In addition, the control signal output of the buffer 420 can also be used to determine the correct byte of the buffer 420 in the next clock cycle. In order to achieve the decision to write enable the buffer 420, the controller 450 can also identify various states in a current clock cycle.

In a first case, the content of buffer 410 may be written to buffer 420 using a pass-through. This situation can occur when the buffer 420 is empty, or when the buffer 420 has an end-of-packet (SOP) signal, where this packet granularity needs to be maintained. In addition, this situation may also occur when the buffer 410 has a start-of-packet (SOP) signal, no matter what state the buffer 420 has. In such cases, the byte enable for the corresponding buffer 410 becomes a write enable for the buffer 420 .

In the second case, all sixteen bytes of buffer 410 are written into buffer 420, which means that buffer 420 will be completely filled in the next clock cycle. In such cases, the write enables of buffer 420 will all be "1".

In the third case, none of the bits of buffer 410 are written into buffer 420 . Buffer 410 will have an end-of-packet (EOP) signal and the status of buffers 410 and 420 so that data can be passed directly to buffer 430, thereby eliminating the need for translation on subsequent inputs. In such cases, the write enable of buffer 420 will be all "0".

In the fourth case, the net correct byte count of buffer 410 and buffer 420 would exceed sixteen and the remainder of buffer 410 would be written to buffer 420 using appropriate byte path interleaving. In this case, the write enable of buffer 420 can be calculated as the correct byte number of buffer 410 plus the correct byte number of buffer 420 minus sixteen.

The previously described data aligner 400 can also receive unaligned data of various byte sizes on the line 411 and align this data to achieve a specific byte size, which will be described below with reference to FIG. 5 . Data aligner 400 can support data packets, which can have a header component, a body component, and a trailer component.

Figure 5 shows an embodiment of a data alignment method. This method is described in terms of a data method with a data component having sixteen bytes. However, a similar approach can be applied to other byte packing methods, as previously described. In an embodiment, data aligner 400 may start without any data. When the header element of the data packet arrives, the controller 450 determines whether the header element has less than 16 bytes of data, as shown in step 510 . If the header element has less than sixteen bytes of data, those bytes are transferred to and retained in the buffer 420 for future packing steps, as shown in step 520 . If the header element has complete 16-byte data, then this data is sent to the buffer 430 for output using the control signal, as shown in step 530 .

This header component can follow either a body component or an end component. If this header element follows the body element, since the number of data bytes in the intermediate buffer 420 and the number of bytes in the subsequent body element will be greater than or equal to sixteen bytes, all sixteen bytes will be processed in time after being processed in time. The control signal generated by the controller 450 is sent to the buffer 430 to represent the start of packet (SOP), as shown in step 540 .

Based on the number of bytes with data individually, the decision is made to select either the bytes of the intermediate buffer 420 or the new input bytes of the buffer 410 . New incoming bytes to buffer 410 are rotated by the number of bytes previously transferred directly by buffer 4410 to compensate for the net sixteen bytes, as shown in step 550 . These rotated bytes are written to intermediate buffer 420 . Steps 540 to 550 are repeated until the controller 450 finds that the end component has arrived, as shown in step 560 .

When the end component has arrived, the data of buffer 430 is output on line 431 , regardless of the size of the net packet, so as to maintain the packet boundary of each component, as shown in step 570 . In this way, the data aligner 400 can convert the header element, the body element, and the trailer element (wherein the header element and/or the trailer element can be partially filled with data) into continuous packets, which have a or more body components and an end component.

For example, a header element may be received in buffer 410 and determined by controller 450 to contain seven bytes of data. Therefore, the header element has less than 16 bytes of data, therefore, the 7 bytes of data are transmitted and stored in the intermediate buffer 420 . The next receiving component is the main component. This body component is determined by the controller 450 to have sixteen bytes of data, and the controller 450 performs calculations to determine that a total of twenty-three bytes of data have been received. Because all data have exceeded the size of sixteen bytes of the data aligner 400, therefore, the controller 450 will select the lowest nine bytes of the main body component with sixteen bytes of data to match the seven bytes of the header component The data is output together as the sixteen-byte body component of a packet. To this end, the controller 450 sends the selected nine bytes to the rotator 440 as an input to the multiplexer 460 . These nine rotation bytes, together with the seven bytes of buffer 420 , are then used as inputs to multiplexer 470 . The controller 450 transmits a multiplexer control signal to the multiplexer 470 on the line 453 , so as to obtain and output sixteen connection bytes of the multiplexer 460 .

As such, data aligner 400 has sixteen bytes in buffer 430 for output and the remaining seven bytes in buffer 410 . Since the lowest nine bytes of the sixteen-byte body element have already been output, the remaining seven bytes of buffer 410 can be output by rotator 440 to the lower byte position and written into buffer 420 . These rotated bytes are then input and stored in the intermediate buffer 420 . When the next body element is received, the above steps can be repeated to generate another sixteen-byte element of the packet to output to the buffer 430 .

When the end component is received (such as: after the controller 450 receives an end-of-packet (EOP) signal), the bytes with data in the end component will be combined with the bytes of the intermediate buffer 420 and input to the buffer 430, Instead of waiting for the packet byte size of sixteen bytes. For example, if the middle buffer 420 has seven bytes and the receiving end element has one byte of bit data, the controller 450 will send this one byte to the rotator 440 . Then, the seven bytes stored in the intermediate buffer 420 and the rotated output of the one byte are sent from the controller 450 to the multiplexer 470 for output in the next clock cycle.

As previously mentioned, the method of FIG. 5 can handle fairly regular data streams, which will have header, body, and trailer elements within the packets. In another embodiment, other types of data streams may be encountered in network protocols (hereinafter referred to as complex data streams to distinguish them from the simple data streams described in Figures 4 and 5), wherein such rules Performance may be affected by any enable or disable byte, for example, in the dry sequence of the standard Packet Over SONET (POS) protocol. In one embodiment, complex data streams may have holes or partial body components, as previously described in FIG. 3 . Such complex data flows can be handled by mapping these components to simple data flows (as described in Figures 4 and 5).

FIG. 6 shows an embodiment of a mapping method for handling holes or partial body components in a data stream. In one embodiment, the header component of the complex dataflow can be mapped 610 to the header component of the simple dataflow; the body component of the complex dataflow can be mapped 620 to the body component of the simple dataflow; and the end component of the complex dataflow can be Map 630 to the end component of the simple dataflow. Holes can be handled by leaving state 640 and not performing data aligner actions, which will be described below in conjunction with data aligner 700 of FIG. 7 .

Part of the body function can be mapped 650 and 660 to the end element of the simple data flow, which classifies the end element into two different end elements: end element A and end element B. End element A indicates that the partial body of FIG. 7 and the intermediate buffer 720 of the data aligner 700 have an end element with a net number of data bits less than sixteen bytes. The end element B indicates that the partial body of FIG. 7 and the intermediate buffer 720 of the data aligner 700 have an end element with a net byte number of data bits greater than or equal to sixteen bytes.

Figure 7 shows another embodiment of a data aligner that can be implemented for complex data streams. In one embodiment, data aligner 700 may have two streamlined stages (first stage 704 and second stage 706 ), which are separated by buffers 720 and 730 . Data aligner 700 has buffer 730 , rotator 740 , controller 750 , and multiplexers 760 , 770 , 780 , and 790 . The rotator 740 and controller 750 operate in a manner similar to the rotator 440 and controller 450 of FIG. 4 unless otherwise indicated.

Buffers 710 , 720 , and 730 each have a clock input coupled to receive a clock signal via line 781 . The clock signal can be recovered via the data signal, or can be generated by a clock generator (not shown). In addition, the clock signal may include multiple clock periods, so as to implement the operation sequence of the data aligner 700 .

The buffer 720 operates to store all failed data between the first circuit stage 704 and the second circuit stage 706 . The data aligner 700 includes a buffer 710 and a buffer 730 coupled to the inputs of the first stage circuit 704 and the second stage circuit 706 respectively. In one embodiment, the buffers 710, 720, and 730 may be registers. Control buffers 715, 725, and 735 are coupled to controller 750 and operate to store byte enables.

Buffer 710 has an input coupled to receive data packets on line 711 and output these data packets to rotator 740 and controller 750 on lines 712 and 713, respectively. The output of rotator 740 is coupled to a data input of multiplexer 780 , while another data input of multiplexer 780 is coupled to receive the output of multiplexer 775 on line 776 . Additionally, the output of rotator 740 is also coupled to receive the output of multiplexer 775 via line 776 . The output of multiplexer 780 is coupled to the input of buffer 720 .

Rotator 740 operates to rotate one or more bytes to different byte slots (or positions) under the control of controller 750 . In one embodiment, the controller 750 may apply a rotation amount control signal to the rotator 740 via a line 758 . The function of this rotation amount control signal determines the amount of rotation of the contents of buffer 710 so that the remainder of buffer 710 (if present) and the remainder of buffer 720 (if present) can be connected and the contents of buffer 720 May be properly byte-aligned.

To determine this amount of rotation, the controller 750 can identify various byte states one clock cycle before the actual rotation occurs, as described for the rotator 440 of FIG. 4 . The means of advancing one clock cycle can be maintained while supporting a part of the structure of the main components. In complex data streams, the number of buffer 720 bytes for the next clock cycle is predicted and replaced with the net correct number calculated so far. In the present calculation, this net correct number is the number of bytes in buffer 710 plus the number of bytes in buffer 720 . This current net correct byte count becomes the number of bytes in buffer 720 when supporting partial body components and predicting subsequent input rotations. This amount of rotation is used as a control and seed for other control signals.

Controller 750 has control outputs coupled to control inputs of rotator 740 and multiplexers 760, 770, 775, and 780 via lines 752, 753, 754, and 755, respectively. Control 750 also has a control output coupled to rotator 740 via line 759 , and a control input coupled to buffer 720 via line 759 .

The output of multiplexer 760 is coupled to the data input of multiplexer 770 via line 761 . The output of buffer 720 is coupled to another data input of multiplexer 770 and a data input of multiplexer 775 via lines. The output of multiplexer 770 is coupled to buffer 730 via line 771 . Buffer 730 includes data outputs and control inputs. The data output of buffer 730 is coupled to the data input of multiplexer 775 via line 779 . The control output of buffer 730 is output on line 778 .

Controller 750 has a control output coupled to buffer 720 via line 759 and to this buffer 730 via line 751 . In one embodiment, the control signals output to buffers 720 and 730 via lines 759 and 751 respectively may be sixteen bits wide. The control signal of the buffer 720 controls the write operation of the buffer byte by byte after selecting the content of the select buffer based on the rotational amount control signal. In addition, the control signal output to the buffer 720 can also determine the correct byte of the buffer 720 for the next clock cycle. In order to determine the write enable of the buffer 720, the controller 750 recognizes various states during the current clock cycle, as previously described in FIG. 4 . Hole receptions can be handled in a state-preserving manner.

As an example, the reception instructions for some of the main body components are as follows. Assume that upon activation of the data aligner 700, there is a sequence of six bytes followed by six bytes followed by eight bytes within the same packet. The case where buffer 710 has eight bytes, buffer 720 has six bytes, and buffer 710 does not have an end-of-packet (EOP) signal cannot be included in the previous description of FIG. 4 . In this case, we would want to transfer fourteen bytes to buffer 730 together. In the next clock cycle, the controller 750 will determine that this is a partial body condition and restore the combined output (control and data) of the buffer 730 to the intermediate buffer 720 and suppress the use of the controller 750 to generate an output enable to be sent to the buffer 730. This merge action skips one clock cycle and resumes in the next clock cycle if no new data is available. Otherwise, if new data is received, the skip action will continue until the test of the end component A is passed.

Feedback of this net correct number has been processed for subsequent calculations for the purposes of rotation calculations. This restore action shows that buffer 720 has fourteen bytes and buffer 710 has six bytes. This represents the case of ending component A as previously described in FIG. 6 . In this way, we can perform calculation actions as if we were receiving, calculating, and recovering a simple data stream. Relative to fourteen bytes, this amount of rotation is predicted to be equal to 32-14=18 bytes of rotation, which is equivalent to a rotation of two bytes (only four bits). Thus, for buffer 710 with six bytes, rotating two bytes places byte 0 and byte 1 at positions 14 and 15 respectively, which are merged with the fourteen bytes of buffer 720 . If this is a true end element, then the sixteen bytes are sent to buffer 730 . These write enables are 20-16, if the left four bytes are written into buffer 720 .

For the case where buffer 720 has fourteen bytes and buffer 710 has six bytes, this predicted rotation equals 32-20=12. In this case, the left four bytes of buffer 720 will maintain their positions, and a twelve-byte rotation will place byte 0 of the new incoming byte at position 4, for subsequent concatenation operations, and so on. This program is repeated endlessly.

The aforementioned data aligner 700 can receive unaligned data of different byte sizes on the line 711 and align the data to obtain a specific byte size, which will be described in detail with reference to FIG. 8 as follows. In addition, the data aligner 700 can also support data packets with holes and partial body elements, except for the general header element, body element, and trailer element.

The rotator 740 operates in a similar one-clock-cycle-advance manner as the rotator 440 described in FIG. 4 to support part of the main body assembly structure. The mapping method previously described in FIG. 6 is implemented by predicting and replacing the number of bytes in the buffer 720 for the next clock cycle as the net correct number for the current calculation. In the present calculation, this net correct count is the number of bytes in buffer 710 plus the number of bytes in buffer 720 . In the case of partial body component support and rotation prediction for subsequent inputs, the current net correct byte count would become the buffer 720 byte count. This amount of rotation is the main control, and can also be used as a seed for other control signals.

Fig. 8 shows another embodiment of a data alignment method for complex data streams. In one embodiment, the packet component receives and analyzes to determine the type of component, as shown in step 810 . If this component is determined to be a header component, a body component, or an end component, as shown in step 815, then this component can be mapped to the corresponding component type of the simple data stream, and processed according to the method described in FIG. 5, as Step 820 is shown.

If the component is not a header component, a body component, or an end component, the component will be analyzed to determine whether it is a hole or part of the body component, as shown in step 825 . If the component is determined to be a hole, then the status of the buffers 710 , 820 , and 730 of the data aligner 700 will remain unchanged and no action will be taken, as shown in step 830 . However, if the component is determined to be part of the main component, then part of the main functions of this component will be mapped to the end component, as shown in step 835 . When performing this mapping action, the part body component can be classified into two types of mapping components based on the number of bytes (net number) of data in the part body and the intermediate buffer 720, namely: end component A and end component B , as shown in step 840.

If this net number is less than sixteen bytes, then the previous ending sequence shown in FIG. 5 can be followed, as in step 845, with the following adjustments, which include: suppressing the control output of the data aligner 700, as in step 850 As shown (this basically means: the control signal indicating the correctness of the byte in position 1 to 16 will be generated in the second circuit stage 706, but will be passed through the logic circuit of this controller 750 when the end component A is detected Suppress); skip this intermediate buffer 720, as shown in step 855; In certain embodiments, the net number of current clock cycles can be predicted as the number of intermediate buffers 730 for the next clock cycle. Subsequently, steps 850, 855, and 860 are repeated until the net number exceeds or equals sixteen.

For example, if intermediate buffer 720 has seven bytes and buffer 710 receives one byte, then eight bytes are sent to buffer 730 . Therefore, the number of bytes stored in the buffer 730 is less than sixteen bytes, and the controller 750 will suppress the control output 778 . In one embodiment, the control output 778 remains inhibited until the net number equals or exceeds sixteen bytes, or an end-of-packet (EOP) signal is received. In another embodiment, another logic architecture and control signal may be used to suppress the control output 778 of the data aligner 700 .

Then, using the control signal transmitted by the controller 750, the output of the buffer 730 can be fed back through the multiplexers 775, 760, and 770, so as to be input to the buffer 730 in the next clock cycle. In this way, the output of intermediate buffer 720 can be pulsed with the contents of buffer 730 . Then, using the predictive method previously described in FIG. 7, this buffer 710 can perform net number calculations when additional bytes are received. These steps are repeated until the net byte count of the buffer 710 and the buffer 720 (including the skipped bytes from the buffer 730) equals or exceeds sixteen bytes.

If this net number is equal to or greater than sixteen bytes, the following adjustments will be added to the ending sequence (as shown in step 865) previously described in FIG. ) and byte enabling), as shown in step 870; the end-of-packet (EOP) control signal is not generated, as shown in step 875; and this intermediate buffer 720 is not skipped, as shown in step 880, because it has been properly to update.

Continuing with the previous example, if buffer 720 (including the skipped byte of buffer 730) stores eight bytes of data, and receives another eight bytes, those eight bytes are sent along with the output of rotator 760 Up to multitasker 760. Since the sum is equal to sixteen, the output of this connection is sent to the multiplexer 770 for output in the next clock cycle. The controller 750 does not generate any end-of-packet (EOP) control signals. In this way, partial body elements that result in greater than or equal to sixteen bytes in buffers 710 and 720 (including the skipped byte of buffer 730) can be treated similarly to the end element of a simple data stream, instead of An end-of-packet (EOP) control signal needs to be generated.

The method described above allows complex data streams to be mapped to relatively simple devices, and only needs to add multiplexers and combinational logic circuits. This structure can reduce the control design burden of the first stage circuit, which may have quite strict timing requirements and need to distribute logic circuits between two circuit stages, rather than just packaging the first stage circuit and logic circuits . This kind of circuit structure may get better timing effect and higher operating frequency.

Figure 9 shows an embodiment of a spinner. In one embodiment, the rotator 900 may be used in the rotator 440 of FIG. 4 or the rotator 740 of FIG. 7 . The rotator 900 represents four stages of byte rotation circuits in series, where each byte rotation circuit 981 to 984 is capable of rotating one, two, four, eight bytes on its own. Byte-rotating circuits are known techniques, and therefore, a detailed description thereof will not be provided.

Based on the rotation input function, each byte rotation circuit 981 to 984 can be skipped. In this architecture, the rotator 900 may generate a rotated output 979 via a sixteen byte input based on control signals 971 to 974 representing a byte rotation amount of zero to fifteen bytes. Figure 11 shows an embodiment showing the output of a spinner 900 based on the input and the amount of rotation.

Control signals 971 to 974 serve as control inputs to multiplexers 991 to 994 respectively. Control signals 971-974 select between outputs 961-964 of byte rotation circuits 981-984, and inputs 951-954 of byte rotation circuits 981-984, respectively. The inputs 951 to 954 are used as data inputs of the multiplexers 991 to 994 respectively. Fig. 10 shows an output 979 based on these input data 951 to 954 and these rotation amounts. In another embodiment, another type of rotator may be used, for example a barrel rotator.

The method and device described in the invention are used to solve the general and cyclic problems of complex data path design. In addition, hardware implementations associated with network protocols (where data streams can be encoded and decoded for error detection and correction) may also lead to faster and more efficient checker and generator pipeline designs, and thus to Design for higher frequency and wider bandwidth.

In another embodiment, the method and apparatus described in the present invention can be used in other types of systems and components that require data alignment, for example, processors that require alignment of misaligned data in various byte lanes Load and storage engines. As another example, the method and apparatus can be applied to data storage functions, where multiple byte-wide store operations of an internal command are mapped to a single store operation on an external bus.

In summary, the present invention has been described in detail with reference to specific embodiments. However, it is obvious that various changes and adjustments can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention listed in the claims. Therefore, the specification and drawings of the present invention are only used to describe the characteristics of the present invention, rather than to limit the scope of the present invention.

Claims (53)

1. data alignment device, it comprises:

Input, the input of importing group in order to the parallel format of receiving digital data unit is temporary serial;

The data alignment device is coupled to this input and responds the temporary series of this input is exported group with the parallel format that produces described unit of digital data the temporary series of output;

Output is coupled to this data alignment device to export the temporary series of this output;

This data alignment device comprises buffer, it is coupled to this input with when group is imported in this input reception second, store the data cell of the first input group, and combiner, it is coupled to this buffer and this input, this combiner comprises circulator and controller, wherein this circulator be coupled to this input with rotate this second the input group data cell with locate this second the input group the selected data unit, make this combiner can parallel connection described selected data unit and be stored in all described data cells of this buffer, use and produce a described output group that exports in the group, this controller determines this circulator to rotate the rotation amount of the described data cell of this second input group, this controller be coupled to this circulator with information that this rotation amount of expression is provided to this circulator, thereby this combiner is stored in the described selected data unit of all described data cells of this buffer and this second input group to produce a described output group in order to utilize parallel format combination; And

Data path is coupled to this combiner and this output and can transfers to this output to allow a described output group, and do not need to be stored in this buffer.

2. device as claimed in claim 1, wherein, these second all described data cells of importing the described selected data unit of group and being stored in this buffer of the parallel connection of this combiner use producing a described output group.

3. device as claimed in claim 1, wherein, this combiner comprises selector, and its input is coupled respectively to this input of mentioning at first and this buffer, and its output then is coupled to this data path.

4. device as claimed in claim 1, wherein, this controller is used this rotation amount of decision based on the data cell storage volume of this buffer.

5. device as claimed in claim 4, more comprise another buffer, it is coupled to this input and this combiner when being stored in this buffer of mentioning at first with the described data cell in this first input group, store this second input group, wherein, this controller is used this rotation amount of decision based on the summation of the storage volume of data cell separately of described buffer.

6. device as claimed in claim 1, wherein, the header assembly that each described input group is a data packet, body assembly, and one of ending assembly.

7. device as claimed in claim 1, wherein, each described data cell is a byte.

8. device as claimed in claim 1, wherein, this buffer has the maximum data unit storage volume, and it equals the maximum data unit capacity of input group in the temporary series of described input.

9. device as claimed in claim 8, wherein, this maximum data unit storage volume of this buffer is 16 data cells.

10. device as claimed in claim 1, wherein, this data path is skipped this buffer.

11. a data alignment method, its step comprises:

The temporary series of input of the parallel format input group of receiving digital data unit;

Respond the temporary series of this input, produce the temporary series of output of the parallel format output group of described unit of digital data, it comprises: when receiving the second input group, the data cell that stores the first input group is in buffer;

This generation step comprise the rotation this second the input group data cell with the location in order to all described data cells that are stored in this buffer parallel connected this second the input group the selected data unit, and parallel connection described selected data unit and all described data cells of being stored in this buffer are to produce an output group in the described output group, and based on the data cell storage volume of this buffer, and the rotation amount of the described data cell of this second input group of decision rotation, thereby utilize described selected data unit that the parallel format combination is stored in all described data cells of this buffer and this second input group to produce described output group; And

Export this output group further to handle, do not export group in buffer and do not need to store described one.

12. method as claimed in claim 11, wherein, this output step comprises a described output group, and it skips buffer.

13. a device, in order to connect digital data processor to the digital communication networking, it comprises:

First FPDP, it allows to utilize the digital data exchange of this data processor;

Second FPDP, it allows to utilize the digital data exchange of this telecommunication network; And

The data alignment device, be coupled in this first and this second FPDP between, it comprises an input, in order to the temporary series of input of the parallel format of receiving digital data unit input group; The data alignment device is coupled to this input and responds the temporary series of this input is exported group with the parallel format that produces described unit of digital data the temporary series of output; And output, be coupled to this data alignment device to export the temporary series of this output;

This data alignment device comprises buffer, it is coupled to this input with when group is imported in this input reception second, store the data cell of the first input group, and combiner, be coupled to this buffer and this input, this combiner comprises circulator and controller, wherein this circulator be coupled to this input with rotate this second the input group data cell with locate this second the input group the selected data unit, make this combiner can parallel connection described selected data unit and be stored in all described data cells of this buffer, use and produce a described output group that exports in the group, this controller determines this circulator to rotate the rotation amount of the described data cell of this second input group, this controller be coupled to this circulator with information that this rotation amount of expression is provided to this circulator, thereby this combiner is stored in the described selected data unit of all described data cells of this buffer and this second input group to produce a described output group in order to utilize parallel format combination; And

This data alignment device comprises data path, and it is coupled to this combiner and this output can transfer to this output to allow a described output group, and does not need to be stored in this buffer.

14. device as claimed in claim 13, wherein, this combiner comprises selector, and its input is coupled respectively to this circulator and this buffer, and its output then is coupled to this data path.

15. device as claimed in claim 13, wherein, this controller is used this rotation amount of decision based on the data cell storage volume of this buffer.

16. device as claimed in claim 15, more comprise another buffer, be coupled to this input and this combiner with when this first described data cell of importing group is stored in this buffer of mentioning at first, store this second input group, wherein, this controller is used this rotation amount of decision based on the summation of the storage volume of data cell separately of described buffer.

17. device as claimed in claim 13, it provides as synchronous optical network card, Ethernet card, reaches token ring card.

18. device as claimed in claim 13, wherein, this data path is skipped this buffer.

19. a data alignment device, it comprises:

Input, the input of importing group in order to the parallel format of receiving digital data unit is temporary serial;

The data alignment device is coupled to this input and responds the temporary series of this input is exported group with the parallel format that produces described unit of digital data the temporary series of output;

Output is coupled to this data alignment device to export the temporary series of this output;

This data alignment utensil has buffer, be coupled to this input with when group is imported in this input reception second, store the data cell of the first input group, and combiner, be coupled to this buffer and this input, this combiner comprises circulator and controller, wherein this circulator be coupled to this input with rotate this second the input group data cell with locate this second the input group the selected data unit, make this combiner can parallel connection described selected data unit and be stored in all described data cells of this buffer, use and produce a described output group that exports in the group, this controller determines this circulator to rotate the rotation amount of the described data cell of this second input group, this controller is coupled to this circulator to provide the information of representing this rotation amount to this circulator, thereby this combiner is stored in all described data cells of this buffer and all described selected data unit of this second input group in order to utilize parallel format combination, uses the temporary transient parallel format group of the data cell that produces the temporary series reception of this input;

This data alignment utensil has another buffer, uses when this input receives the 3rd input group, stores this temporary transient parallel format group; And data path, be coupled to this combiner and this another buffer and can transfer to this another buffer, and do not need to be stored in the buffer that this is mentioned at first to allow this temporary transient parallel format group; And

The output that this combiner is coupled to this another buffer is stored in all the described data cells of this another buffer and the selected data unit of the 3rd input group to utilize the parallel format combination, uses another parallel format group that produces the temporary serial data cell that receives of this input.

20. device as claimed in claim 19, wherein, this combiner is operated to utilize the parallel format combination to be stored in all described data cells of this another buffer and all described data cells of the 3rd input group, use and produce this another group, wherein, this another group is another temporary transient group, wherein, this data path allows the temporary transient group of transmission this another to this another buffer, and do not need to be stored in the buffer that this is mentioned at first, wherein, when this another buffer receives the 4th input group in this input, store this another temporary transient group, and wherein, this combiner utilizes parallel format to make up all the described data cells of this another temporary transient group and the selected data unit of the 4th input group, uses the another parallel format group of the data cell that produces the temporary series reception of this input.

21. device as claimed in claim 20, wherein, this another parallel format group is a described output group.

22. device as claimed in claim 20, wherein, this combiner is operated to utilize the parallel format combination to be stored in all described data cells of this another buffer and all described data cells of the 3rd input group, use the temporary transient group of generation this another, wherein, this another temporary transient group is a described output group.

23. device as claimed in claim 19, wherein, this data alignment device comprises another data path, is coupled to this output of this combiner and this another buffer, uses the data cell that allows to be stored in this another buffer and inputs to this combiner.

24. device as claimed in claim 23, wherein, this combiner comprises selector, and its input is coupled to this input of mentioning at first and this another data path separately, and its output is coupled to this data path of mentioning at first.

25. device as claimed in claim 24, wherein, this data alignment device comprises another selector, and its input is coupled to this output of this another buffer, and its output is coupled to this another data path.

26. device as claimed in claim 25, wherein, this another selector has input, is coupled to the output of this buffer of mentioning at first.

27. device as claimed in claim 23, wherein, this data alignment device comprises selector, and its input is coupled to this output of this another buffer, and its output is coupled to this another data path.

28. device as claimed in claim 27, wherein, this selector has input, is coupled to the output of this buffer of mentioning at first.

29. device as claimed in claim 19, wherein, this combiner is carried out described combination operation with as parallel attended operation.

30. device as claimed in claim 19, wherein, the header assembly that each described input group is a data packet, body assembly, and one of ending assembly.

31. device as claimed in claim 30, wherein, one of described body assembly is the part body assembly.

32. device as claimed in claim 19, wherein, each described data cell is a byte.

33. device as claimed in claim 20, wherein, this another temporary transient group is a described output group.

34. device as claimed in claim 19, wherein, this data path is skipped this buffer of mentioning at first.

35. a data alignment method, its step comprises:

The temporary series of input of the parallel format input group of receiving digital data unit;

Respond the temporary series of this input, use the temporary series of output of the parallel format output group that produces described unit of digital data, it comprises: when receiving the second input group, the data cell that stores the first input group is in buffer;

This generation step comprises: the temporary transient parallel format group that produces data cell that the temporary series of this input receives, it comprises: rotate this second the input group data cell with the location in order to all described data cells that are stored in this buffer parallel connected this second the input group the selected data unit, and parallel connection described selected data unit and all described data cells of being stored in this buffer are to produce an output group in the described output group, and based on the data cell storage volume of this buffer, and the rotation amount of the described data cell of this second input group of decision rotation, thereby utilize the parallel format combination to be stored in all described data cells of this buffer and all described selected data unit of this second input group; And

This temporary serial step of output that produces the parallel format output group of described unit of digital data comprises: utilize this temporary transient group to produce a described output group, this utilizes step to comprise: when receiving the 3rd input group, store this temporary transient group in another buffer, this storing step of mentioning at last comprises: transmit this temporary transient group to this another buffer, and do not need to be stored in the buffer that this is mentioned at first, and this utilizes step to comprise: produce another parallel format group of the data cell of the temporary series reception of this input, this step that produces another parallel format group of the temporary serial data cell that receives of this input comprises: all described data cells and the 3rd of utilizing the parallel format combination to be stored in this another buffer are imported the selected data unit of group.

36. method as claimed in claim 35, wherein, this combination step of mentioning at last comprises: utilize the parallel format combination to be stored in all described data cells of this another buffer and all described data cells of the 3rd input group, wherein, this another group is another temporary transient group, wherein, this utilizes step to comprise: utilize this another temporary transient group to produce the another parallel format group of data cell that the temporary series of this input receives, the step of utilizing that this is mentioned at last comprises: when receiving the 4th input group, store this another temporary transient group in this another buffer, this storing step of mentioning at last comprises: transmit this another temporary transient group to this another buffer, and not needing to be stored in the buffer that this is mentioned at first, the step of utilizing that this is mentioned at last comprises: utilize parallel format combination to be stored in all the described data cells of this another temporary transient group of this another buffer and the selected data unit of the 4th input group.

37. method as claimed in claim 36, wherein, this another parallel format group is a described output group.

38. method as claimed in claim 35, wherein, this combination step of mentioning at last comprises: utilize the parallel format combination to be stored in all described data cells of this another buffer and all described data cells of the 3rd input group, and wherein, this another group is a described output group.

39. method as claimed in claim 35, wherein, this another group is a described output group.

40. method as claimed in claim 35, wherein, this transmitting step comprises: the buffer that this is mentioned is at first skipped by this another temporary transient group.

41. a device, in order to connect digital data processor and digital communication networking, it comprises:

First FPDP, it allows to utilize the digital data exchange of this data processor;

Second FPDP, it allows to utilize the digital data exchange of this telecommunication network; And

The data alignment device, be coupled in this first and this second FPDP between, it has input, in order to the temporary series of input of the parallel format of receiving digital data unit input group; The data alignment device is coupled to this input and responds the temporary series of this input is exported group with the parallel format that produces described unit of digital data the temporary series of output; And output, be coupled to this data alignment device to export the temporary series of this output;

This data alignment utensil has buffer, be coupled to this input with when group is imported in this input reception second, store the data cell of the first input group, and combiner, be coupled to this buffer and this input, this combiner comprises circulator and controller, wherein this circulator be coupled to this input with rotate this second the input group data cell with locate this second the input group the selected data unit, make this combiner can parallel connection described selected data unit and be stored in all described data cells of this buffer, use and produce a described output group that exports in the group, this controller determines this circulator to rotate the rotation amount of the described data cell of this second input group, this controller is coupled to this circulator to provide the information of representing this rotation amount to this circulator, thereby this combiner is in order to all described selected data unit of utilizing parallel format combination and being stored in all described data cells of this buffer and this second input group temporary transient parallel format group with the data cell that produces the temporary series of this input and receive, and this data alignment device operation is exported group to utilize this temporary transient group to produce described one;

This data alignment utensil has another buffer, uses when this input receives the 3rd input group, stores this temporary transient group; And data path, be coupled to this combiner and this another buffer, use this temporary transient group of permission and can transfer to this another buffer, and do not need to be stored in the buffer that this is mentioned at first; And

The output that this combiner is coupled to this another buffer is stored in all the described data cells of this another buffer and the selected data unit of the 3rd input group to utilize the parallel format combination, uses another parallel format group that produces the temporary serial data cell that receives of this input.

42. device as claimed in claim 41, it provides as synchronous optical network card, Ethernet card, reaches token ring card.

43. device as claimed in claim 41, wherein, this data path is skipped this buffer of mentioning at first.

44. device as claimed in claim 41, wherein, this data alignment device comprises another data path, is coupled to this input of this combiner and this another buffer, uses the data cell that allows to be stored in this another buffer and inputs to this combiner.

45. device as claimed in claim 44, wherein, this combiner comprises selector, and its input is coupled to this input of mentioning at first and this another data path separately, and its output is coupled to this data path of mentioning at first.

46. device as claimed in claim 45, wherein, this data alignment device comprises another selector, and its input is coupled to this output of this another buffer, and its output is coupled to this another data path.

47. device as claimed in claim 46, wherein, this another selector has input, is coupled to the output of this buffer of mentioning at first.

48. device as claimed in claim 44, wherein, this data alignment device comprises selector, and its input is coupled to this output of this another buffer, and its output is coupled to this another data path.

49. device as claimed in claim 48, wherein, this selector has input, is coupled to the output of this buffer of mentioning at first.

50. device as claimed in claim 41, wherein, this combiner is carried out described combination operation with as parallel attended operation.

51. device as claimed in claim 41, wherein, the header assembly that each described input group is a data packet, body assembly, and one of ending assembly.

52. device as claimed in claim 41, wherein, one of described body assembly is the part body assembly.

53. device as claimed in claim 41, wherein, this another parallel format group is a described output group.

Images