CN1472680A - Crosstalk reduction method used in standard cell overall wiring process - Google Patents

Abstract

The method for reducing crosstalk used in the overall wiring of standard cells belongs to the field of computer-aided design of integrated circuits, and is characterized in that it is carried out after optimizing the time delay in the overall wiring of standard cells, and it first performs signal line on the basis of statistical circuit crosstalk. The crosstalk reduction control between networks, and then optimize the delay judgment according to the delay constraint index given by the user. If it is not satisfied, continue to iterate the delay optimization and crosstalk reduction control program until a set of optimization goals is obtained. All nets in the general wiring diagram up to the wiring tree. After optimizing the circuit delay program, it reduces the crosstalk between the signal nets by controlling the parallel wiring length and wiring interval of adjacent nets; the judgment parameter is the change value of the crosstalk overflow of the nets. Compared with reducing crosstalk in the subsequent stages, it has more space; while reducing crosstalk, especially critical path crosstalk, it also takes delay performance into consideration.

Description

Crosstalk reduction method used in standard cell overall wiring process

technical field

The method of reducing crosstalk used in the overall wiring of standard cells belongs to the field of integrated circuit computer aided design (IC CAD), especially the field of overall wiring of standard cells (SC).

Background technique

In integrated circuit (IC) design, physical design is the main link in the IC design process, and it is also the most time-consuming step. A computer-aided design technique related to physical design is called layout design . In layout design, overall routing is an extremely important link, and its results have a great impact on the success of the final detailed routing and the performance of the chip.

The manufacturing process of integrated circuits is currently entering the nanometer (nanometer) stage from ultra-deep submicron (VDSM) ; the design scale of integrated circuits is developing from very large-scale (VLSI) , very large-scale (ULSI) to G-scale (GSI) ; The operating frequency of integrated circuits is moving from GHz to higher. Under such conditions, on the one hand, the delay of the interconnect line in the design of the integrated circuit has greatly exceeded the delay of the gate , becoming the main factor affecting the performance of the chip. At this time, in addition to optimizing wiring congestion , delay optimization must also be performed. On the other hand, due to the closer arrangement of modules and interconnection lines, the higher operating frequency of the circuit makes the coupling effect between the interconnection lines very strong: this effect further deteriorates the circuit delay ; especially, the coupling capacitance caused by the line Crosstalk becomes a prominent problem. Therefore, if the performance optimization of standard unit overall wiring is still carried out according to the previous method and the influence of crosstalk between lines is ignored, the actual wiring results obtained will be greatly affected in performance, and even the circuit will not work normally.

Crosstalk, produced by capacitive coupling between two adjacent wires, can cause incorrect logic transitions in circuit signals. As a result, the performance of the chip is unlikely to meet the design goals. This problem seriously hinders the further improvement of circuit integration and operating frequency, as well as the further reduction of feature width. Therefore, under the new technical development and process requirements, it is necessary to study the overall wiring method that eliminates crosstalk and optimizes time delay and wiring congestion .

Among the relevant domestic and foreign studies that have been reported and can be consulted, we list, analyze and summarize as follows:

Regarding the representative time delay optimization method, in the literature [applied national invention patents: Hong Xianlong, Jing Tong, Xu Jingyu, Zhang Ling, Hu Yu. Invention name: Standard cell overall wiring method for time delay optimization considering coupling effect. Application date: 2002/12/17. Application number: 02156622.4.] has carried out a comprehensive analysis and introduction.

Two documents [National invention patents that have been applied for: Hong Xianlong, Jing Tong, Bao Haiyun, Cai Yici, Xu Jingyu. Invention name: Standard cell overall wiring method based on key network technology to optimize delay. Application date: 2002/01/15. Application number: 02100354.8. It was published on 2002/07/24. ] and [National invention patents that have been applied for: Hong Xianlong, Jing Tong, Xu Jingyu, Zhang Ling, Hu Yu. Invention name: Overall wiring method of standard cells for delay optimization considering coupling effects. Application date: 2002/12/17. Application number: 02156622.4.] is a new time delay optimization method proposed by us successively. Among them, we first proposed a delay-optimized overall routing method based on key network technologies in the former. The optimization idea of this method has outstanding advantages over other previous methods, and can achieve better delay optimization results. However, due to the limitations of the conditions at that time, the influence of the coupling effect to further deteriorate the circuit delay has not been considered, which makes this method insufficient under the new process conditions. In order to make up for the deficiency, we propose a general layout method of standard cells in the latter which considers the coupling effect and optimizes the time delay . This approach calculates latency more accurately and is more consistent with reality.

However, the above-mentioned works are all focused on the goal of delay optimization, and the influence of crosstalk on circuit performance has not been considered yet, and related optimization work has not been carried out.

For research work related to crosstalk, our review literature in 2001 [Jing Tong, Hong Xianlong, Cai Yici, Bao Haiyun, Xu Jingyu. Key technologies and research progress of performance-driven overall wiring. Journal of Software. 2001, 12(5): 677 -688.] carried out a more detailed analysis and introduction. In addition to briefly enumerating the content of crosstalk analysis in this literature, the following typical related research work will also be supplemented.

The research on crosstalk can be traced back to the work [Catt, I. Crosstalk (Noise) in Digital Systems. IEEE Transactions on Electronic Computers, 1967, 16 (6): 743-763.] many years ago, which clearly introduces The formation of crosstalk and its basic concepts are explained, but it is based on printed circuit boards (PCBs) rather than IC chips. Many years later, with the development of IC technology, research work based on crosstalk in IC wiring was gradually carried out. These works can be divided into two categories: research on crosstalk calculation models ; crosstalk optimization work in wiring .

In 7 papers [Vittal, A., Marek-Sadowska, M.Crosstalk Reduction for VLSI.IEEETransactions on CAD, 1997, 16(3): 290-298.], [Yang, X.Crosstalk-Driven Layout[M.S.Thesis ]. Santa Barbara, California: University of California, 1996.], [Devgan, A. Efficient Coupled Noise Estimation for On-Chip Interconnects. In: IEEE, ACM eds. Proceedings of IEEE/ACM International Conference on Computer-Aided Design( ICCAD). Los Alamitos: IEEE Computer Society Press, 1997.147-153.], [Kawaguchi, H., Sakurai, T. Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. In: IEEE, ACM eds. Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC). Los Alamitos: IEEE Computer Society Press, 1998.], [Sakurai, T. Closed Form Expressions for interconnection Delay, Coupling and Crosstalk in VLSI's. IEEE Transactions on Electron Devices, 1993, 40(1) : 118-124.], [Vittal, A., Chen, L.H., Marek-Sadowska, M. et al. Crosstalk in VLSI Interconnections. IEEE Transactions on CAD, 1999, 18(12): 1817-1824.], [Kuhlmann , M., Sapatnekar, S.S. Exact and Efficient Crosstalk Estimation. IEEE Transactions on CAD, 2001, 20(7): 858-865.], mainly carried out the research work on the crosstalk calculation model. The literature [Parakh, P.N., Brown, R.B.Crosstalk Constrained Global Route Embedding.In: ACM ed.Proceedings of International Symposium on Physical Design (ISPD).New York: ACM Press, 1999.201-206.] is a comprehensive calculation model of crosstalk + delay research work. Literature [Jiang, H.R., Jou J.Y., Chang Y.W. Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. In: ACM, IEEE eds. Proceedings of Design Automation Conference (DAC). New York: ACM Press 9, 0-95. .] The main contribution is to propose an accurate crosstalk calculation model, and the auxiliary work is to optimize the crosstalk based on the proposed calculation model by changing the design size of the circuit components. Although the word "crosstalk" can be seen in these studies, the specific research work carried out by it has not much connection with the main work of this patent, so it will not be carefully analyzed and explained one by one here.

There are 20 papers that mainly focus on optimizing crosstalk in wiring. Here, the introduction will be analyzed to point out the difference between them and the work of this patent. Among them, the crosstalk optimization work of 15 documents is carried out after the detailed wiring (6: [Chaudhary, K., Oniozawa, A., Kuh, ESA Spacing Algorithm for PerformanceEnhancement and Crosstalk Reduction.In:IEEE, ACM eds.Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Los Alamitos: IEEE Computer Society Press, 1993.697-702.], [Gao, T., Liu, CLMinimum Crosstalk Switchbox Routing. In: IEEE, ACM eds. Proceedings of IEEE/ ACM International Conference on Computer-Aided Design (ICCAD). Los Alamitos: IEEE Computer Society Press, 1994.610-615.], [Gao, T., Liu, CLMinimum Crosstalk Channel Routing. IEEE Transactions on CAD, 1996, 15(5): 465- 474.], [Kirkpatrick, D., Sangiovanni-Vincentelli, A. Techniques for Crosstalk Avoidance in the Physical Design of High-performance Digital System. In: IEEE, ACM eds. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD ). Los Alamitos: IEEE Computer Society Press, 1994.616-619.], [Thakur, S., Zhao, KY, Wong, DF An Optimal Layer Assignment Algorithm for Minimizing Cross stalk for Three Layer VHV Channel Routing. In: IEEE ed. Proceedings of International Symposium on Circuit and Systems (ISCAS). Los Alamitos: IEEE Computer Society Press, 1995.207-210.], [Zhang Xuliang, Zhao Mei, Fan Mingyu, etc. An optimization algorithm for reducing crosstalk in the physical design of VLSI circuits. Computer-aided design and graphics Acta Sinica Sinica. 2001, 13(4): 289-293.]), in detailed routing (6 articles: [Zhou, H., Wang, DFAn Optimal Algorithm for River Routing with Crosstalk Constrains.In: IEEE, ACM eds. Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Los Alamitos: IEEE Computer Society Press, 1996.310-315.], [Jhang, KS, Ha, S., Jhon, CSCOP: A Crosstalk Optimizer for Gridded Channel Routing. IEEE Transactions on CAD, 1996, 15(4): 424-437.], [Saxena, P., Liu, CLC Crosstalk Minimization Using Wire Perturbations. In: ACM, IEEE eds. Proceedings of Design Automation Conference (DAC). New York: ACM Press, 1999.100-103.], [Morton, PB, Dai, W. An Efficient Sequential Quadratic Programming Formulation of Optimal Wire Spacing for Cross-Talk Noise Avoidance Routing. In: ACM ed. Proceedings of International Symposium on Physical Design (ISPD ). New York: ACM Press, 1999.22-28.], [Sapatnekar, SSATiming Model Incorporating the Effect of Crosstalk on Delay and its Application to Optimal Channel Routing. IEEE Transactions on CAD, 2000, 19(5): 550-559.] , [Hsu, KC, Lin, YC, Chiu, PX, and Hsieh, TMMinimum Crosstalk Channel Routing with Dogleg. In: IEEE ed. Proceedings of International Symposium on Circuit and Systems (ISCAS). Los Alamitos: IEEE Computer Society Press, 2000.73-76 .]), after overall routing (3 articles: [Xue, TX, Kuh, ES, Wang, DSPost Global Routing Crosstalk Risk Estimation and Reduction.In: IEEE, ACM eds. Proceedings of IEEE/ACMInternational Conference on Computer-Aided Design (ICCAD ). Los Alamitos: IEEE Computer Society Press, 1996.302-309.], [ Xue, TX, Kuh, ES, Wang, DSPostGlobal Routing Crosstalk Synthesis. IEEE Transactions on CAD, 1997, 16(12): 1418-1430.], [ Stohr, T., Alt, M., Hetzel, A., et al. Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips. In: ACM ed. Proceedings of International Symposium on Physical Design (ISPD). New York: ACM Press, 1998.211 -218.]) and other layout stages. Literature [Tseng, HP, Scheffer, L., Sechen, C. Timing and Crosstalk Driven Area Routing. In: ACM, IEEE eds. Proceedings of Design Automation Conference (DAC). New York: ACM Press, 1998.378-381.] The work is oriented to the building block (BBL) design pattern rather than the standard cell (SC) design pattern, and its optimization is carried out in the stage after the general layout. Literature [Kastner, R., Bozorgzadeh, E., Sarrafzadeh, M. AnExact Algorithm for Coupling-Free Routing. In: ACM ed. Proceedings of International Symposium on Physical Design (ISPD). New York: ACM Press, 2001.10-15.] What is studied is the general topology model that can reduce the coupling effect, which is not closely related to the specific routing stage, and does not involve other optimization goals. However, the crosstalk optimization work of this patent is carried out during the overall wiring process.

There are 3 documents on crosstalk optimization in the overall wiring process. Among them, 2 documents [Zhou, H., Wang, DFGlobal Routing with Crosstalk Constrains.In: ACM, IEEE eds.Proceedings of Design Automation Conference (DAC). New York: ACM Press, 1998.374-377.] and [Zhou, H ., Wong, DFGlobal Routing with Crosstalk Constraints. IEEE Transactions on CAD, 1999, 18(11): 1683-1688.] A two-stage heuristic approach is used to control crosstalk: first a new The Steiner tree construction algorithm is used to construct an initial Steiner tree for each net, and then estimate the crosstalk risk of each net, and the nets that exceed the standard will be dismantled and redistributed. The Lagrangian relaxation technique is used in the redistribution process. In this algorithm , the problem of delay optimization is not considered at the same time . Literature [Zhuang Changwen, Fan Mingyu, Li Chunhui, Yu Juebang. A general routing algorithm driven by crosstalk and delay. Journal of University of Electronic Science and Technology of China. 2000, 29(3): 233-238.] carried out crosstalk and delay optimization work, It is oriented to the building block (BBL) design mode rather than the standard cell (SC) design mode, and the routing area is the channel between the modules rather than the entire chip plane. It has a small number of test case nets and a long method implementation time. At the same time, the three documents used the benchmarks of the academic world in the test, did not use the industrial example circuit, and did not use the industrial accurate table lookup performance parameter calculation model.

The work of this patent is to eliminate crosstalk and jointly optimize optimization objectives such as time delay and wiring congestion. Its test uses It is an example circuit in the industry and a calculation model of precise look-up table performance parameters. The optimization work carried out is more extensive than that in the above literature Pan and comprehensive, the optimization method is also different from them.

1 US patent for optimizing crosstalk has been retrieved, see [US Patent: United States Patent, Patent No.: US6218631 B1, Date of Patent: Apr.17, 2001. Hetzel et al. "Structure for Reducing Cross-Talk in VLSI Circuits and Method of Making Same Using Filled Channels to Minimize Cross-Talk".]. It reduces crosstalk by inserting shielded wires (voltage and/or GND metal lines) in unoccupied wiring channels in the detailed wiring stage, which is different from the work of this patent.

Contents of the invention

The object of the present invention is to propose a method for reducing crosstalk used in the overall wiring of standard cells. The method described in the present invention is combined with the time delay optimization method for which the inventor has applied for two Chinese invention patents to form a standard cell overall wiring method that reduces crosstalk and optimizes time delay and wiring congestion. The general idea is: first use the existing technology (the technology in the national invention patent we applied for before) to construct a delay-optimized Steiner tree under the condition that each line network is not subject to any constraints. Then, routing congestion is optimized using existing techniques (from our previously published academic papers) to eliminate crowded edges. Then use the existing technology (the technology in the national invention patent we applied for before) to optimize the delay . Thereafter, according to the method for reducing crosstalk proposed by the present invention, the crosstalk situation of the circuit is counted, and the crosstalk is controlled and reduced . Finally, compare the delay constraint index parameter array given by the user with its one-to-one corresponding optimized delay from input PI to output PO. If it is not satisfied, continue to iterate the delay optimization and crosstalk control program until the obtained A set of all nets satisfying the optimization goal ends in the routing tree in the GRG.

The present invention is characterized in that it is performed after optimizing wiring congestion and optimizing time delay in the overall wiring process of standard cells. It first performs crosstalk reduction control between signal lines and networks on the basis of statistical circuit crosstalk, and then performs optimization from the input node PI to the output node PO according to the time delay constraint index parameter array given by the user. If it is not satisfied, continue to iterate the delay optimization and crosstalk reduction control procedures including wiring congestion until a set of wiring trees in the general wiring diagram (GRG) of all nets that meet the optimization goal is obtained So far; it reduces the crosstalk between signal nets by controlling the parallel trace length and wiring spacing of adjacent nets according to the following four assumptions after executing the optimized circuit delay program:

Assumption 1: In a certain GRG grid i, the length of parallel traces that generate crosstalk between adjacent line segments is the length li of the GRG grid;

Assumption 2: In a certain GRG grid i, each line network can only produce crosstalk with the line network located on its left and right (or above and below);

Assumption 3: In a certain GRG grid i, the wiring interval of adjacent line segments is the average wiring interval of all line segments in the GRG grid;

Hypothesis 4: Since GRG grids are generally divided by integer multiples of unit rows, there will be no crosstalk between line segments in different GRG grids;

According to the above assumptions, when performing crosstalk reduction control, with the help of a computer, it contains the following steps in sequence:

(1) Setting: N _n is the total number of nets, S _n is the total number of GRG grids that net j passes through, and X _j is the amount of crosstalk that net j defined by the user can tolerate;

(2) Calculate the amount of crosstalk Ct _j for each wire net;

(3) Calculate the total crosstalk overflow of the current wiring solution S, that is, the sum of the crosstalk overflow of all wire nets

即其所受到的串扰量Ct_j和所能忍受的串扰量x_j的差值： $\tilde{C}{t}_j=C{t}_j-x_j;$ (3.1) Calculating the crosstalk overflow of the line net j

That is, the difference between the amount of crosstalk Ct _j it suffers and the amount of crosstalk x _j it can tolerate: $\tilde{C}{t}_j=C{t}_j-x_j;$

(3.2) Calculate the total crosstalk overflow of the current wiring solution S $\tilde{C}t\left(S\right)=\underset{j=1}{\overset{N_{\mathrm{no}}}{\mathrm{\Σ}}}\tilde{C}{t}_j=\underset{j=1}{\overset{N_{\mathrm{no}}}{\mathrm{\Σ}}}(C{t}_j-x_j);$

(4) Find out all the wire nets whose crosstalk exceeds the threshold, as the set Vt;

(5) Generate a random subset Vs of Vt;

(6) For each net in Vs, sort the edges it passes through according to the amount of crosstalk, and find out the edge whose crosstalk amount exceeds the threshold in the first m segments;

(7) try to redistribute the m segment edges, and try to make the sum of the crosstalk variation on the m segment edges smaller;

以确定“代价”最小的布线树；是线网j在重布前、后的串扰溢出量的变化量，即： $\mathrm{\Δ}\tilde{C}{t}_j=\underset{s_i\∈T_j^{\′}}{\mathrm{\Σ}}\mathrm{\Δ}\tilde{C}{t_j}^{s_i}+\underset{s_i\∈T_j}{\mathrm{\Σ}}\mathrm{\Δ}\tilde{C}{t_j}^{s_i};$ (8) Record the current wiring tree, and compare the "cost" with the wiring tree that the line network has constructed

To determine the wiring tree with the smallest "cost"; is the variation of the crosstalk overflow of the net j before and after redistribution, that is: $\mathrm{\Δ}\tilde{C}{t}_j=\underset{{\mathrm{the\; s}}_i\∈T_j^{\′}}{\mathrm{\Σ}}\mathrm{\Δ}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}+\underset{{\mathrm{the\; s}}_i\∈T_j}{\mathrm{\Σ}}\mathrm{\Δ}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i};$

是线网j在重布前、后在GRG网格s_i上的串扰溢出量的变化量；in:

is the variation of the crosstalk overflow of the line net j on the GRG grid s _i before and after redistribution;

是线网j由于新布布线树T’_j，在T’_j所经过的所有GRG网格边上的串扰溢出量的变化量之和；

Is the sum of the crosstalk overflow changes on all GRG grid edges that T' _j passes due to the new layout of the wiring tree T' _j in the line net j;

是线网j由于撤消布线树T_j，在T_j所经过的所有GRG网格边上的串扰溢出量的变化量之和；

is the sum of the crosstalk spillover changes on all GRG grid edges that T _j passes due to the undoing of wiring tree T _j in line net j;

T _j and T' _j are the wiring trees of net j before and after redistribution, respectively;

按“代价”最小重布布线树所在的线网：(9) Calculate the total "cost" of the routing solution for each net in Vs

Redistribute the wire net where the wiring tree is located according to the "cost" minimum:

包括重布对线网本身以及其他线网带来的串扰量的变化，它可表示如下： $\mathrm{\Δ}\tilde{C}t=k_1\mathrm{\Δ}\tilde{C}{t}_j+k_2\underset{i=1,i\≠j}{\overset{N_n}{\mathrm{\Σ}}}\mathrm{\Δ}\tilde{C}{t}_i$ ， $=k_1(\underset{s_i\∈T_j^{\′}}{\mathrm{\Σ}}\mathrm{\Δ}\tilde{C}{t_j}^{s_i}+\underset{s_i\∈T_j}{\mathrm{\Σ}}\mathrm{\Δ}\tilde{C}{t_j}^{s_i})+k_2\underset{i=1,i\≠j}{\overset{N_n}{\mathrm{\Σ}}}\underset{s_i\∈T_j^{\′}U{T}_j}{\mathrm{\Σ}}\mathrm{\Δ}\tilde{C}{t_i}^{s_i}$ $k_1+k_2=1;$ total cost

Including the change of crosstalk caused by redistribution to the wire net itself and other wire nets, it can be expressed as follows: $\mathrm{\&Delta;}\tilde{C}t=k_1\mathrm{\&Delta;}\tilde{C}{t}_j+{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A0312409500181.png"\; state="\{\{state\}\}">k</figure-callout>}}_2\underset{i=1,i\&NotEqual;j}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}\tilde{C}{t}_i$ , $=k_1(\underset{{\mathrm{the\; s}}_i\&Element;T_j^{\&prime;}}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}+\underset{{\mathrm{the\; s}}_i\&Element;T_j}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i})+{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A0312409500181.png"\; state="\{\{state\}\}">k</figure-callout>}}_2\underset{i=1,i\&NotEqual;j}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}\underset{{\mathrm{the\; s}}_i\&Element;T_j^{\&prime;}u{T}_j}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_i}^{{\mathrm{the\; s}}_i}$ $k_1+{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A0312409500181.png"\; state="\{\{state\}\}">k</figure-callout>}}_2=1;$

表示除了线网j以外的其余所有线网在受重布影响的GRG网格上的串扰溢出量的变化量。in:

Indicates the variation of the crosstalk overflow of all other nets except net j on the GRG grid affected by the redistribution.

For the GRG grid s _i constituting the critical path, the change of the crosstalk spillover amount of the line net j on s _i before and after redistribution is in $C{t}_j^{\&prime;{\mathrm{the\; s}}_i}-C{t_j}^{{\mathrm{the\; s}}_i}>0$ hour, $\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}=\mathrm{\&beta;}(C{t}_j^{\&prime;{\mathrm{the\; s}}_i}-C{t_j}^{{\mathrm{the\; s}}_i}),\mathrm{\&beta;}>1.$ .

The crosstalk is calculated as follows: $V_{\mathrm{cross\; talk}}=\frac{C_{\mathrm{couponing}}}{C_{\mathrm{total}}},$

Among them: C _coupling is the coupling capacitance; C _total includes ground capacitance, coupling capacitance and load capacitance.

The experiment proves that after the crosstalk is reduced, the total crosstalk overflow of the wiring solution is significantly reduced, and the number of nets exceeding the crosstalk threshold is also controlled. At the same time, the delay performance of the line network has not deteriorated significantly.

Description of drawings

Figure 1: Schematic diagram of the general wiring.

Fig. 2: The overall program flow diagram of the present invention combined with delay optimization.

Figure 3: GRG generated on chip plane with multilayer wiring.

Figure 4: Illustration of an example of the crosstalk reduction process.

Detailed ways

(1) Initialization:

Setting: number of rows N _nr of GRC (Global Routing Cell), number of columns N _nc ,

Coordinates v _{nr, nc} , (x, y) of all vertices in the GRG (general wiring diagram), that is, the central point of the GRC, where nr and nc represent rows and columns respectively, and x and y are the coordinates of the chip plane;

The capacity C _k of each edge e _k in GRG,

The total number of nets in the circuit Nsum, the netlist NetlistIndex of each net, the source point s and drain point t of each net,

All electrical performance parameters of the circuit,

The user-specified delay constraint index parameters;

(2) Generate GRG:

Read in N _nr , N _nc necessary to divide the GRC on a multilayer wiring chip,

Read in the coordinate values of each vertex necessary to generate the GRG on the multilayer wiring chip,

Number the vertices and the edges e _k connecting every two adjacent vertices;

(3) Read in the detailed connection relationship of the circuit, that is, the netlist:

Read the total number Nsum of nets in the circuit,

Read in the netlist of each net,

Number each line net in the order of reading;

(4) read in all electrical performance parameters and constraint indexes of the circuit, and assign them to corresponding variables and arrays;

(5) Construct the initial wiring tree, that is, the Steiner tree, that is, construct a time-delay-optimized Steiner tree under the condition that each line network is not subject to any constraints;

(6) Count the total available routing resources and mark the crowded area:

According to the initial solution obtained after the execution of step (5), count the used amount d _k of each GRG edge, compare C _k with d _k , if C _k <d _k , it means that there is wiring congestion, and get the crowded area. The crowded GRG edge is marked, and the marked line net is the crowded line net;

(7) Use the SSTT.cpp program to optimize wiring congestion and eliminate crowded edges;

(8) Use the Coll_Timing_Info.cpp program to count the circuit delay information, and then calculate the delay according to the wiring results after the execution of step (7), and obtain the delay value of each electrical signal transmission path from input PI to output PO.

(9) Optimize circuit time delay with CC_Timing.cpp program;

(10) Use Redu_Crot.cpp program to reduce circuit crosstalk : This method mainly considers the problem of crosstalk between signal nets, and controls the parallel trace length and wiring interval of adjacent nets . The specific solution adopted is: after one iteration, the information of all the wire nets whose crosstalk exceeds the threshold is collected. For wire nets that exceed the threshold, take certain measures to remove the wires and redistribute them so that the length of parallel wires can be reduced or the wiring interval can be increased. After several iterations, the nets whose crosstalk amount exceeds the threshold are controlled. At the same time, the redistribution of the wire net passing through the critical path is purposely controlled so that the delay is not affected.

According to the characteristics of the overall wiring, without loss of generality, four assumptions are put forward to simplify the problem to a certain extent. The 4 assumptions are as follows:

Assumption 1: In a certain GRG grid i, the length of parallel traces that generate crosstalk in adjacent line segments is the length li of the GRG grid.

Hypothesis 2 : In a certain GRG grid i, each line network can only produce crosstalk with the line network located on its left and right (or above and below).

Hypothesis 3: In a certain GRG grid i, the wiring interval of adjacent line segments is the average wiring interval of all line segments in the GRG grid.

Hypothesis 4 : Since GRG grids are generally divided into integral multiples of unit rows, there will be no crosstalk between line segments in different GRG grids.

Definition: N _n is the total number of nets, S _n is the total number of GRG grids that net j passes through, Ct _j is the amount of crosstalk suffered by net j, X _j is the crosstalk that net j defined by the user can tolerate amount (that is, the maximum crosstalk amount for which the correct logic function of net j is not destroyed). Crosstalk spillover of net j is the difference between the amount of crosstalk it receives and the amount of crosstalk it can tolerate, namely: $\tilde{C}{t}_j=C{t}_j-x_j$

Then, the total crosstalk overflow of the current wiring solution S is defined as the sum of the crosstalk overflow of all wire nets, namely: $\tilde{C}t\left(S\right)=\underset{j=1}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}\tilde{C}{t}_j=\underset{j=1}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}(C{t}_j-x_j)$

Given the current routing solution S, we can compute both the total crosstalk spillover and the crosstalk spillover on each net. If the wired network exceeds the threshold, take certain measures to remove the wires and rewire. The redistributed net will bring changes in the amount of crosstalk to itself and other nets. We use the combination of these two parts to represent the "cost" of rerouting a net . Crosstalk variation due to redistribution of net j can be defined as follows: $\mathrm{\&Delta;}\tilde{C}t=k_1\mathrm{\&Delta;}\tilde{C}{t}_j+{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A0312409500181.png"\; state="\{\{state\}\}">k</figure-callout>}}_2\underset{i=1,i\&NotEqual;j}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}\tilde{C}{t}_i$ $=k_1(\underset{N_i\&Element;T_j^{\&prime;}}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}+\underset{{\mathrm{the\; s}}_i\&Element;T_j}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i})+{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A0312409500181.png"\; state="\{\{state\}\}">k</figure-callout>}}_2\underset{i=1,i\&NotEqual;j}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}\underset{{\mathrm{the\; s}}_i\&Element;T_j^{\&prime;}u{T}_j}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}$ $(k_1+{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A0312409500181.png"\; state="\{\{state\}\}">k</figure-callout>}}_2=1)$

是线网j在重布前、后在GRG网格s_i上的串扰溢出量的变化量。

表示除了线网j以外的其余所有线网在受重布影响的GRG网格上的串扰溢出量的变化量。Where: T _j and T' _j are the wiring trees of net j before and after redistribution, respectively. is the variation of the crosstalk overflow of the net j before and after redistribution,

is the variation of the crosstalk overflow of the line net j on the GRG grid s _i before and after the redistribution.

Indicates the variation of the crosstalk overflow of all other nets except net j on the GRG grid affected by the redistribution.

为： $\mathrm{\&Delta;}\tilde{C}{t_j}^{s_i}=\mathrm{\&beta;}(C{t}_j^{\&prime;s_i}-C{t_j}^{s_i})\mathrm{\&beta;}>1\mathrm{if}(C{t}_j^{\&prime;s_i}-C{t_j}^{s_i}>0)$ In crosstalk control, considering the delay performance, we hope that the delay of the critical path can be protected. For the GRG grid s _i constituting the critical path, define the change of the crosstalk spillover amount of the line net j on s _i before and after redistribution

for: $\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}=\mathrm{\&beta;}(C{t}_j^{\&prime;{\mathrm{the\; s}}_i}-C{t_j}^{{\mathrm{the\; s}}_i})\mathrm{\&beta;}>1\mathrm{if}(C{t}_j^{\&prime;{\mathrm{the\; s}}_i}-C{t_j}^{{\mathrm{the\; s}}_i}>0)$

in: and Respectively defined as the crosstalk value of net j on s _i before and after redistribution. In this way, if the crosstalk value generated by the GRG grid on the critical path increases after a certain line network is redistributed, the redistribution operation is discouraged, so as to avoid the consequences of increased congestion and poor time delay caused thereby. Therefore, it is possible to purposefully control the delay performance without deterioration.

The newly constructed wiring tree will be recorded and compared "cost" with all previously constructed wiring trees. Meanwhile, we randomly vary the order of rewiring nets to expand the search space. This method can be described as follows (including a total of 8 steps of S1-S8):

S1: Calculate the amount of crosstalk for each wire net;

S2: Calculate the total crosstalk overflow of the current wiring solution;

S3: find out all the nets whose crosstalk exceeds the threshold, as a set Vt;

S4: Generate a random subset Vs of Vt;

S5: For each net in Vs, sort the edges it passes through according to the amount of crosstalk, and find out the edges whose crosstalk amount exceeds the threshold in the first m segments;

S6: Try to redistribute the m-segment edges, and try to make the sum of the crosstalk changes on the m-segment edges smaller;

以确定“代价”最小的布线树；S7: Record the current wiring tree, and compare the "cost" with the wiring tree once constructed by the wire net

To determine the wiring tree with the smallest "cost";

S8: Calculate the total "cost" of the routing solution for each net in Vs Redistribute the wire net where the routing tree with the smallest "cost" is located.

The crosstalk calculation formula used is as follows: $V_{\mathrm{cross\; talk}}=\frac{C_{\mathrm{couponing}}}{C_{\mathrm{total}}}$ Among them: C _total includes ground capacitance, coupling capacitance and load capacitance, and C _coupling is coupling capacitance.

(11) Judging whether the wiring delay meets the constraint index:

If: delay optimization result > delay constraint index, continue to execute delay optimization and crosstalk control procedures;

If: delay optimization result ≤ delay constraint index, the program terminates.

Below in conjunction with example, specifically describe as follows:

For the current multi-layer wiring technology in IC design, the routing area is no longer a wiring channel between units, but a complete chip plane. The grid method can be used to divide the entire chip plane into several regions called the general wiring unit GRC according to the rows and columns, and then generate the dual graph of the GRC, that is, the general wiring diagram GRG shown in Figure 1. GRG consists of N _nr ×N _nc nodes and edges connecting these nodes. The coordinates of node v nr _{, nc} corresponding to GRC nr _{, nc} are the central point of GRC _{nr, nc} . The edge connecting two nodes v _{nr1, nc1} and v _{nr2, nc2} is called e _k ; l _k represents the distance between two nodes v _{nr1, nc1} and v _{nr2, nc2} , which is called the length of e _k ; C _k represents the length of two nodes v _{nr1, nc1} and v _{nr2, nc2} correspond to the number of lines that can pass through the adjacent sides of the two GRCs, which is called the capacity of e _k . Therefore, the pin point Pin to be connected in the line network is mapped to a series of corresponding nodes in the GRG where it is located. In this way, a net in GRG can be represented by a set of nodes, and the routing problem for a net corresponds to solving the Steiner tree problem of node set {v _{nr, nc} } in GRG.

The flowchart of this wiring method is shown in Fig. 2 .

Now a circuit example biu in the industry is used as an embodiment of the present invention, and the overall wiring method of the present invention is used for wiring in combination with the program flow of FIG. 2 . It has the following steps in order:

(1) Initialization:

Assume: the number of rows N _nr =66, the number of columns N _nc =26, as shown in FIG. 3 . At this time, there are a total of 1716 vertices in the GRG graph, and each vertex has a corresponding position coordinate (x, y). For example: in Figure 3, the position coordinates of v _{1, 1} vertex are (-3900, -3900) , the position coordinates of v _{1, 2} vertices are (-1700, -3900), which can be expressed by v _{nr, nc} (x, y), nr indicates the row on the GRG, nc indicates the column on the GRG, and the coordinates (x , y) is relative to the coordinate origin of the chip plane; there are 3340 sides in total, and each side has a capacity given by the user, from 14 to 19, for example: the side connecting v _1,1 and v _1,2 has a capacity of 14, and the edge connecting v _1,2 to v _1,3 has a capacity of 14.

Suppose: the total number Nsum of the line network is 943,

The delay constraint index given by the user, for example, one of the delay values is 10.000000ns.

(2) Generate GRG:

Read in N _nr = 66, N _nc = 26; according to the order of the first row and then the column, all the 1716 vertices are numbered, which are respectively 1 to 1716; and then according to the order of the first row and the second column, starting from the vertex No. 1, the 3340 vertices All GRG edges are numbered from 1 to 3340.

(3) Read in the detailed connection relationship of the circuit, that is, the netlist:

Read in the total number of nets in the circuit Nsum=943. According to the order in which the netlist is read, all the 943 nets are numbered, net 1~net 943 respectively. Then get a netlist including source point and leak point information for each line net, and its specific form is described as follows:

The netlist representation of line 8 is: (net8(vertexList 710 2 736 2 762 2 788 2 686 2 6602 634 2 608 1)),

The netlist representation of line 943 is: (net 943(vertexList 310 2 309 2 308 1)).

Taking net 943 as an example, it means: the 310th vertex is the leak point, the 309th vertex is the leak point, and the 308th vertex is the source point. Their general formula can be expressed as:

(net number(VertexList vertex number source point/leakage point...)),

Among them: the number 1 indicates the source point, and the number 2 indicates the leakage point.

(4) Read in all the electrical performance parameters and constraint indexes of the circuit, and assign them to corresponding variables and arrays:

Read in: assign the time delay constraint index parameters given by the user to the array, and one of the time delay constraint index (from PI to PO)=2.900000ns.

(5) Construct an initial delay-optimized routing tree:

Use ITDT_Tree.cpp program to complete. Among them, the "national invention patents that have been applied for: Hong Xianlong, Jing Tong, Xu Jingyu, Zhang Ling, Hu Yu. Invention name: Standard cell overall wiring method for delay optimization considering coupling effect. Application date: 2002/12/17. The application number is: 02156622.4." to realize this step. The form of the initial wiring tree obtained by this algorithm is as follows:

#Init_Steiner_Tree 8

(

(connect 710 711)

(connect 711 712)

(connect 736 762)

(connect 762 788)

(connect 710 736)

)

……………………

#Init_Steiner_Tree 943

(

(connect 308 309)

(connect 309 310)

)

Its general expression is:

#Init_Steiner_Tree XXX

(

(connect vertex number vertex number)

…………

(connect vertex number vertex number)

)

(6) Count the total available routing resources and mark the crowded area:

Use the Update_Resources.cpp program to complete. Count the used amount of each GRG side (that is, how many lines have passed the side) d _k , and then compare it with the allowable capacity C _k , if C _k <d _k , it indicates that there is wiring congestion, put it in the structure Marked as 1 in EdgeIndex; all line nets passing through the GRG edge marked as 1 are determined as crowded nets.

In this embodiment, a total of 124 GRG edges and 228 crowded nets are marked.

(7) Optimize wiring congestion and eliminate crowded edges:

Use SSTT.cpp program to complete. Among them, the "Wiring Congestion Optimization Algorithm Based on Search Space Traversal Technology (SSTT)" was used, which was published in the international academic conference in 2001: "Tong Jing, Xian-Long Hong, Hai-Yun Bao, et al.'An Efficient Congestion Optimization Algorithm for Global Routing Based on Search Space Traversing Technology'. In Proceedings of IEEE ASICON, 2001, 114~117".

In this embodiment, after the routing congestion optimization is performed, all the crowded edges are eliminated.

(8) Use the Coll_Timing_Info.cpp program to count the circuit delay information, and then calculate the delay according to the wiring results after the execution of step (7), and obtain the delay value of each electrical signal transmission path from input PI to output PO. Among them, the "national invention patents that have been applied for: Hong Xianlong, Jing Tong, Xu Jingyu, Zhang Ling, Hu Yu. Invention name: Standard cell overall wiring method for delay optimization considering coupling effect. Application date: 2002/12/17. The application number is: 02156622.4." to realize this step.

Then, compare the user delay constraint index with the delay value of each electrical signal transmission path calculated above, and analyze and obtain the critical path whose delay does not meet the user's requirement at this time.

(9) Optimize circuit delay:

Complete with the CC_Timing.cpp program. Among them, the "national invention patents that have been applied for: Hong Xianlong, Jing Tong, Xu Jingyu, Zhang Ling, Hu Yu. Invention name: Standard cell overall wiring method for delay optimization considering coupling effect. Application date: 2002/12/17. The application number is: 02156622.4." to realize this step.

In this embodiment, after the delay optimization is performed, the delay optimization task of the circuit is completed.

(10) Optimizing circuit crosstalk:

The circuit crosstalk was optimized with the program Redu_Crot.cpp.

The optimization process of the local crosstalk of the circuit can be shown in Figure 4. Among them, n1 to n5 represent the 1st to 5th nets, and step1 to step4 indicate the operations from step 1 to step 4 respectively. The dotted line part indicates the area where the net has crosstalk. After calculation, the amount of crosstalk from n1 to n5 exceeds the threshold. In the wiring trees available for these nets, by calculating the amount of crosstalk change, the crosstalk change in the direction of crosstalk reduction caused by net n1 being redistributed according to the wiring tree shown in Figure 4(b) is the largest . Therefore, in step1, the line network n1 is redistributed, and the crosstalk situation is improved to a certain extent, which is shown by the reduction of the dotted line. In step2, the net n3 is redistributed (as shown in Figure 4(c)). In step3, the net n5 is redistributed (as shown in Figure 4(d)). In step4, the net n2 is redistributed (as shown in Figure 4(d)). Finally, the dotted line part disappears, indicating that the crosstalk is reduced.

The crosstalk situation of the wiring solution in this embodiment before reducing the circuit crosstalk is given below. test example Number of lines Before crosstalk optimization Crosstalk Total Spillover Exceeded the threshold number of nets circuit delay BIU 943 2.49 46 7.43

After crosstalk optimization, the crosstalk situation of the wiring solution in this embodiment is shown in the following table: test example Number of lines Crosstalk optimized Crosstalk Total Spillover Exceeded the threshold number of nets circuit delay BIU 943 0.38 9 7.60

It can be seen from the comparison that after crosstalk optimization, the total crosstalk overflow of the routing solution is significantly reduced, and the number of nets exceeding the crosstalk threshold is also controlled. At the same time, the delay performance of the line network does not change significantly.

(11) Determine whether the delay on each electrical signal transmission path from PI to PO satisfies all the given delay constraint indicators, if: delay optimization result > delay constraint indicator, then continue to perform delay optimization and crosstalk control The program, when all are satisfied, outputs the wiring results of 943 nets in the circuit.

The hardware that the present invention uses is the Enterprise 450 type workstation of a Sun Company; Use Unix operating system.

It can be seen that the technology of eliminating crosstalk and performing time delay and wiring congestion optimization described in the present invention has the following advantages:

(1) The analysis and elimination of crosstalk in the overall wiring process can have a larger optimization space compared with the subsequent stage, and create more favorable conditions for the subsequent detailed wiring work in improving wiring performance;

(2) Taking into account the main factors affecting the crosstalk, the statistics of the crosstalk of the wiring solution are used, and the wiring is removed and redistributed to reduce the crosstalk. At the same time, taking into account the delay performance, the GRG grid passing through the critical path is controlled, so as to reduce the crosstalk and ensure that the delay performance of the circuit will not deteriorate.

Claims (3)

1. The method for reducing crosstalk used in the general wiring process of standard cells is characterized in that it is carried out after optimizing wiring congestion and optimizing time delay in the general wiring process of standard cells. It first performs crosstalk reduction control between signal lines and networks on the basis of statistical circuit crosstalk, and then performs optimization from the input node PI to the output node PO according to the time delay constraint index parameter array given by the user. If it is not satisfied, continue to iterate the delay optimization and crosstalk reduction control procedures including wiring congestion until a set of wiring trees in the general wiring diagram (GRG) of all nets that meet the optimization goal is obtained So far; it reduces the crosstalk between signal nets by controlling the parallel trace length and wiring spacing of adjacent nets according to the following four assumptions after executing the optimized circuit delay program: Assumption 1: In a certain GRG grid i, the length of parallel traces that generate crosstalk between adjacent line segments is the length li of the GRG grid; Assumption 2: In a certain GRG grid i, each line network can only produce crosstalk with the line network located on its left and right (or above and below); Assumption 3: In a certain GRG grid i, the wiring interval of adjacent line segments is the average wiring interval of all line segments in the GRG grid; Hypothesis 4: Since GRG grids are generally divided by integer multiples of unit rows, there will be no crosstalk between line segments in different GRG grids; According to the above assumptions, when performing crosstalk reduction control, with the help of a computer, it contains the following steps in sequence: (1) Setting: N _n is the total number of nets, S _n is the total number of GRG grids that net j passes through, and X _j is the amount of crosstalk that net j defined by the user can tolerate; (2) Calculate the amount of crosstalk Ct _j for each wire net; (3) Calculate the total crosstalk overflow of the current wiring solution S, that is, the sum of the crosstalk overflow of all wire nets

(3.1) Calculating the crosstalk overflow of the line net j That is, the difference between the amount of crosstalk Ct _j it suffers and the amount of crosstalk x _j it can tolerate: $\tilde{C}{t}_j=C{t}_j-x_j;$ (3.2) Calculate the total crosstalk overflow of the current wiring solution S $\tilde{C}t\left(S\right)\underset{j=1}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}\tilde{C}{t}_j=\underset{j=1}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}(C{t}_j-x_j);$ (4) Find out all the wire nets whose crosstalk exceeds the threshold, as the set Vt; (5) Generate a random subset Vs of Vt; (6) For each net in Vs, sort the edges it passes through according to the amount of crosstalk, and find out the edge whose crosstalk amount exceeds the threshold in the first m segments; (7) try to redistribute the m segment edges, and try to make the sum of the crosstalk variation on the m segment edges smaller; (8) Record the current wiring tree, and compare the "cost" with the wiring tree that the line network has constructed To determine the wiring tree with the smallest "cost"; is the variation of the crosstalk overflow of the net j before and after redistribution, that is: $\mathrm{\&Delta;}\tilde{C}{t}_j=\underset{{\mathrm{the\; s}}_i\&Element;T_j^{\&prime;}}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}+\underset{{\mathrm{the\; s}}_i\&Element;T_j}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i};$ in:

is the variation of the crosstalk overflow of the line net j on the GRG grid s _i before and after redistribution;

Is the sum of the crosstalk overflow changes on all GRG grid edges that T' _j passes due to the new layout of the wiring tree T' _j in the line net j;

is the sum of the crosstalk spillover changes on all GRG grid edges that T _j passes due to the undoing of wiring tree T _j in line net j; T _j and T' _j are the wiring trees of net j before and after redistribution, respectively; (9) Calculate the total "cost" of the routing solution for each net in Vs Redistribute the wire net where the wiring tree is located according to the "cost" minimum: total cost Including the change of crosstalk caused by redistribution to the wire net itself and other wire nets, it can be expressed as follows: $\mathrm{\&Delta;}\tilde{C}t=k_1\mathrm{\&Delta;}\tilde{C}{t}_j+k_2\underset{i=1,i\&NotEqual;j}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}\tilde{C}{t}_i$ , $=k_1(\underset{{\mathrm{the\; s}}_i\&Element;T_j^{\&prime;}}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}+\underset{{\mathrm{the\; s}}_i\&Element;T_j}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i})+k_2\underset{i=1,i\&NotEqual;j}{\overset{N_{\mathrm{no}}}{\mathrm{\&Sigma;}}}\underset{{\mathrm{the\; s}}_i\&Element;T_j^{\&prime;}u{T}_j}{\mathrm{\&Sigma;}}\mathrm{\&Delta;}\tilde{C}{t_i}^{{\mathrm{the\; s}}_i}$ $k_1+k_2=1;$ in: Indicates the variation of the crosstalk overflow of all other nets except net j on the GRG grid affected by the redistribution. 2. The method for reducing crosstalk used in the general wiring process of standard cells according to claim 1, characterized in that: for the GRG grid S _i that constitutes the critical path, the described line net j is redistributed before and after The amount of crosstalk spillover on s _i changes in $C{t}_j^{\&prime;{\mathrm{the\; s}}_i}-C{t_j}^{{\mathrm{the\; s}}_i}>0$ hour, $\mathrm{\&Delta;}\tilde{C}{t_j}^{{\mathrm{the\; s}}_i}=\mathrm{\&beta;}(C{t}_j^{\&prime;{\mathrm{the\; s}}_i}-C{t_j}^{{\mathrm{the\; s}}_i}),\mathrm{\&beta;}>1.$ . 3. the method for reducing crosstalk used in the standard unit overall wiring process according to claim 1, is characterized in that: described crosstalk is calculated as follows: $V_{\mathrm{cross\; talk}}=\frac{C_{\mathrm{couponing}}}{C_{\mathrm{total}}},$ Among them: C _coupling is the coupling capacitance; C _total includes ground capacitance, coupling capacitance and load capacitance.

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