CN1457471A - Two architectures for integrated realization of sensing and processing in a single device - Google Patents

Abstract

An integrated sensing device comprising an array of sensor processor cells capable of being arranged into a detection array: Each sensor processor cell comprises a sensing medium; at least one transconductance amplifier configured for feedforward template multiplication; at least one transconductance amplifier configured for feedback template weights; a plurality of local dynamic memory cells; a data bus for data transfer; and a local logic unit. The array of sensor processor cells, by responding to data control signals, is capable of transforming, reshaping, and modulating the original sensed image into varied represenations which include (and extend) traditional spatial and temporal processing transformations.

Description

Integrating two architectures for sensing and processing in a single device

field of invention

The present invention relates to integrated sensing and processing devices. More specifically, the present invention relates to architectures that integrate sensing and processing in a single device.

background

Currently, cellular neural networks (CNNs), based on a set of standard differential equations (Equations 1-3 below) that explicitly express a set of nonlinear dynamic interactions among individual cells in a (usually two-dimensional) an example. Setting There are some degrees of freedom in determining these interactions. In effect, the CNN is programmed by controlling these values. The nonlinearity comes from the nonlinear nature of the function ("f" in Equation 2). Function "f" can have different shapes and properties. Programming a specific function is then used to find the correct combination of A, B, x (t=0), I to produce the desired output (y), giving the input form (u). This type of programming is quite flexible.

A CNN is a hybrid of a cellular robot and a neural network (hence the name cellular neural network), which combines the best features of both worlds. Like neural networks, their time-continuous nature enables real-time signal processing, while their locally interconnected nature, like cellular automatons, enables practical implementation in VLSI. Its grid-like structure is suitable for solving high-order equations of first-order nonlinear differential equations online and in real time. In summary, a CNN can be thought of as an array of simulated nonlinear dynamic processors. The basic unit of a CNN is called a cell. Each cell accepts input from its nearest neighbors (and from itself via feedback) as well as from external sources such as sensor array points and/or previous layers.

The standard CNN equation sums up the following relationship: ${\mathrm{\τ}}_{\mathrm{ij}}{\stackrel{\&Center\; Dot;}{x}}_{\mathrm{ij}}=-x_{\mathrm{ij}}\left(l\right)+\underset{\mathrm{kl}\∈N_r\left(\mathrm{ij}\right)}{\mathrm{\Σ}}{A}_{\mathrm{ij};\mathrm{kl}}({\mathrm{the\; y}}_{\mathrm{kl}}\left(l\right),{\mathrm{the\; y}}_{\mathrm{ij}}\left(l\right))+\underset{\mathrm{kl}\∈N_r\left(\mathrm{ij}\right)}{\mathrm{\Σ}}{B}_{\mathrm{ij};\mathrm{kl}}(u_{\mathrm{kl}}\left(l\right),u_{\mathrm{ij}}\left(l\right))+I_{\mathrm{ij}}$

Formula 1

y _ij = f(x _ij )

Formula 2

and I _ij =I

Formula 3

Among them, u represents the input and x represents the state. Y represents a non-linear function of the state associated with the unit (or neuron), while A and B represent templates for the clone.

In a typical CNN, the local connections between neighbors (feedback weights, input to matrix A in Equation 1), together with the connections forming the sensor array (input weights, input to matrix B in Equation 1), form a programmable Clone template. Cloning templates have been developed to perform various vision processing tasks. Each template has a specific application, such as a cloning template for planar detection or a binocular stereomicroscope. Cellular neural networks are attractive in image processing due to their programmability. One only needs to change the template to perform different image tasks.

Despite this flexibility, serious problems still arise when trying to implement CNNs in circuits. However, the CNN model described by equations (1-3) is not suitable for direct implementation of VLSI. In an integrated circuit implementation of a CNN model, the summation equation is a current-based calculation as assumed by the circuit model in Figure 1. According to Kirchhoff's law, the currents of all nodes entering the state of a certain cell (x) must add up to zero. Since the intrinsic resistance (R) is very large and the capacitance is very small, very little charge is required to maintain a specific voltage. This also means that the current required to change the voltage level of the state is relatively small. The magnitude of the noise current value is large enough to make a noticeable difference. When one considers the fact that transistor characteristics can typically vary by up to 20% on the same chip substrate, it becomes apparent that the (x) node is very likely to be charged up and down the supply rail. One remedy is to add sufficient capacitance to each node. This is undesirable since it requires precious VLSI resources and further increases the response time of the unit. The current VLSI implementation of the CNN model does not address this issue, therefore, the current CNN model described by equations (1-3) is not suitable for direct VLSI implementation.

Summary of the invention

An integrated sensor device comprising an array of sensor processor units that can be arranged in a detection array. Each sensor processor unit includes a sensor medium; at least one transconductance amplifier for feed-forward template multiplication; at least one transconductance amplifier for feedback template weighting; multiple local dynamic memory units; a data bus for data transfer ; and the local logic unit. An array of sensor processor elements is capable of transforming, shaping, and modulating a previously sensed image into representations including (and augmenting) conventional spatial and temporal processing transformations by responding to data control signals.

Brief description of the drawings

The invention is illustrated by way of example in the following drawings, in which like reference numerals are used to designate like elements. The following drawings disclose various embodiments of the present invention, which are for the purpose of illustration only and are not intended to limit the scope of the invention.

Figure 1 (Prior Art) shows a prior implementation that actually implements the construction of the standard equations for cellular neural networks.

FIG. 2 illustrates an implementation of a dynamic cellular computing model for a VLSI layout according to an embodiment of the present invention.

FIG. 3 shows an alternative implementation of using a dynamic cellular computing model for a VLSI layout according to an embodiment of the present invention.

Figure 4 illustrates an alternative implementation of the dynamic cellular computing model for a VLSI layout using analog multipliers, according to one embodiment of the present invention.

Fig. 5 shows an embodiment of the operation process of the dynamic cellular structure according to one embodiment of the present invention in the form of a flow chart.

Figure 6 shows an embodiment of a honeycomb construction element or cell according to one embodiment of the invention.

Figure 7 shows an embodiment of the layout of a CMOS chip containing several cells according to one embodiment of the present invention.

Figure 8 shows an embodiment of an initialized 1-input-1-output unit according to an embodiment of the present invention.

Figure 9 shows an embodiment of a programmable type feedback unit according to an embodiment of the present invention.

FIG. 10 shows an embodiment of a state-initializable unit with positive and negative feedback hard-wired according to an embodiment of the present invention.

Figure 11(a) shows an embodiment of a floating state cell with two (+/-) hardwired feedbacks according to one embodiment of the present invention.

Figure 11(b) shows an embodiment of only one feed-forward unit according to one embodiment of the present invention.

Figure 12 shows an embodiment of digital input devices cascaded via parallel transistors according to an embodiment of the present invention.

Figure 13 shows an embodiment of a feedforward unit according to an embodiment of the present invention.

Figure 14 shows an embodiment resulting from a 3-input 1-output unit without feedback connections according to one embodiment of the invention.

Figure 15 shows an embodiment of a dual distributed cellular configuration according to an embodiment of the present invention.

Figure 16 shows an embodiment of a layout of a signed sensor according to an embodiment of the invention.

Figure 17 illustrates an embodiment of a dual output light sensing pixel according to an embodiment of the present invention.

Figure 18 shows an embodiment of a cell schematic of a programmable convolution array (PCA) according to an embodiment of the present invention.

Figure 19 shows an embodiment of the layout of a single cell of a programmable convolution array (PCA) according to one embodiment of the present invention.

Figure 20 shows an embodiment of the output of a programmable convolution array (PCA) element according to one embodiment of the present invention.

Figure 21 shows an embodiment of a 5x5 programmable convolution array (PCA) with I/O pads according to one embodiment of the invention.

FIG. 22 shows an embodiment of the operation process of a programmable convolution array (PCA) with a dual distribution structure according to an embodiment of the present invention in the form of a flow chart.

Figure 23 shows an embodiment of elements of a programmable cellular logic array (PCLA) according to one embodiment of the invention.

Figure 24 shows in flow chart form an embodiment of the operation process of a programmable cellular logic array (PCLA) in a dual distribution configuration according to one embodiment of the present invention.

FIG. 25 shows in flowchart form an embodiment of the operation of using a Programmable Convolution Array (PCA) in conjunction with a Programmable Cellular Logic Array (PCLA) in dual distribution configuration according to one embodiment of the present invention.

Figure 26 illustrates an embodiment of a computing environment in which the present invention may be implemented, according to one embodiment of the present invention.

Figure 27 illustrates an embodiment of a network environment in which the present invention may be implemented, according to one embodiment of the present invention.

A detailed description

The following detailed description presents numerous specific details in order to provide a thorough understanding of the present invention. However, it will be understood by one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, protocols, components, algorithms, and circuits have not been described in order not to obscure the present invention.

In one embodiment, the various steps or processes of the present invention are embodied in machine-executable instructions, such as computer instructions. These instructions can be used to cause a general or special purpose processor programmed with the instructions to perform the various steps of the present invention. Alternatively, the various steps of the invention may be performed by dedicated hardware components containing hard-wired logic to perform the individual steps, or by any combination of programmed computer components and dedicated hardware components.

The general object of the present invention is a new cellular network architecture that can be successfully implemented using circuits and integrated microelectronic chips, and a new distributed architecture comprising two separate arrays, i.e. programmable volumes Product array PCA and programmable logic array PLA are used to process one-dimensional, two-dimensional, or three-dimensional array (measured) sensor data.

dynamic cellular structure

One embodiment of the present invention introduces a self-normalizing feedback structure for computing inputs and feed-forward templates. Also, the present invention introduces the same structure into the feedback part of the construction. These corrections yield a new set of equations and, in turn, a new set of dynamics, representing a new structure, form, and configuration. Feedback during feed-forward input weight multiplication, and feedback during feedback weight multiplication, are used to keep the state node (x) from accumulating or losing charge rapidly enough to saturate the power rail.

Figure 2 shows an embodiment of the invention implemented in a circuit. Figure 2(a) shows an embodiment of a self-adjusting mechanism, where instead of multiplying the input by B (as in the prior art), each node determines a function of the input minus the state and multiplies this amount by B. Thus , a stable and self-ratioing feedback element around the amplifier does not saturate the output of the amplifier. The gain of the amplifier is controlled so as to obtain a factor which is the quantized (normalized) form of B. In this way, the output is always a normalized form of the input multiplied by "B", and multiple (aggregate) inputs from neighboring cells will not cause the cell to bunch up or the output to saturate or be overdriven by slight fluctuations in the input. Figure 2(b) shows an implementation of a dynamic cellular computing model for a VLSI layout using the concept shown in Figure 2(a). In one embodiment, it is assumed that all input weights (ie, all B-weight inputs) are non-negative, and all feedback weights (all A-weight inputs) are non-positive.

As shown in the embodiment of Figure 2, in the circuit implementation shown in Figure 2(b): (1) u (unsigned) and x (signed) are both represented as analog voltages u and x; (2) template weights can be digitally stored and programmed; and (3) a transfer function f() such as that shown in Eq. Produces 0 output in a local region of the input (rather than just at a point).

The unique equations combining the characteristics of the circuit structure of Fig. 2 are listed below. $C{\stackrel{\&Center\; Dot;}{x}}_{\mathrm{ij}}\left(t\right)=\frac{-x_{\mathrm{ij}}\left(t\right)}{R}+\underset{\mathrm{kl}\&Element;N_r\left(\mathrm{ij}\right)}{\mathrm{\&Sigma;}}{A}_{\mathrm{kl}}{\mathrm{the\; y}}_{\mathrm{kl}}\left(t\right)+\underset{\mathrm{kl}\&Element;N_r\left(\mathrm{ij}\right)}{\mathrm{\&Sigma;}}{B}_{\mathrm{kl}}\tanh \left[\frac{\mathrm{<figure-callout\; id="2"\; label="QUR"\; filenames="A0080711700351.png,A0080711700401.png"\; state="\{\{state\}\}">QUR</figure-callout>}}{2\mathrm{kT}}(u_{\mathrm{kl}}\left(t\right)-x_{\mathrm{ij}}\left(t\right))\right]+I_{\mathrm{ij}}$

Formula 4 $\mathrm{the\; y}=f\left(x\right)=\tanh \left(\frac{\mathrm{<figure-callout\; id="2"\; label="QUR"\; filenames="A0080711700351.png,A0080711700401.png"\; state="\{\{state\}\}">QUR</figure-callout>}}{2\mathrm{kT}}(x-V_{\mathrm{REF}})\right)$

Formula 5

and I _ij =I

Formula 6

where the hyperbolic tangent (tanh) describes a basic transconductance circuit. Furthermore, the differential equation needs to be initialized from the unit initial condition x _ij (0).

We observed that capacitor C and resistor R may be caused by parasitics of the microelectronics implementation process. But in cases where a capacitance larger than the parasitic capacitance is desired to reduce or trim the prototyping process, then a capacitance of about pf can be implemented on-chip. Any larger capacitance could be implemented off-chip, but with the possible attendant cost of limiting the size of the cellular array.

In one embodiment, the input (feedforward) weights (B) are implemented in a negative feedback structure. Thus, in this implementation, the feedback structure stabilizes the state (x) node, which otherwise has a tendency to charge up and down the power rail all the time, and this structure is very resilient to problems such as transistor mismatch. In the embodiment of Fig. 2, a modified dynamic cellular model is shown where the polarity of the inputs and weights have been assumed, eg B is non-negative and A is non-positive.

Figure 3 shows an alternative implementation illustrating the enhancement of the scope of the implementation and also the modification of the contribution of the enhancement state. Therefore, specific equations represent the circuit configurations that can be implemented in an integrated microelectronic chip: $C{\stackrel{\&CenterDot;}{x}}_{\mathrm{ij}}\left(t\right)=\frac{-x_{\mathrm{ij}}\left(t\right)}{R}+A_{\mathrm{ij}}{\mathrm{the\; y}}_{\mathrm{ij}}\left(t\right)+\underset{\mathrm{kl}\&Element;N_{\mathrm{the}}\left(\mathrm{ij}\right)}{\mathrm{\&Sigma;}}{A}_{\mathrm{ij}}{\mathrm{the\; y}}_{\mathrm{kl}}\left(t\right)+\underset{\mathrm{kl}\&Element;N_r\left(\mathrm{ij}\right)}{\mathrm{\&Sigma;}}{B}_{\mathrm{ij}}\tanh \left[\frac{\mathrm{<figure-callout\; id="2"\; label="QUR"\; filenames="A0080711700351.png,A0080711700401.png"\; state="\{\{state\}\}">QUR</figure-callout>}}{2\mathrm{kT}}(u_{\mathrm{kl}}\left(t\right)-x_{\mathrm{ij}}\left(t\right))\right]+I_{\mathrm{ij}}$ Formula 7 ${\mathrm{the\; y}}_{\mathrm{ij}}=f\left(x_{\mathrm{ij}}\right)=\tanh \left(\frac{\mathrm{<figure-callout\; id="2"\; label="QUR"\; filenames="A0080711700351.png,A0080711700401.png"\; state="\{\{state\}\}">QUR</figure-callout>}}{2\mathrm{kT}}(V_{\mathrm{REF}}-x_{\mathrm{ij}})\right)$ Formula 8 ${\mathrm{the\; y}}_{\mathrm{kl}}=f\left(x_{\mathrm{kl}}\right)=\tanh \left(\frac{\mathrm{<figure-callout\; id="2"\; label="QUR"\; filenames="A0080711700351.png,A0080711700401.png"\; state="\{\{state\}\}">QUR</figure-callout>}}{2\mathrm{kT}}(x_{\mathrm{jl}}-x_{\mathrm{ij}})\right)$

and $I_{\mathrm{ij}}=\tanh \left(\frac{\mathrm{qk}}{2\mathrm{kT}}(V_{\mathrm{exl}}-V_{\mathrm{ref}})\right)$ Formula 9

Among them, hyperbolic tangent (tanh) represents a basic (or broadband) transconductance amplifier circuit.

In one embodiment, for the feedback term A, the subscript kl overflows near cell location ij, while the subscript kl overflows near location ij in the feedforward term associated with the B parameter. The input (feed-forward) weights (B) are implemented in a negative state feedback structure as previously described. Thus, in this implementation, the feedback structure stabilizes the state (x) node, which otherwise has a tendency to charge up and down the power rail all the time, and this structure is very resilient to problems such as transistor mismatch. Figure 3 thus shows this modified dynamic cellular model where the polarity of the inputs and weights have been assumed, eg the individual B and A elements are non-negative.

Figure 4 shows another implementation using analog multipliers instead of amplifiers with gain. Thus, as shown in FIG. 4(b), the feedback to the amplifier connected to the embodiment of FIG. 3 (as shown in FIG. 4(a)) can be replaced by an analog multiplier to implement sign weighting. Furthermore, digital gain can also be established by modifying the analog multiplier gain with a digital input device via a parallel transistor cascade as shown in FIG. 9 . By adding a multiplier that can represent the sign, the restriction on the template weight is removed.

Dynamic Cell Construction Process

Fig. 5 shows an embodiment of the operation process of the above-mentioned dynamic cellular structure. In one embodiment, the A, B, x(0), and offset values necessary for all operations to be performed are determined before the process begins. Thus, in one embodiment, the program consists of the individual operations required to accomplish the task, such that each step of the program specifies an operation, where each operation consists of A, B, x(0), and Formal definition of the offset value. In one embodiment, it is possible to derive these values simply from the results of the preceding operations. In one embodiment, the program can be stored externally or on the same chip that implements the configuration. In an alternative embodiment, each unit of the fabric may contain its own program memory.

Referring back to Fig. 5, an embodiment of the operation process of the above-mentioned dynamic cellular structure can be realized through the following process:

1. start

2. If the previous operation is completed or if new data is required, new input is obtained. These inputs (the values of the nodes marked u) can come from data sampled continuously or discretely from sensors built into the configuration, or alternatively, can be scanned from an external data source to the input node (u) using a suitable scanning device middle.

3. Apply A, B, and bias values to the correct nodes, either externally or from internally stored program memory.

4. Apply the initial state (x(t=0)) to the state node.

5. Sufficient time to complete the computation, ie sufficient time for the circuit to reach a change in state value equal to 0 or to have a sufficient response to input stimuli. For active sensors that do not produce a static output, there may be a particular optimal or desired instant at which to sample their output. Another option is for the output itself to be a time-varying waveform.

6. Read and store state (x) or output node (y). The state or output of each node can be stored externally or internally.

7. If the program terminates, go to "end".

8. To (2).

9. End.

The process steps described above thus illustrate one embodiment of the operational process of a dynamic cellular configuration.

Dynamic Cellular Structure - Sampling Realization

Figure 6 shows one embodiment of a practical implementation of a simple 5x5 array dynamic cellular configuration. Figure 6 shows the integrated light sensing and processing architecture implemented in a cellular chip according to the dynamic cellular architecture of the present invention. It will be appreciated that the inventive concepts of the present invention can be used in a wide variety of different technologies and implemented in a wide variety of different practical configurations, and are not meant to limit the invention to integrated light sensing and processing configurations . In one embodiment, the integrated light sensing and processing architecture of a dynamic cellular fabric according to the present invention consists of an array of identical single sensor processor units, each comprising: (1) a photodiode and an active light sensing circuit; 2) Transconductance amplifier for feedforward template weight multiplication; (3) Broadband transconductance amplifier for feedback template weight; (4) Analog/single-bit digital local dynamic memory unit; (5) Data for transmission bus; (6) local programmable logic; and (7) read/write data control.

In an embodiment of the structure depicted in Figure 6, the operations of the cellular paradigm can be performed using a pair of 3x3 clone templates, eg defined by A and B in Equations (4) or (7). In general, each operation can be performed in a short time, simultaneously in each element on the entire image. This means unprecedented processing rate improvements for sequential processors. In one embodiment, operations include linear transformations of the input (convolution operations), detection of positively connected components, and other types of data manipulation allowed by feedback weights. For example, some exemplary operations are planar position, topography operators such as dilation, thinning, and erosion, pre-adaptation, scratch removal, texture, color, and shape analysis. In addition, in one embodiment, using the previously obtained structure to initialize the state, it is also possible to use two template arrays to implement temporal operations such as motion analysis, such as local velocity detection and motion direction detection.

In the embodiment of Figure 6, the entire cellular chip is depicted as a system. In this embodiment, an external (or international cable core) microcontroller generates the command signals required by the integrated sensor processor, such as sensor timing, row selection, and program code. In an alternative embodiment, a processor or digital signal processor may be used in place of the microcontroller, depending on the computing needs of the particular application at hand. Also, in one embodiment, the program memory may be internal, where the denser address levels are encoded into bit-level microinstructions and determine the boilerplate values and data transfers in the structure.

In the embodiment of Figure 6, the contents of the cells are described in more detail. For example, feedforward and feedback weights that also integrate the transfer function are shown in diagram form. Furthermore, local logic and memory functions are also shown in a similar manner. In one embodiment, there is a main data bus over which data transfers can occur. It is then possible to form a 2-way connection between the data bus and the 2 analog and 4 digital memory cells, the state (x) and the input (u). Connections can also be made from logic outputs and reference voltages to the data bus. Furthermore, logic can be implemented by means of programming similar to a programmable logic array. Likewise, the advent of reconfigurable logic arrays represents another option or implementation.

As stated above, it is to be understood that the inventive concept of the present invention may be applied to a variety of different technologies and implemented in a variety of different practical configurations, and that the present invention is not meant to be limited to the integration of pre-sensing and Handle construction. For example, the same configuration can be applied to applications such as acoustic or sound-based systems where there are multiple sensors arranged in a one-dimensional, two-dimensional, or three-dimensional grid. Each sensor on the grid can then respond to the same physical quantity (such as the frequency of the audible sound spectrum). Thus, individual sensors may sense different properties of the same signal (eg, each sensor tuned to a different frequency of the audible sound spectrum). This measures the frequency pattern of the sound incident on the array. Furthermore, it is also conceivable to mix the two, for example to measure color graphics.

Realization of several honeycomb model circuits

Figure 7 shows an embodiment of the layout of a CMOS chip according to the inventive concept, which contains several cellular cells (eg VLSI using the cellular dynamic construction cell prototype). In one embodiment, the CMOS chip design can be done in MOSIS 2 micron ORBITANALOG process. Also, in one embodiment, the die size is achieved by bonding to a 40-pin DIP "TINYCHIP" package with an area of 2.3 mm x 2.3 mm.

As described in the embodiment of Figure 7, in one embodiment of the CMOS chip, the CMOS chip includes 11 types of units: 4 initialized 1 feedforward-1 feedback units; 2 programmable type (positive or negative) feedback units; 2 hardwired feedback and state initializeable cells; 2 (+/-) hardwired feedback and floating state cells; and 1 feedforward-only cell. In one embodiment, all useful outputs are available through broadband output amplifiers at the outputs, and all programmable cell parameters, ie, feedforward and feedback weights, and bias voltages are at 3-bit resolution (positive sign bits). External inputs are available through pins to set these weights.

Figures 8-11 each schematically illustrate these units. Figure 8 shows a schematic implementation consisting of 4 units in a compact manner: 4 initialized 1 feedforward-1 feedback units. On the top of the chip in Figure 7, there are four 1-input-1-output units. There are four types of simple 1-input-1-output simple units of this type. Four types emerge due to four methods capable of realizing positive feedback and negative feedback permutation. 4 combinations of +/- terminals are possible and all of them can be realized. Furthermore, all 4 units include state initialization means to define x at an initial instant (t=0). This means that states can be initialized at any voltage that a particular microelectronic device is capable of carrying. This is equivalent to defining the initialization point x| _t=0 in equations (4) and (7). In this particular setup, both the feedforward and feedback amplifiers have 3-bit programmable gains.

Figure 9 shows a schematic implementation of two programmable types (positive or negative) feedback units. Two 3-input 1-output selectable types (+ or -) of the feedback unit can be realized. One of them can also initialize the state in exactly the same way as described in FIG. 8 . Figure 9 shows such a unit uninitialized. In one cell implementation, as shown, there is an added delay of the window transistor in the state feedback. Depending on the feedback sign selection bit, two signals (state node x and Vref) are routed to the terminals of the feedback weight amplifier. In one implementation, all amplifiers have 3-bit programmable gains.

Figure 10 shows a schematic implementation of two hard-wired feedback and state-initializable units. Consists of 2 initialized 3-input 1-output units as described in Figure 10. These units differ only slightly from the units described in FIG. 9 . In one embodiment, the feedback type is implemented directly rather than being programmable. Two combinations of +/- terminals are possible and both have been implemented. In one implementation, both amplifiers have 3-bit programmable gains.

Figure 11(a) shows a schematic implementation of two (+/-) hardwired feedback and floating state cells. In one embodiment, these cells are identical to those described in Figure 10, but do not include state initialization circuitry. The initial value of the state is then undefined.

Figure 11(b) shows a schematic implementation of a feed-forward only unit. This is a 3-input, 1-output unit with programmable bias. In one embodiment, the feedback feature is eliminated. This unit then deviates from the cellular neural network paradigm and can only be used for feed-forward operations.

Figure 13 shows an embodiment of a feedforward unit. In one embodiment, the input u is always non-negative but has a signed representation, while u+ is chosen for positive inputs and u- is chosen for negative inputs of the B template.

Feedforward Weights and Image Convolution: A Sampling Operation

Convolution is a very common image processing step for many imaging tasks. It is often used as a technique to generate a secondary (different) image from an original in which desired features are enhanced and/or undesired features (eg noise) suppressed. In one embodiment, convolution may be described as a continuous spatial operation or a temporal operation, but its application to the sampled image is discrete and involves a convolution influence function with discrete values.

This discrete convolution operation denoted by  between image I and influence function k can be described as: $I\&CircleTimes;k{|}_{x.\mathrm{the\; y}}=\underset{i=-N}{\overset{N}{\mathrm{\&Sigma;}}}\underset{j=-N}{\overset{N}{\mathrm{\&Sigma;}}}{I}_{x+i.\mathrm{the\; y}+j}{k}_{i.j}$

Formula 10

Among them, I is the input image, x and y are the coordinates of the second image, and k is the (2N+1×2N+1) square influence function.

It can be easily seen that the sum of feedforward weight input products in equation (1) $\underset{\mathrm{kl}\&Element;N_r\left(\mathrm{ij}\right)}{\mathrm{\&Sigma;}}{B}_{\mathrm{kl}}(u_{\mathrm{kl}}\left(t\right),u_{\mathrm{ij}}\left(t\right),)$ Similarity with the sum in equation (10).

Then, if I=0 and A=0 are set, the steady-state solution of equation (1) is $x_{\mathrm{ij}}\left(t\right)=\underset{\mathrm{kl}\&Element;N_r\left(\mathrm{ij}\right)}{\mathrm{\&Sigma;}}{B}_{\mathrm{ij};\mathrm{kl}(u_{\mathrm{kl}}\left(t\right),u_{\mathrm{ij}}\left(t\right))}$

This is actually equivalent to Ik|x,y _i,j , where the second term is the normalized influence function.

The model adopted by the VLSI performs a normalization operation, which uses the equation (4) $\underset{\mathrm{kl}\&Element;N_r\left(\mathrm{ij}\right)}{\mathrm{\&Sigma;}}{B}_{\mathrm{kl}}\tanh \left[\frac{\mathrm{<figure-callout\; id="2"\; label="QUR"\; filenames="A0080711700351.png,A0080711700401.png"\; state="\{\{state\}\}">QUR</figure-callout>}}{2\mathrm{kT}}(u_{\mathrm{kl}}\left(t\right)-x_{\mathrm{ij}}\left(t\right))\right]$

Instead of the standard model's feed-forward weights multiplied by the sum of the input values in equation (1) $\underset{\mathrm{kl}\&Element;N_r\left(\mathrm{ij}\right)}{\mathrm{\&Sigma;}}{B}_{\mathrm{kl}}\left(u_{\mathrm{kl}}\left(t\right)\right)$

The normalized convolution denoted by  _n is very similar to the regular convolution operation, except that the output is normalized by the sum of the influence function inputs. Since the influence function is the same over the entire image, the result is essentially divided by a normalization factor common to the entire image. The advantage is that the resulting image has essentially the same dynamic range as the input image. $I{\&CircleTimes;}_{\mathrm{no}}k{|}_{x,\mathrm{the\; y}}=\frac{\underset{i=-N}{\overset{N}{\mathrm{\&Sigma;}}}\underset{j=-N}{\overset{N}{\mathrm{\&Sigma;}}}{I}_{x+i,\mathrm{the\; y}+j}{k}_{i,j}}{\underset{i=-N}{\overset{N}{\mathrm{\&Sigma;}}}\underset{j=-N}{\overset{N}{\mathrm{\&Sigma;}}}{k}_{i,j}}$

Formula 11

To implement the normalized convolution described above, the input voltage value is loaded with the input voltage corresponding to the image and the gain from the influence function input. Since the conductance (or gain value) must be positive, to achieve negativity with this method, one needs to be able to define a negative input voltage and select the negative polarity of the input to the transconductance amplifier for which negativity is desired. Although the input range of the influence function is still unaffected, this cuts off half of the dynamic range of the image. If the bias amplifier is ignored, the cell arrangement in Figure 11(b) can be seen accordingly.

Sampling operation

For example, in a sampling operation, the 4-bit plus-sign representation shown in Figure 12 (via a parallel transistor cascaded digital input device) can be used as the input to the B template in equations (1) and (4), scaled by 0.25 The increments take values in the range -3.75 to 3.75. In one embodiment, this unit is equivalent to the feed-forward configuration shown in Figure 11(a), provided that the gain of the amplifier is fed by the B-plate. With more area and more bits, higher resolution and dynamic range are possible.

In the sampling operation, other parameters can be as follows:

0>u<1

u+＝Vref+u

u-=Vref-u

-3.75<b<3.75

umin<x<umax

In this configuration, Vref may be a representation of zero. An assumed value for Vref is the midpoint between the ground and power supply of the microelectronic device.

The implementation of the sign is based on the choice of u+ or u-. Note that this also creates the opportunity to implement negative u. In other words, it is also possible to accommodate values of u<0 in this configuration. In this case, the parameters can be as follows:

-1<u<1

u+＝Vref+u

u-=Vref-u

A concrete realization of the range -3.75 to 3.75 for different values of template B in the construction yields the following results:

b = b sign(v) b ³ (MSB) b ² b ¹ b ⁰ (LSB)

-3.75 0V 1V 1V 1V 1V

-2.00 0V 1V 0V 0V 0V

-1.00 0V 0V 1V 0V 0V

-0.50 0V 0V 0V 1V 0V

-0.25 0V 0V 0V 0V 1V

0.25 5V 0V 0V 0V 1V

0.50 5V 0V 0V 1V 0V

1.00 5V 0V 1V 0V 0V

2.00 5V 1V 0V 0V 0V

3.75 5V 1V 1V 1V 1V

Where power is 5V and logic 1 is 5V. 1V can be chosen as the bias voltage in order to make the bias transistor work near the threshold. In one embodiment, the state node (x) is referenced to Vref and does not require a signed representation. The positive input value of the feedback template "A" can be used to direct x to the + terminal of the wideband differential amplifier, while the negative input directs it to the - terminal. In the 4-digit positive sign representation, the value of A can also take values in the range -3.75 to 3.75 in increments of 0.25. With more area and more bits, higher resolution and dynamic range are possible. Other parameters are as follows: -3.75<aij<3.75 and 0<x<Vdd.

In this way, the feedback configuration of the feedforward weights provides some safety against the tendency of the active current computation unit to be attracted to the power supply line.

Two actual images are captured by a CCD camera, and three inputs are provided to the chip at the same time. The three input weights are set to represent the one-dimensional vertical plane influence function composed of 1, 0, and -1. In this sampling operation, individual pixels are provided in this manner. In the sampling operation, along the horizontal direction to the model circuit shown in FIG. 11(b), the bias amplifier is turned off, and the entire image is provided with 3 pixels at the same time. The result is shown in FIG. 14.

double distribution structure

As shown in Figure 15, one embodiment of the present invention incorporates a dual distribution configuration of a 5x5 array. In one embodiment, the dual distribution architecture consists of two distinct structures: (i) the Programmable Convolution Array PCA, a sensing grid with convolution capabilities, which may also include some short-term memory, and (ii ) PLA, a programmable logic array and memory areas on which transformations or different representations of sensed data can be generated. In one embodiment, the two regions compute in parallel and communicate with each other in serial random access as needed. Likewise, the Programmable Cellular Logic Array (PCLA) primarily communicates with an external area, which may include a conventional digital signal processor, microprocessor, or microcontroller.

Taking into account the effect of the speed of the device medium (most commonly silicon microelectronics) on the requirements of large-area cellular processors, consider again the elements of the unit of the specific device enumerated in the dynamic cellular structure above, namely: (1) optoelectronics Diode and active light sensing circuit; (2) transconductance amplifier for feed-forward template weight multiplication; (3) broadband transconductance amplifier for feedback template weight; (4) analog/single-bit digital local dynamic memory unit; (5) data bus for transfer; (6) local programmable logic; and (7) read/write data control.

Practical concerns and implementations of integrated cellular sensor-processor systems typically refer to the following considerations: (1) the sensor can be fabricated and embedded in the processing system; (2) the resolution of the sensing portion of the system is close to that available in the market; ( 3) Fill factor (ratio of sensor area to total area of each cell) is reasonable for the application; (4) Maintain sensor performance as process size decreases; (5) A set of operators that fetch data from large neighbors value. These are merely considerations when implementing an integrated cellular sensor-processor system, but need not be specifically followed, and thus, the above-mentioned factors are not intended to limit the scope of the present invention.

Even so, adopting a systematic approach to meet the above objectives should generally point out the following factors: (1) In order to improve the resolution, the unit must be reduced; (2) In order to improve the fill factor, the photosensitive area must be increased; (3) In order to maintain the sensor work, the sensor (or the entire chip) may need to be built with a larger scale process, which in turn means the cells must be made smaller; and (4) to increase the neighbor size, larger connections may have to be made unit. These again are only considerations when implementing an integrated cellular sensor-processor system, but need not be specifically followed, and thus, the aforementioned factors are not intended to limit the scope of the invention.

In this way, it is also possible to realize (in feed-forward connections) arbitrarily sized neighbors, or influence functions as they are commonly called in image processing, which include influence functions as large as the entire sensor array itself, but at the same time have only one Such an influence function. This allows the speed of the device medium to affect the area requirements of the processor.

The dual distribution configuration generally offers 3 distinct advantages over currently implemented existing configurations.

First, the computational concept of construction is simpler and much more convenient than the prior art cellular neural network concept employing nonlinear circuit dynamics. Also, much less training of implementing engineers is required to implement this configuration. The method of programming operations in the dual distribution configuration is much more straightforward than the method required to determine or find the correct parameters A, B, x(0) and I than currently implemented existing configurations.

Second, since the effects of nonlinear dynamics are minimized, circuit anomalies such as mismatches or noise inherent to the substrate on which the construct is built have much less impact on the computational output. This makes the manufacture of the device much easier and more cost effective.

Third, the dual distribution construct, as its name implies, consists of two parts, each of which has a separate function. In other words, each part functions independently and can be realized independently. The first part of the dual distribution configuration is the Programmable Convolution Array PCA, which in one embodiment contains a sensing grid with convolution capabilities and can also include some short-term memory. The programmable convolutional array PCA section performs arbitrary linear transformations of the entire sensed data or parts of the sensed data. The desired weights of individual elements can be programmed directly. The second part of the dual distribution fabric is the Programmable Cellular Logic Array (PCLA). In one embodiment, the PCLA is cellular, meaning that each element of the array is connected to its set of neighbors. But PALA is not a neural network, and in one embodiment relies on conventional logic to perform its operations. In one embodiment, the actual logic can be implemented with conventional digital logic such as, but not limited to, AND, OR, XOR, or non-conventional analog logic gates. Furthermore, in one embodiment, there can be state machines (ie, minicomputers) at the various elements. For independently applicable operation, individual elements of the PALA can be equipped with sensors, or can scan in data from external sources.

Signed output sensor (SOS)

As with certain types of implementations of convolution functions, such as those using non-negative gain amplifier circuits, it may be that each sensor must produce a dual output.

Therefore, depending on the nature of the sensor, the method of producing this dual output may differ. For sensors that measure non-negative values with reference to 0 (eg, light), (+) and (-) pixel outputs may be required. Positive (+) outputs are used to feed amplifiers if they contain positive influence function values. Accordingly, negative (-) pixel outputs can be used to negatively influence function values. A one-dimensional example is given below.

Assume that it is necessary to implement a one-dimensional planar influence function composed of [10-1] on a photosensitive grid. The equivalent arithmetic operation is to sum pixels[i-1]+(-pixels[i+1]). Since current summation can be used, it is necessary to add the positive representation of current for pixel [i-1] to the negative representation of current for pixel [i+1].

Figure 16 shows an embodiment of an exemplary layout of such a single-sign output active sensor. In the embodiment of Figure 16, the active area is a 100λ x 100λ square, and the entire cell covers an area of 195λ x 130λ. The (grounded) METAL2 layer covering areas of the cell that should not be exposed to light is not shown.

Likewise, Figure 17 shows a corresponding schematic diagram of a signed sensor, where the representation of the plus and minus pixels is noted. In one embodiment, since the photocurrent is very small and the sensing node should not be disturbed, an additional follower is used.

Programmable Convolution Array (PCA)

Figure 18 shows an embodiment of the elemental design of a light-sensing PCA. In one embodiment, individual pixel cells are addressable by a combination of row and column select signals. Likewise, weight bits can thus be written to selected pixels. The pixel midpoint defines the "0" value represented by the signed pixel value, ie no light. Resetting the pixel will bring the pixel output to this value. In one embodiment, there is no need to route a dedicated ground signal since the metal layer covering the circuit (with the window in the photosensitive area) can be grounded. In the embodiment of Fig. 18, each unit comprises: (1) a signed output sensor (SOS); (2) 4 D flip-flops for storing 3-bit weight and sign; (3) 4 multipliers; (4) wideband transconductance amplifiers connected in a unitary output configuration; and (5) 3-input AND gates.

In one embodiment, the cell size can be significantly reduced due to some empty space as shown in the layout of a single cell in FIG. 19 . Smaller feature sizes and added metal layers will undoubtedly make the unit more compact. Significant savings in area may come from dynamic memory cells, since individual influence functions may be applied short-term. Several data and control signals are usually directed to each unit.

In one embodiment, control signals common to all units include: (1) clock weight, (2) reset photodiode (or sensor), and (3) sign. The addressing signals are row and column. In one embodiment, data signals common to all units include: (1) Pixel Reference, (2) Inverter Reference, (3) Weight High, (4) Weight Low, (5) Weight MSB, (6) ) weight MID, (7) weight LSB. Also, in one embodiment, as shown in FIG. 20, the elements of each row have a common row select signal, and the elements of each column have a common column select signal. Thus, the outputs of the individual cells can be summed on a common line. Alternatively, the output may be combined along columns, rows, or blocks, or along other conventions.

Figure 21 shows an exemplary PCA layout of 5x5 pixels. In the embodiment of FIG. 21, each of the 25 elements uses 4 weight bits (3 magnitude, 1 sign) stored in a D flip-flop. Therefore, the weight bits are clocked in only when both row and column are selected, and when the weight clock bit is activated. The weight output triggers the selection between weight high and weight low. In one implementation, the broadband transconductance amplifier in the output stage has 3 bias transistors with W/L ratios of 1/4, 1/2, 1, each corresponding to an amplitude bit. If all weights are 0, the pixel does not contribute any current to the output. If either weight is non-zero, the pixel contributes positive or negative current to the total readout, depending on the sign. The high weight of the data signal also determines the gain of the light sensor. In one embodiment, dynamic memory may be used in place of D flip-flops in order to save silicon area. In one embodiment, the design may be implemented in a 2 micron CMOS process design with pads configured to fit in a 2.3mm x 2.3mm area and embedded within a 40-pin DIP chip package. In this example implementation, all 25 pixel outputs are summed on a common output line. Different signs and weights of individual units can be chosen to perform arbitrary convolution operations. In this particular implementation, any 4-bit influence function up to 5x5 can be programmed.

PCA process

Figure 22 shows one embodiment of the operation of the programmable convolution array (PCA) described above. In one embodiment, the necessary weight forms to be applied to the array are determined for all operations to be performed before the process begins. Thus, in one embodiment, the program consists of the operations required to accomplish the task, such that each step of the program specifies an operation, where each operation is defined by the form of weights to be applied to the array. In one embodiment, it is possible to derive the weight form simply from the result of the preceding operation. In one embodiment, the program can be stored externally or on the same chip that implements the array. In an alternative implementation, each element of the array has its own program memory.

Referring back to FIG. 22, the implementation of the operation process of the above-mentioned programmable convolution array (PCA) can be realized through the following process:

1. start

2. If the previous operation is completed or if new data is required, new input is obtained. These inputs may come from continuously or discretely sampled data from sensors built into the array, or alternatively may be scanned into input nodes from external data sources using suitable scanning means.

3. Apply the weighted form of the instruction either externally or from internal program memory.

4. Make the time sufficient to complete the calculation, ie the time sufficient for the circuit to reach a state where the change in the output value of the array is equal to zero. For active sensors that do not produce a static output, there may be a particular optimal instant at which to sample their output. Another option is for the output itself to be a time-varying waveform.

5. Read and store the output of the array. This output can be stored externally or internally. If PCA is used in cascade with PCLA, the output can also be fed to PCLA.

6. Wait for the next operation

7. If the program terminates, go to the end.

8. To (2).

9. End.

Programmable Cellular Logic Array (PCA)

The output of the convolution operation performed by PCA is usually an analog current or voltage value. While such fast arbitrary-sized influence function convolution operations are extremely useful, there are many lookahead operations that require further processing of the results of many convolution operations. Programmable cellular logic arrays (PCLAs) are one way to achieve this stage.

In one embodiment, a PCLA is a processing device for processing binary or digital data using an array of fixed or programmable logic elements arranged on a cellular grid. Therefore, if PCLA is used with PCA, the dimensions of the two arrays can be the same or different. In one embodiment, the PCLA grid can be used as a "cache" for a set of image operations such as shape detection, contour following, form matching, all using the output of the PCA or externally, Execute at a resolution that may differ from the data received.

Also, individual PCLA elements can be accessed as a memory array to which an input (such as the output of a PCA) can be applied or stored, and from which a result can be retrieved. Added functionality may come from the ability to transfer bits between neighbors (similar to a shift operation) or to an arbitrary location on the cellular logical grid (random access transfer).

The embodiment of Figure 23 shows a simple arrangement of programmable cellular logic array (PCLA) elements. In the embodiment shown in Figure 23, only the central cell connections are shown to prevent clutter, while, in the embodiment shown, the cell outputs have been staged to prevent race conditions. In this embodiment, all operations are strictly local operations. This is not a limitation of the invention. In one embodiment, global operations such as match with global form, reset, set can also be implemented in PCLA. Moreover, increased functionality can be achieved in the following ways: (1) Increased connectivity, where each element receives more inputs, such as from additional elements in the immediate vicinity, or from any element of the array via memory-like access ; and (2) increase cell memory, where the result of the previous operation can be stored in the cell. In one embodiment, the logic in the cell should be programmable. In fact, the program can be changed many times during operation. The sampling logic function may be an AND, OR, INVERT, XOR, etc. of a set of available inputs.

In one embodiment, PCLAs may benefit from the emerging use of reconfigurable field programmable gate arrays (FGPAs). But this is a relatively new field, and researchers are trying to think of ways to exploit the inherent flexibility of these devices so that better computing paradigms can be easily built.

A specific concept of this, called plastic cell construction, has led to a new type of circuit laid out as an array of identical computational elements, or cells, that can dynamically reconfigure themselves for specific problems. This new computing paradigm offers novel features beyond the common concept of reconfigurable FPGAs, in which circuits have hitherto been able to be reconfigured simply by software downloaded to one or more FPGAs, and the chip then directly executes the prescribed hardwired circuit functions . This addition features the ability for one circuit to dynamically compose another. The resulting processing array can mimic the ability to generate dedicated cells, which in turn enables cellular arrays like PCLAs to self-configure based on the output of their neighbors or themselves. This level of data-driven performance enables very complex functionality from very simple rules.

PCLA process

Figure 24 shows one embodiment of the operation process of the Programmable Cellular Logic Array (PCLA) described above. In one embodiment, the necessary local and global logic functions are determined before the process begins. These logic functions should already be implemented in the individual elements of the array to be performed, or it should be possible to program the logic contained in the individual elements of the array to perform the desired logic functions. Typically, operations are defined in terms of operations performed by individual elements of the array.

Thus, a program consists of the sequence of operations required to accomplish a task, such that each step of the program specifies one or more functions to be performed by each element of the array. In one embodiment, all elements may perform the same function or different functions at any given time. Likewise, in one embodiment, it is also possible to derive the next operation from one or more previous operations. In one embodiment, the program can be stored externally or on the same chip that implements the array. In an alternative embodiment, the program memory may be local, that is, each element of the array may have its own program memory.

Referring back to FIG. 24 , the embodiment of the operation process of the above-mentioned programmable cellular logic array (PCLA) can be realized through the following process:

1. start

2. If the previous operation is completed or if new data is required, new input is obtained. These inputs may come from continuously or discretely sampled data from sensors built into the array, or may be scanned into the input nodes from external data sources including but not limited to PCA using suitable scanning means.

3. To perform a prescribed operation, the opcode for the prescribed operation may be applied from an external source or from internally stored program memory.

4. Make the time sufficient to complete the calculation, ie the time sufficient for the circuit to reach a state where the change in the output value of the array is equal to zero. The output of active sensors should first be digitized.

5. Read and store the output of the array. This output can be stored externally or internally. If PCLA is used in cascade with PCA, the output can also be fed to PCA.

6. Wait for the next operation.

7. If the program terminates, go to the end.

8. To (2).

9. End.

Communication between PCA and PCLA

Obviously, in addition to power and ground signals, many other data, control, and address signals typically need to be distributed on the chip. As is the case with many photosensor chips, the PCA portion of the chip should be covered with a metal layer with windows only at the photosensitive areas in order to expose the package to light. It is usually possible to ground the metal layer covering the entire chip. Similar layers can also be used on the PCLA portion of the double construct to route the output of the PCA to all points of the logic array.

The PCA's row select and column select signals are reminiscent of a memory addressing diagram. A particular pixel is selected only when both signals are logic high. These signals can be used to load weights to cells.

Elements of PCLA can also be addressed like memory cells. A cell line can be thought of as a long word. A set of write and shift operations can replace the need to send multiple address signals across the PCLA.

PCA and PCLA cascade process

Figure 25 shows one embodiment of a process using a cascaded programmable convolutional array (PCA) and programmable cellular logic array (PCLA). In one embodiment, the necessary form of weights to be applied to the PCA for all operations to be performed is determined before the process begins. Also, determine the necessary local and global logic functions required by the PCLA. In one embodiment, the operations are defined by the weighted form of the PGA and performed by the individual elements of the PCLA in the logical functional form.

Thus, in one embodiment, a program consists of the sequence of individual operations required to accomplish a task, such that each step of the program specifies one or more operations to be performed by PCA or PCLA, or both. In one embodiment, the program can be stored externally, or on the same chip or multi-chip module implementing the two arrays. In an alternative embodiment, the program memory may be central or local, ie each element of the array may have its own program memory.

Referring back to FIG. 25, an embodiment of an operating process employing a cascaded Programmable Convolution Array (PCA) and Programmable Cellular Logic Array (PCLA) may be achieved by the following process:

1. start

2. If the previous operation is completed or if new data is required, new input is obtained. These inputs may come from data sampled continuously or discretely from sensors built into one or more arrays, or may be scanned using suitable scanning devices from external sources including, but not limited to, from one array to another. input node.

3. Carry out the prescribed operation. Opcodes specifying operations can be applied from an external source or from internal program memory.

4. Sufficient time to complete the computation, ie sufficient time for the circuit to reach a state where the change in the output value of the array is equal to 0 or some other criterion by which the operation is considered complete.

5. Read and store the output of the array. This output can be stored externally or internally. This output can also be fed from one array to another.

6. Wait for the next operation.

7. If the program terminates, go to the end.

8. To (2).

9. End.

Application Example: Single Chip Fingerprint Lock Control

The concept of the present invention can be applied to fingerprint identification systems. Current fingerprint systems require sensors, memory, processors, and software loading, which again limits their practical use. But there are countless applications for a single chip that can accomplish the same task without an external processor, memory, or program. For example, door locks with fingerprint keys, drawer locks or power button locks are examples. The lock is maintained until an "authorized" fingerprint is pressed against the lock.

In this embodiment, since the fingerprint image is binary, it is practical to equip the PCLA with a binary sensor and use it independently. The logic used to control the image and determine if it is the correct fingerprint can be built directly into the device. Alternatively, a separate PCA can be built if only a linear transformation of the fingerprint image is sufficient. A program can be a combination of weights and can be stored on the device. Alternatively, using both PCLA and PCA can enhance features, improve resolution, ie provide better security.

computer environment

Figure 26 and the foregoing description are intended to provide a general description of a suitable computing environment in which the invention may be implemented. Although not required, an embodiment of the invention can be implemented as a generally organized set of computer-executable instructions, such as program modules, executed by a computer such as a commissioned workstation or server. Generally, program modules include channels, programs, objects, components, data structures, and the like that perform particular tasks or implement particular abstracted data types.

Moreover, those skilled in the art will understand that, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, communication devices, network personal computers, minicomputers, mainframe computers, etc. other computer system configurations to implement the present invention. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

As shown in FIG. 26 , an exemplary general purpose computing system may include, for example, a conventional personal computer 20 that includes a processor 21, a system memory 22, and a system coupling various system elements including the system memory 22 to the processor 21. system bus 23 . System bus 23 can be of any of several bus architectures, including a memory bus or memory controller, a peripheral bus, and a local bus. System memory 22 may include read only memory (ROM) 24 and random access memory (RAM) 25 . A basic input/output system 26 (BIOS), including the basic channels that assist in the transfer of information between various components in the personal computer 20, such as during start-up, may be stored in ROM 24. The personal computer 20 may also include a hard disk drive 27 for reading from or writing to a hard disk (not shown), a magnetic disk drive 28 for reading from or writing to a removable magnetic disk 29, and An optical disc drive 30 to read from or write to a removable optical disc 31 such as a CD-ROM or other optical media. Hard disk drive 27, magnetic disk drive 28, and optical disk drive 30 may be connected to system bus 23 by hard disk drive interface 32, magnetic disk drive interface 33, and optical drive interface 34, respectively. The drives and their associated computer-readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules, and other data for the personal computer 20 .

Although the exemplary embodiments described herein may use hard disks, removable magnetic disks 29, and removable optical disks 31, or combinations thereof, those skilled in the art will appreciate that capable Other types of computer-readable media that store computer-accessible data, such as magnetic cards, flash memory cards, digital video disks, Bernoulli tapes, random access memory (RAM), read only memory (ROM), and the like.

A large number of program modules, including operating system 35, one or more application programs 36, other program modules 37, and program data 38, may be stored on a hard disk, magnetic disk 29, optical disk 31, ROM 24, or RAM 25. A user may enter commands and information into the personal computer 20 through input devices such as a keyboard 40 and pointing device 42 . Other input devices (not shown) may include one or more microphones, joysticks, game pads, accessory disks, scanners, and the like. These and other input devices are usually connected to the processor 21 through a serial interface 46 coupled to the system bus 23, but other interfaces such as a parallel interface, a game interface, or a universal serial bus (USB) may be used for connect. A monitor 47 or other type of display may also be connected to system bus 23 through an interface such as video adapter 48 . In addition to the monitor 47, a personal computer may typically include other peripheral output devices (not shown), such as speakers and a printer.

The personal computer 20 may operate in a network environment using logical connections to one or more remote computers such as 49 . Although only memory storage device 50 is shown in FIG. 26, remote computer 49 may be another personal computer, server, channelizer, network PC, peer device, or other public network node, and typically includes many or all Regarding the above-mentioned elements of the personal computer 20 . The logical connections shown in FIG. 26 include a local area network (LAN) 51 and a broadband network (WAN) 52 . Such networking environments are commonplace in offices, enterprise computer networks, the Internet, and intranets.

When used in a LAN network environment, the personal computer 20 is connected to the LAN 51 through a network interface or adapter 53. When used in a WAN network environment, the personal computer 20 typically includes a modem 54 or other device for establishing communications over a broadband network 52 such as the Internet. Modem 54 , which may be internal or external, is connected to system bus 23 through serial interface 46 . In a network environment, program modules depicted relative to the personal computer 20, or portions thereof, may be stored in the remote memory storage device. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between the computers may be used.

It is also to be understood that different elements or components may be included or excluded from the general computing environment, or combined, to implement the inventive concept as defined by the appended claims.

Web environment

As noted, the above-described general-purpose computers can be employed as part of a computer network. In general, the above description applies to both server and client computers used in network environments. Figure 27 illustrates one such exemplary network environment in which the present invention may be used. As shown in FIG. 27, a large number of servers 10a, 10b, etc. are interconnected to a large number of client computers 20a, 20b, 20c, etc., via a communication network 160 (which may be a LAN, WAN, the Internet, or an intranet). In a network environment where communication network 160 is, for example, the Internet, server 10 may be a Web server by which client computer 20 communicates via a number of known protocols, such as Hypertext Transfer Protocol (HTTP). Each client computer 20 may be equipped with a browser 180 and a client application software 185 for accessing the server 10 . As shown in the embodiment of FIG. 27 , the server 10a includes or is coupled to a dynamic database 12 .

As shown, database 12 may include a database field 12a containing information stored in database 12 about an item. For example, database field 12a can be structured in a database in a variety of ways. The field 12a may be constituted by a link list, a multidimensional data array, a hash table, or the like. This is usually a design choice based on ease of implementation, amount of free memory, nature of the data to be stored, whether the database will be written frequently or mostly read, etc. A common field 12a is shown on the left. As shown, a field typically has subfields containing various information about the field, such as an ID or title subfield, an item type subfield, a subfield containing attributes, and so on. These database fields 12a are shown for illustrative purposes only, and as stated, the specific implementation of data storage in the database can vary widely according to preference.

Thus, the present invention can be implemented in a computer network environment having a client computer for accessing and interacting with the network and a server computer for interacting with the client computer and communicating with a database storing storage fields. Likewise, the invention can be implemented in a wide variety of network-based architectures and thus should not be limited to the illustrated embodiments.

From the foregoing description and accompanying drawings, those of ordinary skill in the art will appreciate that the particular embodiments shown are for illustration purposes only and are not intended to limit the scope of the invention. Those skilled in the art can understand that the present invention can be embodied in other specific forms without departing from the concept or main characteristics thereof. References made to details of specific embodiments are not intended to limit the scope of the claims.

Claims (3)

1. integrated sensor spare, it comprises:

By the array that the sensing processor unit that can be arranged in detection array is formed, each sensing processor unit comprises:

The sensing medium;

The trsanscondutance amplifier of at least one model multiplication that is configured to feedover;

At least one is configured to feed back the trsanscondutance amplifier of model weight;

A plurality of local dynamic storage units;

Be used for the data bus that data transmit;

The local logic unit; And

Sensing processor unit array wherein is by means of the response data control signal, can and be modulated into the various statements that comprise (and expansion) conventional space and temporary transient treatment conversion with image conversion, the shaping of original sensing.

2. integrated sensor processing unit device, it comprises:

Be configured to produce the sensing medium of the pixel output of sign;

Be configured to store at least one storage component part of weight position, wherein at least one storage component part is configured to store the pixel output of sign;

The a plurality of multipliers relevant with at least one storage component part work;

With at least one the relevant trsanscondutance amplifier of at least one work in a plurality of multipliers, this at least one trsanscondutance amplifier is used to the operation in having the unit follower structure of variable gain;

The relevant many input logic gates of at least one described storage component part with the pixel output that is used for storing sign; And

Integrated sensor processing unit wherein is by means of the response data control signal, can and be modulated into the various statements that comprise (and expansion) conventional space and temporary transient treatment conversion with image conversion, the shaping of original sensing.

3. integrated sensing and image device, it comprises:

By the array that the sensing processor unit that can be arranged in detection array is formed, each described sensing processor unit comprises:

But be used for producing the sensing medium of the signal output of electrical representation;

Quantize the device of described sensor output,

Store the device of described sensor output,

Be arranged in a plurality of programmable logic elements on the honeycomb grid, wherein each logic element can receive input from the output and the output of himself of neighbour unit; And

Integration imaging device wherein is by means of response inside or external data control signal, can and be modulated into the various statements that comprise (and expansion) conventional space and temporary transient treatment conversion with conversion of signals, the shaping of original sensing.

Images