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CN1440074A - 半导体装置及其制造方法、电路板和电子仪器 - Google Patents

半导体装置及其制造方法、电路板和电子仪器 Download PDF

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CN1440074A
CN1440074A CN03103719A CN03103719A CN1440074A CN 1440074 A CN1440074 A CN 1440074A CN 03103719 A CN03103719 A CN 03103719A CN 03103719 A CN03103719 A CN 03103719A CN 1440074 A CN1440074 A CN 1440074A
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semiconductor chip
substrate
wiring pattern
semiconductor device
semiconductor
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CN1224097C (zh
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谷口润
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明提供一种半导体装置，它包含：具有第一布线图案(12)的衬底(10)、形成在衬底(10)上的外部端子(14)、面朝下接合在衬底(10)上的具有第二布线图案(24)的第一半导体芯片(20)、面朝下接合在第一半导体芯片(20)上的第二半导体芯片。外部端子的配置不受限制、安装性好。

Description

半导体装置及其制造方法、电路板和电子仪器
技术领域
本发明涉及半导体装置及其制造方法、电路板和电子仪器。
背景技术
以往，作为具有多个半导体芯片的CSP(Chip Size/Scale Package)型的半导体装置，众所周知的有：在衬底的两面上搭载半导体芯片的结构、以及由引线接合法连接半导体芯片和衬底的结构。
但是，如果在衬底的两面上搭载半导体芯片，有时就会限制半导体装置的外部端子的配置。另外，如果根据由引线接合法连接半导体芯片和衬底的结构，则会使半导体装置大型化，还需要模压密封的步骤。
发明内容
鉴于以上所述问题的存在，本发明的目的在于：提供对外部端子的配置没有限制，安装性好的半导体装置及其制造方法、电路板和电子仪器。
(1)本发明的半导体装置包含：在第一面上形成有第一布线图案的衬底；
形成在所述衬底的第二面一侧，与所述第一布线图案电连接的多个外部端子；
具有第二布线图案，面朝下接合在所述衬底的所述第一面上，并且电连接着所述第一布线图案的第一半导体芯片；
面朝下接合在所述第一半导体芯片的形成有所述第二布线图案的面上，电连接着所述第二布线图案的第二半导体芯片。
根据本发明，第二半导体芯片配置在第一半导体芯片和衬底之间。因此，能实现半导体装置的小型化。另外，在第一半导体芯片和衬底之间，如果填充底层填料，就不需要另外模压密封第二半导体芯片的步骤。而且，因为第二半导体芯片不限制外部端子的配置，所以能自由地选择外部端子的位置。
(2)在该半导体装置中，
在与所述第二半导体芯片重叠的区域中可以至少形成有所述多个外部端子中的一个。
据此，就能在第二半导体芯片的区域内形成外部端子。
(3)在该半导体装置中，还可以包含：
形成在所述第一半导体芯片和所述衬底之间的底层填料。
据此，就能保护第一半导体芯片和第二半导体芯片或衬底的接合部。
(4)在该半导体装置中，
在所述衬底的所述第一面上形成有凹部；
所述第二半导体芯片可以进入所述凹部。
据此，就能避免衬底以及第一布线图案和第二半导体芯片的接触。
(5)在本发明的电路板上安装了所述半导体装置。
(6)本发明的电子仪器具有所述半导体装置。
(7)本发明的半导体装置的制造方法包含：在第一半导体芯片上面朝下接合第二半导体芯片；
在衬底上面朝下接合所述第一半导体芯片；
在所述衬底上形成多个外部端子；
第一布线图案形成在所述衬底的第一面上，所述外部端子形成在所述衬底的第二面上，所述第一布线图案和所述外部端子电连接在一起；
所述第二半导体芯片面朝下接合在所述第一半导体芯片的形成有第二布线图案的面上，电连接着所述第二布线图案；
所述第一半导体芯片面朝下接合在所述衬底的所述第一面上，电连接着第一布线图案。
根据本发明，第二半导体芯片配置在第一半导体芯片和衬底之间。因此，能使半导体装置小型化。另外，如果在第一半导体芯片和衬底之间填充底层填料，就能省略另外模压密封第二半导体芯片的步骤。而且，因为第二半导体芯片不限制外部端子的配置，所以能自由选择外部端子的位置。
(8)在该半导体装置的制造方法中，
在与所述第二半导体芯片重叠的区域中可以形成所述多个外部端子中的至少一个。
据此，就能在第二半导体芯片的区域内形成外部端子。
(9)在该半导体装置的制造方法中，还可以包含：
在所述第一半导体芯片和所述衬底之间设置底层填料的步骤。
据此，就能保护第一半导体芯片和第二半导体芯片或衬底的接合部。
(10)在该半导体装置的制造方法中，
在所述第一半导体芯片和所述第二半导体芯片之间、所述第一半导体芯片和所述衬底之间，可以用一次的步骤设置所述底层填料。
据此，就能用一次的步骤设置底层填料，能提高作业效率。
(11)在该半导体装置的制造方法中，
所述衬底的所述第一面具有凹部；
使所述第二半导体芯片进入所述凹部。
据此，就能使第二半导体芯片和衬底以及第一布线图案不接触。
附图说明
下面简要说明附图。
图1是表示应用了本发明的实施例1的半导体装置的图。
图2是表示应用了本发明的实施例2的半导体装置的图。
图3是表示本发明实施例的电路板的图。
图4是表示本发明实施例的电子仪器的图。
图5是表示本发明实施例的电子仪器的图。
下面简要说明附图符号。
10-衬底；12-第一布线图案；14-外部端子；18-第一面；19-第二面；20-第一半导体芯片；22-第一电极；24-第二布线图案；30-第二半导体芯片；32-第二电极；40-底层填料；52-凹部；54-第三布线图案。
具体实施方式
下面，参照附图，就本发明的实施例加以说明。但是，本发明并不局限于以下的实施例。
(实施例1)
图1是表示应用了本发明的实施例1的半导体装置的图。本实施例的半导体装置具有衬底10。衬底10也可以称作布线衬底或插入层。衬底10的平面形状一般为矩形，但是并不局限于此。另外，衬底10的整体形状并未特别限定。
衬底10的材料可以是有机类或无机类的任意一种材料，也可以是由它们的复合结构构成的材料。作为衬底10，例如可以使用由聚对苯二甲酸乙二醇酯(PET)构成的衬底或薄膜。或者，可以使用由聚酰亚胺树脂构成的柔性衬底作为衬底10。作为柔性衬底，可以使用FPC(FlexiblePrinted Circuit)、TAB(Tape Automated Bonding)技术中使用的带。另外，作为由无机类的材料形成的衬底10，例如有陶瓷衬底和玻璃衬底。作为有机类和无机类的材料的复合结构，例如有玻璃环氧衬底。
在衬底10上形成有第一布线图案12。也可以把衬底10的形成有第一布线图案12的面称作第一面18。例如通过图中未显示的粘合材料把铜箔等金属箔粘贴在衬底10上，可以在应用了光刻后，蚀刻形成第一布线图案12。此时，构成了三层衬底。或者，也可以不用粘合材料，在衬底10上形成第一布线图案12，构成2层衬底。例如，可以通过溅射等，形成第一布线图案12。或者，也可以应用由非电解镀层形成第一布线图案12的添加法。另外，第一布线图案12可以具有凸台部。另外，可以避开第一布线图案取得电连接的部分，在第一布线图案12的表面形成绝缘膜。
在衬底10上形成有外部端子14。外部端子14可以形成在衬底10的第一面18的背面，也可以把形成有外部端子14的面称作第二面19。可以把焊锡球作为外部端子14。或者，可以在通孔16的内部使第一布线图案12的一部分弯曲，形成外部端子14。外部端子14电连接着第一布线图案12。在图1所示的例子中，第一布线图案12和外部端子14通过通孔16电连接。
在衬底10的第二面19一侧，未安装第一半导体芯片20和第二半导体芯片30，所以能在衬底10的第二面19的任一位置形成外部端子14。在图1所示的例子中，因为外部端子14只形成在第一半导体芯片20的安装区域的内侧，所以该半导体装置为输入端型。或者，只在第一半导体芯片20的安装区域的外侧形成外部端子14，作为输出端型。或者，在第一半导体芯片20的内侧和外侧形成外部端子14，作为输入/输出端型。
本实施例的半导体装置具有第一半导体芯片20。第一半导体芯片20例如是闪存、SRAM、DRAM、AISC或MPU等。作为第一半导体芯片20和后面描述的第二半导体芯片30的组合，例如有SRAM间、DRAM间、或者闪存和SRAM，但是并不局限于此。第一半导体芯片20的平面形状常常为矩形(正方形或长方形)。在第一半导体芯片20的一方的面(有源面)形成有多个第一电极22和第二布线图案24。另外，在第一半导体芯片20的有源面也可以形成图中未显示的钝化膜。钝化膜例如能由SiO2、SiN、聚酰亚胺树脂形成。
在第一半导体芯片20形成有第一电极22。第一电极22可以沿着第一半导体芯片20的有源面的至少一边(常常是平行的2边或4边)排列。第一电极22可以避开第二半导体芯片30的安装区域形成，也可以包围第二半导体芯片30的安装区域而形成。图1所示的第一电极22包含焊盘26和凸台28。焊盘26例如可以由铝或铜等在第一半导体芯片20上，薄而平地形成。凸台28可以由非电解镀层形成，也可以是基于引线接合的凸台。在焊盘26和凸台28之间可以附加镍、铬、钛等作为凸台金属的扩散防止层。或者，可以没有凸台28，而只用焊盘构成电极22。另外，可以设定第一电极22的高度，使第二半导体芯片30与衬底10或第一布线图案12不接触。
在第一半导体芯片20上形成有第二布线图案24。第二布线图案24可以在设置在第一半导体芯片20的有源面上的钝化膜(图中未显示)上形成。第二布线图案24可以由与形成第一布线图案12的步骤相同的步骤形成。
本实施例的半导体装置具有第二半导体芯片30。第二半导体芯片30与第一半导体芯片20的内容相同。第二半导体芯片30常常为矩形。第二半导体芯片30具有多个第二电极32，第二电极32形成在第二半导体芯片30的一方的面(有源面)上。第二电极32可以沿着第二半导体芯片30的面的至少一边(常常是平行的2边或4边)排列。第二电极32可以采用与所述的第一电极22相同的结构。另外，可以设定第二电极32的高度，使第二半导体芯片30不接触衬底10或第一布线图案12。
在本实施例中，第二半导体芯片30面朝下接合(倒装)在第一半导体芯片20上。而且，第二电极32与第二布线图案24电连接。
另外，在本实施例中，安装了第二半导体芯片30的第一半导体芯片20面朝下接合(倒装)在衬底10上。而且，第一电极22和第一布线图案12电连接。
本发明的半导体装置在衬底10和第一半导体芯片20配置了第二半导体芯片30。因此，能使半导体装置变薄。另外，因为面朝下接合(倒装)了第二半导体芯片30和第一半导体芯片20，所以没必要通过引线实现电连接，不需要模压密封的步骤。
在衬底10和第一半导体芯片20之间可以设置底层填料40。底层填料40可以是以液状或胶状准备的粘合剂，也可以是由薄板状准备的粘合薄板。粘合剂可以以环氧树脂为主要材料。粘合剂可以是绝缘性的，例如NCF(Non Conductive Film)和NCP(Non Conductive Paste)。
底层填料40可以是分散了导电粒子的各向异性导电粘合剂(ACA)，例如各向异性导电膜(ACF)和各向异性导电胶(ACP)。各向异性导电粘合剂是在粘合剂中分散了导电粒子(填充剂)，有时是添加了分散剂。作为各向异性导电粘合剂的粘合剂，常常使用热硬化性的粘合剂。
衬底10的至少设置底层填料40的区域可以为粗糙面。即可以使用喷沙，机械地使衬底10的表面粗糙；或者使用等离子体、紫外线、臭氧等，在物理上使衬底10的表面粗糙；使用蚀刻剂，在化学上使衬底10的表面粗糙。据此，就能使衬底10和底层填料40的粘合面积增大，或使物理、化学的粘合力增大，使两者更牢固地粘合。利用底层填料40的收缩力，通过使第一布线图案12和第一电极22压接，使第二布线图案24和第二电极32压接，能提高半导体装置的电连接的可靠性。
本实施例的半导体装置的结构如上所述，下面，说明它的制造方法。
预先准备形成有上述的第一布线图案12以及外部端子14的衬底10、形成有电极22和第二布线图案24的第一半导体芯片20、形成有电极32的第二半导体芯片。
在进行了把第二半导体芯片30安装到第一半导体芯片20上的第一步骤后，进行把第一半导体芯片20安装到衬底10上的第二步骤，通过最后设置底层填料40，就得到了本发明的半导体装置。
在第一和第二步骤中，可以利用面朝下接合和倒装。当进行面朝下接合时，有基于Au-Au、Au-Sn、粘合剂等的金属接合的方法、基于绝缘树脂的收缩力的方法，可以采用其中的任意方法。
另外，在本实施例中，在第一半导体芯片20上安装第二半导体芯片30，在衬底10上安装了第一半导体芯片20后，设置底层填料40。因此，能用一次的步骤来设置底层填料40。
(实施例2)
图2是用于说明应用了本发明的实施例2的半导体装置的图。须指出的是，即使在本实施例中，也能尽可能应用实施例1中说明了的内容。
在本实施例的衬底10上形成有凹部52。凹部52形成在衬底10的第一面一侧。凹部52的形状并未特别限定，另外，凹部52的深度也未特别限定。本实施例的半导体装置能把配置在衬底10和第一半导体芯片20之间的第二半导体芯片30嵌入凹部52。因此，能使该半导体装置变薄。
在本实施例的衬底10上可以形成第一布线图案12。第一布线图案12可以避开凹部52而形成。
在本实施例的衬底10上可以形成第三布线图案54。第三布线图案54可以由与形成第一布线图案12或第二布线图案24的步骤同样的步骤形成。第三布线图案54电连接着第一布线图案12。在图2所示的例子中，在衬底10上形成有通孔56，第三布线图案54通过通孔56电连接着第一布线图案12。在第三布线图案54的表面可以避开与外部端子14接触的部分而形成绝缘膜。
在本实施例的衬底10上形成有外部端子14。在图2所示的例子中，外部端子14形成在第三布线图案54上，通过第三布线图案54，电连接着第一布线图案12。但是，也可以通过通孔16，使外部端子14直接接触第一布线图案12。
即使在本实施例的半导体装置中，在衬底10的第二面19上也未安装第一半导体芯片20和第二半导体芯片30的任意一个。因此，能在衬底10的第二面19一侧的任意位置形成第三布线图案54和外部端子14。另外，利用第三布线图案54，通过实现第一布线图案12和外部端子14的电连接，能不受凹部52的位置的影响，配置外部端子14。
作为具有本发明的实施例的半导体装置的电子仪器，在图3中表示了安装了本发明的实施例的半导体装置的电路板1000，图4中表示了笔记本型个人电脑2000，图5中表示了移动电话3000。
本发明并不局限于上述的实施例，能有各种变形。例如，本发明包含与实施例中说明的结构实质上相同的结构(例如，功能、方法以及结果相同的结构或目的以及结果相同的结构)。另外，本发明包含置换了实施例中说明的结构的非本质的部分的结构。另外，本发明包含与实施例中说明的结构能产生相同作用的结构或能实现相同目的的结构。另外，本发明包含在实施例中说明的结构中附加了公知技术的结构。

Claims (11)

1.一种半导体装置，其特征在于，包含：
在第一面上形成有第一布线图案的衬底；
形成在所述衬底的第二面一侧，与所述第一布线图案电连接的多个外部端子；
具有第二布线图案，面朝下接合在所述衬底的所述第一面上，并且电连接着所述第一布线图案的第一半导体芯片；
面朝下接合在所述第一半导体芯片的形成了所述第二布线图案的面上，电连接着所述第二布线图案的第二半导体芯片。
2.根据权利要求1所述的半导体装置，其特征在于：
在与所述第二半导体芯片重叠的区域中至少形成有所述多个外部端子中的一个。
3.根据权利要求1或2所述的半导体装置，其特征在于：还包含：
形成在所述第一半导体芯片和所述衬底之间的底层填料。
4.根据权利要求1～3中任意一项所述的半导体装置，其特征在于：
在所述衬底的所述第一面形成有凹部；
所述第二半导体芯片进入所述凹部。
5.一种电路板，其特征在于：
电连接了权利要求1～4中任意一项所述的半导体装置。
6.一种电子仪器，其特征在于：
具有权利要求1～4中任意一项所述的半导体装置。
7.一种半导体装置的制造方法，其特征在于：包含：
在第一半导体芯片上面朝下接合第二半导体芯片；
在衬底上面朝下接合所述第一半导体芯片；
在所述衬底上形成多个外部端子；
第一布线图案形成在所述衬底的第一面上，所述外部端子形成在所述衬底的第二面上，所述第一布线图案和所述外部端子电连接在一起；
所述第二半导体芯片面朝下接合在所述第一半导体芯片的形成了第二布线图案的面上，与所述第二布线图案电连接；
所述第一半导体芯片面朝下接合在所述衬底的所述第一面上，与所述第一布线图案电连接。
8.根据权利要求7所述的半导体装置的制造方法，其特征在于：
在与所述第二半导体芯片重叠的区域中形成所述多个外部端子中的至少一个。
9.根据权利要求7或8所述的半导体装置的制造方法，其特征在于：还包含：
在所述第一半导体芯片和所述衬底之间设置底层填料。
10.根据权利要求9所述的半导体装置的制造方法，其特征在于：
在所述第一半导体芯片和所述第二半导体芯片之间、所述第一半导体芯片和所述衬底之间，用一次的步骤设置所述底层填料。
11.根据权利要求7～10中任意一项所述的半导体装置的制造方法，其特征在于：
所述衬底的所述第一面具有凹部；
使所述第二半导体芯片进入所述凹部。
CNB031037194A 2002-02-21 2003-02-17 半导体装置及其制造方法、电路板和电子仪器 Expired - Fee Related CN1224097C (zh)

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JP4639731B2 (ja) * 2004-09-30 2011-02-23 セイコーエプソン株式会社 半導体装置の実装方法
JP4875844B2 (ja) * 2004-11-25 2012-02-15 ローム株式会社 半導体装置の製造方法
JP2009302212A (ja) * 2008-06-11 2009-12-24 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法
US8836115B1 (en) * 2008-07-31 2014-09-16 Amkor Technology, Inc. Stacked inverted flip chip package and fabrication method
JP2010074072A (ja) * 2008-09-22 2010-04-02 Nec Corp 半導体装置および半導体装置の製造方法
US20100289138A1 (en) * 2009-05-13 2010-11-18 Kenji Masumoto Substrate structure for flip-chip interconnect device
US20110051352A1 (en) * 2009-09-02 2011-03-03 Kim Gyu Han Stacking-Type USB Memory Device And Method Of Fabricating The Same
KR101531097B1 (ko) * 2013-08-22 2015-06-23 삼성전기주식회사 인터포저 기판 및 이의 제조방법
KR102311677B1 (ko) * 2014-08-13 2021-10-12 삼성전자주식회사 반도체소자 및 그 제조방법
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US11373946B2 (en) * 2020-03-26 2022-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
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TWI800104B (zh) * 2021-11-19 2023-04-21 欣興電子股份有限公司 晶片封裝結構及其製作方法

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