CN1412994A - Radio communication base band modulation circuit and its multichannel gain matching control method - Google Patents

Abstract

The wireless communication baseband modulator circuit includes auxiliary circuit, digital modulation module, multi-channel gain control module, analog processing module, gain error detection module, timer and sine-wave generator. The multi-channel gain control module, multi-channel analog processing module and gain error detection module are connected and formed into a multi-channel gain control loop. Said multi-channel gain control module can implement gain regulation function on the circuit in the course of electric initialization, and the gain error detection module can be used for detecting analog output of multi-channel analog processing module and calculating gain regulation coefficient of other channel except for reference channel. Said invention is applicable to high-frequency baseband modulation of wireless communication.

Description

Radio communication base band modulation circuit and multichannel gain matching control method thereof

Technical field

The present invention relates to a kind of wireless communication baseband modulation technique, relate to or rather a kind ofly adopt adaptive technique, the multichannel baseband modulation in the radio communication is carried out the control method of the radio communication base band modulation circuit of accurate gain controlling and multichannel gain coupling thereof, its circuit design then is particularly suitable for being produced on the integrated circuit (IC) chip.

Technical background

In existing wireless communication baseband modulating system, each interchannel gain coupling is that the manufacturing process by integrated circuit guarantees.Though integrated circuit has the better matching property energy to device closely, the interchannel coupling for being formed by a plurality of circuit modules then is difficult to guarantee its matching precision.

The gain of signal is not simultaneously when between each circuit path, particularly in modern wireless communication systems, be extensive use of under the condition of phase modulation technique, signal phase deviation will occur and noise margin is reduced in decode procedure situation, correspondingly improved the error rate and caused communication speed to reduce, therefore the signal gain matching precision of each circuit path of control is crucial in baseband modulation.

Illustrate a kind of structure of presently used multichannel wireless communication baseband modulation integrated chip in the accompanying drawing 1, mainly comprise digital modulation module (DIGITAL MODULATION) 11, simulation process module (ANALOGPROCESS) 12 and auxiliary circuit module (AUXILIARY CIRCUIT) 13.Simulation process module 12 wherein is provided with a plurality of treatment channel (as Q), and each treatment channel is by digital to analog converter (DAC) 121 (as 12～14 bits), filter (FILTER) 122 and analog line driver (DRIVER) 123 formation that is linked in sequence.

Input data (DATA INPUT) are finished digital modulation after entering the digital modulation module 11 of chip internal, mode with parallel (12～14bits position) multichannel (Q) data-signal sends simulation process module 12 to, in simulation process module 12, finish digital-to-analogue conversion, filtering and power drive respectively by a plurality of (Q) simulation process passage of correspondence, export in the mode of multichannel (Q) analog signal then, the multichannel OUTPUT1 of output,, the OUTPUT Q signal is delivered to the back level processor.

The logic input terminal of this chip (LOGIC INPUT) is mainly used in to be controlled the various functions of chip, and auxiliary circuit module 13 is mainly finished functions such as voltage reference.

According to schematic structure as can be seen the main feature of this multichannel integrated chip circuit baseband modulation be:

(1). the modulation to the data input signal is finished with digital form, and for the radio communication in modern times, the digital baseband modulation has advantages such as precision height, response speed is fast, antijamming capability is strong;

(2). do not proofread and correct for each interchannel that partly produces by simulation process unmatched situation that gains, just with the integrated circuit fabrication process consistency preferably characteristics ERROR CONTROL that Q interchannel gained in certain scope;

(3). because the integrated circuit fabrication process error is a random distribution, cause chip performance to be offset within the specific limits, make the consistency of each chip parameter relatively poor;

(4). if adopt laser-adjusting and melt aluminium, melt bearing calibration such as polysilicon silk, need chip be tested, and test process needs by precision instrument, thereby increased the difficulty and the cost of chip testing;

(5). laser-adjusting has only large-scale semiconductor company just to have the ability to do, and is not suitable for general manufacturer and adopts;

(6) even. proofreaied and correct precision, but circuit chip still may produce skew after long-time the use, cause the chip electric property to reduce.

In sum, the multichannel of the radio communication quadrature modulation Base-Band Processing integrated chip circuit of obvious structure shown in Figure 1 gain coupling guarantees that technology is not fill part, and the utmost point has improved necessity.

Summary of the invention

The objective of the invention is to design a kind of wireless communication multichannel base band modulation circuit and multichannel gain matching control method thereof, its circuit is the radio communication base band modulation circuit with multichannel gain coupling controlled function, be suitable in the high frequency baseband modulation of wireless communication system, using, especially in high performance wireless communication system, use, as GPRS (GPRS) pattern of GSM, the baseband modulation integrated chip circuit design of Wideband Code Division Multiple Access (WCDMA) (W-CDMA) system, and adjust the precision height, error can not occur adjusting because of service time is long.

The technical scheme that realizes the object of the invention is such: a kind of wireless communication multichannel base band modulation circuit, comprise auxiliary circuit, to importing the digital modulation module that data are carried out digital modulation and exported the parallel multi-channel data, simulation process module with parallel multi-channel data subchannel being carried out output multi-channel analog signal after digital-to-analogue conversion, filtering and the power drive is characterized in that:

Also comprise multichannel gain control module and gain error detection module; Multichannel gain control module, described multichannel analog processing module and gain error detection module connect and compose the multichannel gain control loop; The gain error detection module carries out the channel selecting detection and calculates each channel gain adjustment coefficient the multi-channel analog signal of multichannel analog processing module output, pass to the multichannel gain control module again, carrying out after each interchannel gain-adaptive coupling control again to the parallel multi-channel data of digital modulation module output, subchannel is sent to the multichannel analog processing module; Also include the sine-wave generator and the timer that connect digital modulation module and gain error detection module respectively, in the initialization procedure of timer-operated channel gain control loop operating time, ride gain error-detecting module is carried out the gain error test and gain adjustment factor calculates.

Described multichannel gain control module is connected and composed by the accurate passage of a roadbed, the common passage in other road and a synchronous circuit; The benchmark passage is connected and composed by pre-attenuator circuit and delay circuit, and each common passage is connected and composed by pre-attenuator circuit and gain adjustment circuit; The benchmark passage is distinguished the corresponding parallel multi-channel data that connect described digital modulation module output with the pre-attenuator circuit of common passage, the delay circuit of benchmark passage is connected described synchronous circuit with the gain adjustment circuit of common passage, the parallel multi-channel data of synchronous circuit output are sent to each analog to digital conversion circuit of described simulation process module.

Described gain error detection module is linked in sequence by analog switch, analog to digital conversion circuit, digital peak testing circuit and gain error counting circuit and constitutes; Analog switch is connected with the multi-channel analog signal output of described simulation process module, and the output of gain error counting circuit connects described gain control module, and each channel gain of gain control module is carried out the self adaptation adjustment.

Described pre-attenuator circuit is connected and composed by shift register, adder and subtracter, to the input data be shifted, addition, the operation that addition more finally subtracts each other that is shifted again, by the position of selection shift register and the figure place of displacement, realize the attenuation coefficient that requires to the input data.

Described gain adjustment circuit by " with " array, shift register, adder and multiplier connect and compose, by " with " array carries out AND operation to each logic input of input data and ride gain respectively, again by the position of selection shift register and the figure place of displacement, to " with " operation result of array is shifted, addition, again to addition result be shifted, addition, finally by multiplier under the control of adjusting the gain operator to the operation that adds deduct of input data and final addition result, realize requiring to importing the gain coefficient of data.

Described auxiliary circuit, sine-wave generator, timer, digital modulation module, multichannel gain control module, simulation process module, gain error detection module are produced on the integrated circuit (IC) chip.

The technical scheme that realizes the object of the invention still is such: a kind of multichannel gain matching control method of radio communication base band modulation circuit is characterized in that comprising following treatment step:

A. circuit powers on and enters initial phase;

B. the digitized sine wave signal of sine-wave generator output is sent into digital modulation module as the data-signal of input and carry out digital modulation, and send the multichannel gain control module to the mode correspondence of parallel multi-channel data;

C. selecting a passage in the gain control module is the benchmark passage, the parallel signal of importing this benchmark passage enters synchronous circuit after decaying in advance, postponing, the parallel signal of other passage beyond the input reference passage also enters synchronous circuit through pre-decay, gain after adjusting, and the parallel multi-channel data-signal of synchronous circuit output send the simulation process module;

D. by a plurality of simulation process passages corresponding in the simulation process module parallel multi-channel data-signal is carried out digital-to-analogue conversion, filtering and power drive respectively, the output multi-channel analog signal send the gain error detection module simultaneously;

When E. utilizing by the analog switch of gain error detection module merotype to multichannel analog output carry out gating and analog-to-digital conversion, by the amplitude that detects respective channel the dateout of digital peak testing circuit after analog-to-digital conversion, from this amplitude information, calculate the initial phase gain coefficient that each passage need be adjusted except that the benchmark passage by the gain error counting circuit, and pass to the multichannel gain control module, to the adjustment that gains of the gain adjustment circuit of each passage except that the benchmark passage, finish each interchannel gain-adaptive control;

F. finish initial phase, locking gain error counting circuit calculates the gain coefficient that obtains, and the gain error detection module is placed off position.

Described steps A further comprises:

A. in the initialization procedure that circuit powers on, earlier with in the multichannel gain control module except that the benchmark passage gain coefficient of each gain adjustment circuit be changed to default value;

B. the data input with digital modulation module switches to sinusoidal wave binary data input;

Described step e further comprises:

C. by the gain error detection module with the benchmark passage in the multichannel gain control module as the reference passage, detect and calculating benchmark passage and other interchannel gain errors, calculate the gain adjustment factor of each respective channel according to the amplitude digital quantity and the ratio of each passage amplitude digital quantity of reference channel;

D. the gain coefficient correspondence that each channel gain is adjusted circuit except that the benchmark passage in the multichannel gain control module is changed to by step c and calculates the gain adjustment factor value that obtains, when the gain error of benchmark passage and other passages is in preset range, other passages and benchmark passage coupling;

E. the data input of digital modulation module is switched to the data input of outside by the sinusoidal wave binary data input of inside.

The sample frequency Cheng Fei of analog to digital conversion circuit is divided exactly relation in the signal frequency of described sine wave and the described gain error detection module, and quantizes to realize over-sampling by the sine wave to an above cycle of analog-digital conversion circuit as described.

The initial phase of described steps A and step e is adjusted required precision by a timer according to gain and is carried out length control.

Radio communication base band modulation circuit of the present invention and multichannel gain matching control method thereof, in the wireless communication baseband modulation, adopt the coupling control technology of amplitude between multichannel, its chip circuit comprises: digital modulation, gain controlling, simulation process, gain error detect, the sinusoidal wave generation, timing, circuit modules such as auxiliary unit.Gain control stages wherein is made of pre-attenuation module, gain regulation module, time delay module and synchronization module.Gain error detection module wherein is made of modules such as analog switch, analog-to-digital conversion (ADC), digital peak detection, gain error calculating.

Digital modulation module in the circuit of the present invention can adopt and comprise GMSK, 8PSK, QAM and the modulation scheme relevant with the GSM technology with CDMA.

Gain controlling of the present invention is finished at numerical portion, simultaneously at multichannel characteristics, is benchmark with some passages, precision is carried out in the gain of other passage control, and guarantees that at last digital signal exports synchronously.

Gain control stages of the present invention, its pre-decay is a parameter of determining according to integrated circuit technology, and at different technology and rate of finished products requirement, this parameter is variable, and simultaneously, the multiplying of pre-decay realizes by simple adder.

Gain control stages of the present invention, the adjustment of gain can be carried out (positive and negative scope) on both direction, and the multiplying that gain is adjusted is finished by simple adder.The digital peak testing circuit detects the amplitude of respective channel from the dateout of analog to digital conversion circuit, keep the gain of benchmark passage constant, and be reference with it, from the amplitude information of each passage, calculate the gain error of each passage and the gain coefficient that need adjust thereof by the gain error counting circuit, and pass to the gain adjustment circuit of respective channel in the gain control module, finish inner each the interchannel gain-adaptive control of chip circuit automatically.

The present invention is that the quantification by sine wave is finished in the chip initiation process to the detection of gain, any two interchannel errors are quantized by same analog to digital converter (ADC), peak value by detection signal calculates its amplitude again, thereby obtains the gain error of passage.The present invention is designed to the non-relation that divides exactly with the frequency of sine-wave generator signal and the sample frequency of analog to digital converter (ADC), by the quantification to a plurality of cycles, reaches the purpose of over-sampling, thus accurate detection signal peak value.

Initialization procedure of the present invention, be that the precision decision that the length of initialization procedure is adjusted by gain is after initialization finishes by the decision of the timer of chip internal, it is promptly locked to calculate the gain error that obtains, and circuit such as analog switch, analog-to-digital conversion, digital peak then place off position.

The beneficial effect of technical solution of the present invention is:

(1). realize gain adjustment automatically, need not to adopt extra test and corrective action;

(2). the adjustment of gain can be used on the integrated chip that utilizes different semiconductor technologies to make at chip circuit, particularly uses on the FOUNDRY business;

(3). gain adjustment is adopted adaptive technique, thereby the error of each piece integrated circuit (IC) chip all is controlled in the corresponding scope;

(4). the adjustment that after circuit chip powers at every turn, promptly gains automatically, thereby As time goes on control precision can not change.

Gain control module is finished gain and is adjusted function in the power-up initializing process of chip circuit, be to utilize low frequency signal to detect gain error at this moment, the signal of normal modulation then can be operated in high-frequency region, therefore be suitable in the high frequency baseband modulation of radio communication, using, simultaneously, also have very high adjustment precision, error can not occur adjusting along with the lengthening of service time, be particularly suitable in high performance system, use in the chip design as the GPRS pattern of GSM, W-CDMA etc.

Description of drawings

Fig. 1 is the baseband processing chip structural representation of radio communication quadrature modulation.

Fig. 2 adopts multichannel to mate the baseband processing chip structural representation of the radio communication quadrature modulation of correction automatically.

Fig. 3 is that coefficient is the structural representation block diagram of 0.96 pre-decay implementation.

Fig. 4 is that coefficient is the signal flow block diagram of 0.96 pre-decay implementation.

Fig. 5 is that step-length is 1/512, adjusting range is the ± gain controlling implementation structure schematic block diagram of (15/512).

Fig. 6 is that step-length is 1/512, adjusting range is the ± gain controlling implementation signal flow block diagram of (15/512).

Fig. 7 is wrong digital peak detection waveform schematic diagram.

Fig. 8 is correct digital peak detection waveform schematic diagram.

Embodiment

Addressed before Fig. 1 illustrates and repeated no more.

Referring to Fig. 2, the radio communication quadrature modulation baseband processing circuitry structure that illustrates among the figure, adopted self-adapting multi-channel of the present invention to mate alignment technique automatically, and be made into integrated circuit (IC) chip, have the baseband processing chip that multichannel mates the radio communication quadrature modulation of calibration result automatically thereby form.

Same Fig. 1 of structure of the digital modulation module that is comprised (DIGITAL MODULATION) 21, simulation process module (ANALOGPROCESS) 23 and auxiliary circuit module (AUXILIARY CIRCUIT) 26, simulation process module 23 wherein also is provided with a plurality of treatment channel (as Q), each treatment channel is by digital to analog converter (DAC) 231, filter (FILTER) 232 and analog line driver (DRIVER) 233 formation that is linked in sequence.

The present invention has increased gain control module (GAIN ADJUSTMENT) 22, gain error detection module 24, timer 27 and sine wave signal generator 25 on the basis of above-mentioned basic structure.

The data-signal (in the initialization procedure) of data (DATA INPUT) signal of outside input or 25 outputs of inner sine wave signal generator enters the digital modulation module (DIGITAL MODULATION) 21 of chip internal and finishes digital modulation, and (mode of 12～14bits) multichannels (Q) data is given gain control module (GAIN ADJUSTMENT) 22 to walk abreast.Digital modulation can adopt and comprise GMSK, 8PSK, QAM and the modulation scheme relevant with the GSM technology with CDMA.

Selecting a passage in the gain control module 22 is the benchmark passage, and the parallel data signal of importing this benchmark passage enters synchronous circuit (SYNC) 223 through pre-decay (pre_att) circuit 221 pre-decay with through postponing after (DELAY) circuit 222 postpones; And also enter synchronous circuit (SYNC) 223 after the gain adjustment of the parallel data signal process of importing other passage pre-the decay 221 pre-decay of (pre_att) circuit and process gain adjustment (GAIN ADJUSTMENT) circuit 224,223 pairs of multichannel binary systems of synchronous circuit (SYNC) (adjustment) data are carried out Synchronous Processing before it enters the simulation process module, avoiding producing phase error when the digital-to-analogue conversion, (12～14bits) multichannels (Q) data-signal send simulation process module 23 for synchronous circuit 223 outputs parallel.

The present invention takes to finish at numerical portion the scheme of gain controlling, simultaneously at multichannel characteristics, is benchmark with a certain passage, precision is carried out in the gain of other passages control, and guarantees that at last digital signal exports synchronously.With the passage that does not have gain adjustment circuit 224 is the benchmark passage, the input data of any one external channel can be sent in this benchmark passage, the foundation that other passages are adjustment with this benchmark passage, when soon the gain error of the gain of other passages and benchmark passage is controlled within the specific limits, think that these two passages mate.

The present invention as the parameter of being determined by the integrated circuit fabrication process error, at different technology and rate of finished products requirement, and should change pre-attenuation parameter with pre-attenuation coefficient, i.e. the scope that gain is adjusted is answered the covering process error, as matching error is controlled in 5%.

After pre-decay, even gain error is arranged, the gain of passage can not overflowed yet, and this also is to keep the benchmark channel gain constant, only the reason that can meet the demands to other channel gain adjustment.The time of delay of delay circuit 222 is by the clock cycle decision (not shown) that realizes that gain is adjusted.

Because multichannel gain regulation module 22 is to utilize binary data adjustments that gain, so the coefficient that only changes gain adjustment circuit 224 just can be adjusted gain.

D/A converting circuit 231), filtering (filter circuit 232) and power drive (power driving circuit 233) in simulation process module 23, finish digital-to-analogue conversion (DAC: respectively by a plurality of (Q) simulation process passage of correspondence, export in the mode of multichannel (Q) analog signal then, the multichannel OUTPUT 1 of output, OUTPUT Q analog signal is delivered to the back level processor, send Error Gain detection module 24 simultaneously.

Gain error detection module 24 is by analogue multiplexer 241 (ANALOG MUX also claims analog switch), analog to digital conversion circuit (ADC) 242, digital peak testing circuit 243 and gain error counting circuit 244 process that is linked in sequence.

The multichannel simulation output OUTPUT 1 of 241 pairs of initial phases of analogue multiplexer ..., OUTPUT Q signal (amplitude) detects, and being used for the benchmark channel gain is the gain adjustment factor of other passages of reference calculation.Merotype was to multichannel analog output carrying out gating when analogue multiplexer 241 utilized, and send analog to digital conversion circuit 242 to convert digital signal to the analog output signal of selector channel, digital peak testing circuit 243 detects the digital quantity of each passage amplitude from the dateout of analog to digital conversion circuit 242, digital quantity as benchmark passage amplitude is X1X1X1, the digital quantity of rest channels amplitude is respectively X2X2X2, X3X3X3..., and be deposited with in the digital peak testing circuit 243, again by gain error counting circuit 244 according to the digital quantity of each passage amplitude and the ratio of the digital quantity of benchmark passage amplitude: (X1X1X1)/(X2X2X2), X1X1X1/X3X3X3..., calculate the gain adjustment factor of each respective channel, promptly finish the calculating of calculating the gain coefficient of each respective channel needs adjustment according to amplitude information, and pass to the gain adjustment circuit 224 of respective channel in the gain control module 22, finish inner each the interchannel gain-adaptive control of chip circuit automatically.

Sine-wave generator (sine waveform GENERATOR) 25 produces the low-frequency sine signal, uses for gain test and adjustment as input signal in system initialisation phase.Gain error detection module 24, detection to gain is that the quantification by sine wave signal is finished in the circuit initialization procedure, benchmark passage and detected interchannel gain error quantize by same analog to digital conversion circuit (ADC) 242, pass through to detect the peak value of output signal after analog-to-digital conversion and the amplitude of calculating peak value by digital peak testing circuit 243 and gain error counting circuit 244, and obtain the gain error of sense channel.The present invention remains the non-relation that divides exactly with the signal frequency of sine-wave generator 25 and the sample frequency of analog to digital conversion circuit (ADC) 242, by the quantizing process in a plurality of cycles, reaches the over-sampling purpose, thereby can accurately detect the peak value of signal.

Timer 27 is used to control operating time of the channel gain control loop initial phase that is connected and composed by gain control module 22, simulation process module 23 and gain error detection module 24.The precision decision that the length of this initialization procedure is adjusted by gain, after initialization procedure finishes, it is just locked to calculate the gain adjustment factor that obtains, and the analog switching circuit 241 in the gain error detection module 24, analog to digital conversion circuit 242, digital peak circuit 243 and gain adjustment circuit 244 all can be placed in off position.

The logic input (LOGIC INPUT) of circuit chip is mainly used in the various functions from the external control circuit chip.Auxiliary circuit module 26 is mainly finished functions such as voltage reference.

The multichannel gain control loop that connects and composes by multichannel gain control module 22, simulation process module 23 and gain error detection module 24 of the present invention, its gain controlling flow process can further be summarised as following steps:

(1) in the initialization procedure that circuit powers on, the gain coefficient with each gain adjustment circuit 224 in the multichannel gain control module 22 is changed to default value earlier;

(2) the data input with digital modulator 21 switches to sinusoidal wave binary system input;

(3) by gain error detection module 24 with the benchmark passage in the multichannel gain control module 22 as the reference passage, detect and calculate the gain error of each passage;

(4) gain coefficient of each channel gain in the multichannel gain control module 22 being adjusted circuit 224 is changed to the calculated value of above-mentioned gain error, and when the gain error of benchmark passage and other passages was in preset range, other passages and benchmark passage mated;

(5) the data input with digital modulator 21 switches to the data input by sinusoidal wave binary system input;

(6) initialization finishes, and each channel gain is adjusted the gain coefficient of circuit 224 in the locking multichannel gain control module 22, and gain error detection module 24 is changed to off position.

Below in conjunction with several concrete parameters, further specify the technical measures that the present invention takes several key technologies, comprising: the pre-decay technique of realizing particular factor; Realize the gain adjustment technology of particular factor; Realize the digital peak detection technique of specific precision.

Referring to Fig. 3, Fig. 4, implementation structure and the flow process of pre-attenuator circuit 221 shown in the figure when realizing specific 0.96 pre-attenuation coefficient.

Circuit structure mainly comprises first shift register 31, second shift register 32, the 3rd shift register 33, first adder 34, second adder 35 and subtracter 36.

Realization flow is: step 44, input data (input data) after first shift register 31 moves to right 1 bit (bit) in first adder 34 with former input data (input data) addition, obtain node N1 data (N1=DATA[N]/2+DATA[N]); Step 45, node N1 data after second shift register 32 moves to right 2 bits (bit) in second adder 35 with the addition of node N1 data, obtain node N2 data (N2=N1/4+N1); Step 46, node N2 data are subtracted each other with former input data (input data) in subtracter 36 after the 3rd shift register 33 moves to right 6 bits (bit), obtain pre-attenuation coefficient and be 0.96 dateout (output data, OUTPUT=DATA[N]-N2/2 ⁶).

By above structure and flow process, can obtain: $\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="A0113627800211.png,A0113627800241.png"\; state="\{\{state\}\}">N</figure-callout>}1=\mathrm{INPUTDATE}\&times;(1+\frac{1}{2})$ $N2=N!\&times;(1+\frac{1}{4})$ $\mathrm{OUTPUTDATE}=\mathrm{INPUTDATE}-N2\&times;\frac{1}{2^6}$ $=\mathrm{INPUTDATE}\&times;(1-\frac{15}{512})$

The pre-attenuation coefficient of data is 1-15/512.

Referring to Fig. 5, Fig. 6, gain adjustment circuit shown in the figure 224 is being realized particular factor: gain controlling (adjustment) structure and flow process when step-length 1/512, adjusting range ± (15/512).

Circuit structure mainly comprises: with array 51, first shift register 52, second shift register 53, the 3rd shift register 54, the 4th shift register 55, first adder 56, second adder 58 and multiplier 59.

Among the figure, ampADJ_b3, ampADJ_b2, ampADJ_b1, ampADJ_b0 are the logic input (LOGIC INPUT) of ride gain.

The ampADJ_sign that is connected among the figure on the multiplier (ALU) 59 is an operator of adjusting gain.When ampADJ_sign=0, in multiplier 59, carry out add operation; When ampADJ_sign=1, in multiplier 59, carry out subtraction.

Input data (INPUT DATA) with array 51 in carry out AND operation with ampADJ_b3, ampADJ_b2, ampADJ_b1, ampADJ_b0 after, obtain respectively node N1, N2, N3, N4 data (step 54, N1=DATA[N] ampADJ_b3; N2=DATA[N] ampADJ_b2; N3=DATA[N] ampADJ_b1; N4=DATA[N] ampADJ_b0); Node N2 data after first shift register 52 moves to right 1 bit (bit) with the addition in first adder 56 of node N1 data, obtain node N5 data (step 55, N5=N2/2+N1); Node N4 data after second shift register 53 moves to right 1 bit (bit) in second adder 57 with the addition of node N3 data, obtain node N6 data (step 56, N6=N4/2+N3); Node N6 data after the 3rd shift register 54 moves to right 2 bits (bit) in the 3rd adder 58 with the addition of node N5 data, obtain node N7 data (step 57, N7=N6/4+N5); Node N7 data are carried out addition or subtraction (operator of computing is by the state decision of ampADJ_sign in the multiplier) with former input data (INPUT DATA) in multiplier 59 after the 4th shift register 55 moves to right 6 bits (bit), adjusted dateout (output data obtains gaining, step 58, OUTPUT=N7/2 ⁶± DATA[N]).

By above structure and flow process, can obtain:

N1＝INPUTDATE×ampADJ_b3

N2＝INPUTDATE×ampADJ_b2

N3＝INPUTDATE×ampADJ_b1

N4＝INPUTDATE×ampADJ_b0 $N5=\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="A0113627800211.png,A0113627800241.png"\; state="\{\{state\}\}">N</figure-callout>}1+N2\&times;\frac{1}{2}$ $N6=N3+N4\&times;\frac{1}{2}$ $N7=N5+N6\&times;\frac{1}{4}$ $\mathrm{OUTPUTDATE}=\mathrm{INPUTDATE}(+/-)N7\&times;\frac{1}{64}$

Work as ampADJ_sign=0, ampADJ_b[3: 0]=1111 o'clock,

OUTPUT?DATA＝INPUT?DATA×(1+15/512)。

Referring to Fig. 7, Fig. 8 and in conjunction with referring to Fig. 2, mistake when being illustrated in the digital peak of realizing specific precision among Fig. 7,8 respectively and detecting and correct result.

Peak value detects analog-and digital-two kinds of realization technology.The accuracy of detection that simulated peak detects is generally not high, generally can not be used in the high-precision gain adjustment circuit.Can and digital peak detects, then exist sampled point reflect the problem of realistic simulation signal amplitude.

Wrong as shown in Figure 7 digital peak detects, and when the sample frequency of analog to digital converter 242 was the integral multiple of sine wave signal 25 frequencies, if in one-period, sampled point was insufficient, then can not reflect the amplitude of analog signal truly.The reason that this kind situation occurs is mainly:

(1) sine wave is periodic;

(2) sampled point of analog to digital converter also shows as in one or more sine waves periodically;

(3) number of sampled point is relevant with the precision of adjustment in the one-period.

It is wrong that digital peak shown in Figure 7 detects, this is because there are the integral multiple relation in sample frequency and sinusoidal wave frequency, the data that obtain in n and the sampling of n+1 sampled point, with behind the sine wave period, the data that obtain of pairing sampled point sampling are identical.When the data that obtain at n and n+1 sampled point were not sinusoidal wave peak-data, sampling so after this can not got sinusoidal wave peak-data yet; And when sinusoidal wave peak-data is got in sampling just, then also can get sinusoidal wave peak-data behind the one-period at n and n+1 sampled point.

Divide exactly when concerning when existing between the sine wave freuqency of the sample frequency of integral multiple and integral multiple, also similar situation can occur.

Above mistake former because: peak value can detect, but not necessarily can detect.

In order to detect sine wave signal peak value accurately, make the adjustment precision of gain reach requirement, the technology that the present invention adopts is to allow not have the relation of dividing exactly between the sine wave freuqency of the sample frequency of integral multiple and integral multiple.At this moment, in certain sampling time, as 1 second (s), the 67kHz sine wave has 67k cycle to pass through analog-to-digital conversion, owing to do not have integer relation to a certain degree between sample frequency and the sine wave freuqency, so in 67k cycle, the phase place of each sampled point all is inequality, promptly be equivalent to finish in a sine wave period over-sampling of 67 (k) * m, wherein m is half of the interior number of samples of a sine wave period.

Detect in the equivalent schematic at correct digital peak shown in Figure 8, the value of M is promptly relevant with the precision that peak value detects with the precision of gain controlling.Because sinusoidal wave amplitude all is identical in any one-period, so the sampling in the nonoverlapping M of the phase place cycle can equivalence be M sampling doubly in the one-period.

For amplitude is that A, frequency are the sine wave of f, and when sample frequency was F, the precision of setting peak value sampling was z, and the cycle M that then needs is: $z=\sin \left(2\mathrm{\&pi;f}(t+\mathrm{\&Delta;t})\right)-\sin {\left(2\mathrm{\&pi;ft}\right)}_{\sin \left(2\mathrm{\&pi;ft}\right)-1}$ $=2\mathrm{\&pi;f}\&times;\mathrm{\&Delta;t}$ $M=\frac{2\mathrm{\&pi;f}}{z\&times;F}$

Work as z=0.1%, f=67kHz, during F=1MHz, M=6.28 * 67=420, the peak value sampling time that needs is about 6.7s.When analog-to-digital conversion 242 sample frequencys were 6.5MHz, the sampling time of peak value was about 1s.

Claims (10)

1. wireless communication multichannel base band modulation circuit, comprise auxiliary circuit, to importing the digital modulation module that data are carried out digital modulation and exported the parallel multi-channel data, simulation process module with parallel multi-channel data subchannel being carried out output multi-channel analog signal after digital-to-analogue conversion, filtering and the power drive is characterized in that:

Also comprise multichannel gain control module and gain error detection module; Multichannel gain control module, described multichannel analog processing module and gain error detection module connect and compose the multichannel gain control loop; The gain error detection module carries out the channel selecting detection and calculates each channel gain adjustment coefficient the multi-channel analog signal of multichannel analog processing module output, pass to the multichannel gain control module again, carrying out after each interchannel gain-adaptive coupling control again to the parallel multi-channel data of digital modulation module output, subchannel is sent to the multichannel analog processing module; Also include the sine-wave generator and the timer that connect digital modulation module and gain error detection module respectively, in the initialization procedure of timer-operated channel gain control loop operating time, ride gain error-detecting module is carried out the gain error test and gain adjustment factor calculates.

2. a kind of wireless communication multichannel base band modulation circuit according to claim 1 is characterized in that: described multichannel gain control module is connected and composed by the accurate passage of a roadbed, the common passage in other road and a synchronous circuit; The benchmark passage is connected and composed by pre-attenuator circuit and delay circuit, and each common passage is connected and composed by pre-attenuator circuit and gain adjustment circuit; The benchmark passage is distinguished the corresponding parallel multi-channel data that connect described digital modulation module output with the pre-attenuator circuit of common passage, the delay circuit of benchmark passage is connected described synchronous circuit with the gain adjustment circuit of common passage, the parallel multi-channel data of synchronous circuit output are sent to each analog to digital conversion circuit of described simulation process module.

3. a kind of wireless communication multichannel base band modulation circuit according to claim 1 is characterized in that: described gain error detection module is linked in sequence by analog switch, analog to digital conversion circuit, digital peak testing circuit and gain error counting circuit and constitutes; Analog switch is connected with the multi-channel analog signal output of described simulation process module, and the output of gain error counting circuit connects described gain control module, and each channel gain of gain control module is carried out the self adaptation adjustment.

4. a kind of wireless communication multichannel base band modulation circuit according to claim 1, it is characterized in that: described pre-attenuator circuit is connected and composed by shift register, adder and subtracter, to the input data be shifted, addition, the operation that addition more finally subtracts each other that is shifted again, by the position of selection shift register and the figure place of displacement, realize the attenuation coefficient that requires to the input data.

5. a kind of wireless communication multichannel base band modulation circuit according to claim 1, it is characterized in that: described gain adjustment circuit by " with " array, shift register, adder and multiplier connect and compose, by " with " array carries out AND operation to each logic input of input data and ride gain respectively, again by the position of selection shift register and the figure place of displacement, to " with " operation result of array is shifted, addition, again addition result is shifted, addition, finally by multiplier under the control of adjusting the gain operator to the operation that adds deduct of input data and final addition result, realize requiring to importing the gain coefficient of data.

6. a kind of wireless communication multichannel base band modulation circuit according to claim 1 is characterized in that: described auxiliary circuit, sine-wave generator, timer, digital modulation module, multichannel gain control module, simulation process module, gain error detect mould and certainly are produced on the integrated circuit (IC) chip.

7. the multichannel gain matching control method of a radio communication base band modulation circuit is characterized in that comprising following treatment step:

A. circuit powers on and enters initial phase;

B. the digitized sine wave signal of sine-wave generator output is sent into digital modulation module as the data-signal of input and carry out digital modulation, and send the multichannel gain control module to the mode correspondence of parallel multi-channel data;

C. selecting a passage in the gain control module is the benchmark passage, the parallel signal of importing this benchmark passage enters synchronous circuit after decaying in advance, postponing, the parallel signal of other passage beyond the input reference passage also enters synchronous circuit through pre-decay, gain after adjusting, and the parallel multi-channel data-signal of synchronous circuit output send the simulation process module;

D. by a plurality of simulation process passages corresponding in the simulation process module parallel multi-channel data-signal is carried out digital-to-analogue conversion, filtering and power drive respectively, the output multi-channel analog signal send the gain error detection module simultaneously;

When E. utilizing by the analog switch of gain error detection module merotype to multichannel analog output carry out gating and analog-to-digital conversion, by the amplitude that detects respective channel the dateout of digital peak testing circuit after analog-to-digital conversion, from this amplitude information, calculate the initial phase gain coefficient that each passage need be adjusted except that the benchmark passage by the gain error counting circuit, and pass to the multichannel gain control module, to the adjustment that gains of the gain adjustment circuit of each passage except that the benchmark passage, finish each interchannel gain-adaptive control;

F. finish initial phase, locking gain error counting circuit calculates the gain coefficient that obtains, and the gain error detection module is placed off position.

8. the multichannel gain matching control method of a kind of radio communication base band modulation circuit according to claim 7 is characterized in that described steps A, further comprises:

A. in the initialization procedure that circuit powers on, earlier with in the multichannel gain control module except that the benchmark passage gain coefficient of each gain adjustment circuit be changed to default value;

B. the data input with digital modulation module switches to sinusoidal wave binary data input;

Described step e further comprises:

C. by the gain error detection module with the benchmark passage in the multichannel gain control module as the reference passage, detect and calculating benchmark passage and other interchannel gain errors, calculate the gain adjustment factor of each respective channel according to the amplitude digital quantity and the ratio of each passage amplitude digital quantity of reference channel;

D. the gain coefficient correspondence that each channel gain is adjusted circuit except that the benchmark passage in the multichannel gain control module is changed to by step c and calculates the gain adjustment factor value that obtains, when the gain error of benchmark passage and other passages is in preset range, other passages and benchmark passage coupling;

E. the data input of digital modulation module is switched to the data input of outside by the sinusoidal wave binary data input of inside.

9. the multichannel gain matching control method of a kind of radio communication base band modulation circuit according to claim 8, it is characterized in that: the sample frequency Cheng Fei of analog to digital conversion circuit is divided exactly relation in the signal frequency of described sine wave and the described gain error detection module, and quantizes to realize over-sampling by the sine wave to an above cycle of analog-digital conversion circuit as described.

10. according to the multichannel gain matching control method of claim 7 radio communication base band modulation circuit, it is characterized in that: the initial phase of described steps A and step e is adjusted required precision by a timer according to gain and is carried out length control.

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