CN1412776A - Circuit and method for improving speed and stability of sense amplifiers - Google Patents

Abstract

A circuit and method for improving the speed and stability of a sense amplifier includes a compensation current device and a discharge current device connected to a data node on one side of a transmission transistor, and a sensing node on the other side of the transmission transistor is connected to a charging current device and a leakage current device, and the leakage current is mirrored from the compensation current. The compensation current keeps the transmission transistor from being completely turned off and the data node does not exceed a certain voltage, thereby improving the speed of the sense amplifier. The leakage current improves the stability of the sense amplifier. Mirroring the leakage current from the compensation current allows the operation and performance of the sense amplifier to be well controlled.

Description

Circuit and method for improving speed and stability of sense amplifiers

Field

The present invention relates to a sense amplifier for semiconductor memory, and more particularly, to a circuit and method for improving the speed and stability of the sense amplifier.

Background technique

In a semiconductor memory, sense amplifiers are used to read data from memory cells, and the speed and stability of the sense amplifiers thus dominate memory performance. Fig. 1 shows the basic structure (architecture) of a typical semiconductor memory circuit 10, and it contains a cell array (cell array) 12 that is formed by many storage transistors (storage transistor), for the sake of brevity, it is only representatively drawn in this figure part of the storage unit. An X decoder 14 and a Y decoder 16 select specific memory cells from the row and column directions of the cell array 12 . The selection signal lines WL1, WL2, . . . , WLM from the X decoder 14 are called word lines, and the selection signal lines YS1, YS2, . . . ., YSN is called bit line. The selected memory cell is connected to the data line DL via the bit line selection transistor 18 , and read from there by the sense amplifier 20 , thus generating a data signal OUT at the output terminal of the sense amplifier 20 . Figure 2 illustrates the basic operating principle of a sense amplifier, and Figure 3 is its timing diagram. The sense amplifier 22 includes a transmission transistor (transmission transistor) MN1 separating a data node VD and a sensing node VZ. The data node VD is connected to the data line DL to provide a way to read the memory cell, and the sensing node VZ is output through an output The stage X2 sends out the data signal OUT, and the sum of the capacitances seen from the data node VD and the sense node VZ is denoted as C2 and C1. When the selected memory cell is a transistor that is turned on, it is called a low state. At this time, a cell current Icell appears on the data line DL; otherwise, when the selected memory cell is a non-conductive transistor, it is called a high state. At this time, the cell current Icell on the data line DL is zero. When the sense amplifier 22 reads a low state, the data node VD is discharged by the cell current Icell, causing the pass transistor MN1 to conduct a sense current Isense, and the voltage of the sense node VZ drops to a relatively low voltage. When the sense amplifier 22 reads a high state, the cell current Icell is zero, the sense current Isense is zero or very small, and the sense node VZ maintains a relatively high voltage. When reading the low state, the transfer transistor MN1 will cause a time delay from being off to on, resulting in a low sensing speed, and, due to the feedback effect of the voltage on the data node VD on the transfer transistor MN1, the transfer transistor MN1 is turned on The speed is even slower. However, when reading the high state, the transfer transistor MN1 may be improperly turned on due to noise, thus generating an unstable operation. In addition, the data node VD may be overcharged to a relatively high voltage after repeated read cycles, which will cause the pass transistor MN1 to be turned on more slowly, resulting in a slower sensing speed.

To increase the stability of the sense amplifier, a conventional technique is to charge the sense node VZ additionally, as shown in FIG. A bias voltage BIAS is provided to generate a leakage current (leakage current) Ileakage, which is supplied to the sensing node VZ, thereby obtaining better stability.

As shown in FIG. 6, another conventional technology adds a discharge current device MN3 in the sense amplifier 26 to connect the data node VD through a switch MN2. The timing diagram is shown in FIG. The data node VD is discharged to speed up the pass transistor MN1 being turned on.

The improved sense amplifier of Smarandoiu et al. in US Pat. No. 5,390,147 adds a lubrication current mirror to connect the data node and the reference node, and utilizes the feedback of the reference current mirror to improve the speed of the sense amplifier. However, such an arrangement makes the lubricating current and the reference current affect the sensing current through the feedback path. When non-ideal conditions occur, such as variations in the manufacturing process that cause changes in the reference current, the sensing current will change, and thus the sensing speed will occur. become slower, or even cause errors in sensing results. Therefore, further improvements are required for sense amplifiers.

Contents of the invention

The object of the present invention is to provide an improved sense amplifier to enhance its sensing speed and stability, which is to connect an offset current apparatus (offset current apparatus) to the data node on one side of the transfer transistor, and to make the transfer through the offset current The transistor is not completely turned off and the data node does not exceed a certain voltage, thereby increasing the speed of the sense amplifier; while the sense node on the other side of the pass transistor is connected to a leakage device to improve the stability of the sense amplifier. The operation and performance of the sense amplifier is well controlled by using a current mirror to generate leakage current from the compensation current mirror. The data node is also connected to a discharge current device to offset the leakage current introduced into the pass transistor.

The circuit of the present invention is implemented as follows: a circuit for increasing the speed and stability of a sense amplifier comprising a pass transistor having an input and an output coupled to a sensing node, the input The terminal couples a data node to connect a data line, senses the storage state of a memory unit, and sends a data signal from the sensing node through an output stage, and is characterized in that: the circuit includes: a first current mirror, including a first One and the second branch, for mirroring an intermediary current from the first branch, a compensating current device is inserted between the first branch and the data node in the second branch, controlled by the first control signal to conduct a compensation current; a second current mirror having third and fourth branches coupled to the sensing node, the third branch adapting the intermediate current to mirror a leakage current at the fourth branch; and a charging current The device is coupled to the sensing node, and is controlled by the inverting input of the second control signal to conduct a charging current.

Wherein the first control signal is a power supply voltage.

Wherein the first current mirror has a mirror ratio of 1:1 to 3:4.

Wherein the second current mirror has a mirror ratio of 1:1.

The ratio of the compensation current to the leakage current is 1:1 to 3:4.

It further includes a discharge current device inserted between the data node and the first branch of the first current mirror, and controlled by a third control signal to conduct a discharge current.

Wherein the third control signal is the complement of the second control signal.

Wherein the ratio of the charging current to the discharging current is 5:1 to 10:1.

It further includes an intermediate transistor having a common gate with the transfer transistor, and its source and drain are respectively connected to the second branch of the first current mirror and the third branch of the second current mirror.

The circuit of the present invention can also be implemented as follows: a circuit for improving the speed and stability of a sense amplifier comprising a pass transistor having a source and a drain, the drain serving as a sensing node, The source is used as a data node to connect a data line to sense the storage state of a storage unit, and a storage signal is sent from the sensing node through an output stage, wherein the circuit includes: a first transistor with A source, a drain and a gate, the drain is connected to the data node, the gate is connected to a bias signal; the first current mirror composed of the second and third transistors, each of the second and third transistors It has a source, a drain and a gate, the two sources are grounded, the two gates are connected to each other, the drain of the second transistor is connected to its gate and the source of the first transistor; the fourth The transistor has a source, a drain and a gate, the source is connected to the drain of the third transistor, and the gate is connected to the gate of the transmission transistor; the second current mirror composed of the fifth and sixth transistors , the fifth and sixth transistors each have a source, a drain and a gate, the two sources are connected to a power supply voltage, the two gates are connected to each other, the drain of the fifth transistor is connected to its gate pole and the drain of the fourth transistor, the drain of the sixth transistor is connected to the sensing node; and the seventh transistor has a source, a drain and a gate, the source is connected to the power supply voltage, and the drain The pole is connected to the sensing node, and the gate is connected to an inverting input of a complementary signal of a precharge signal.

Wherein the size ratio of the second transistor and the third transistor is 1:1 to 3:1.

Wherein the size ratio of the fifth transistor and the sixth transistor is 1:1.

Wherein the current ratio of the conduction of the second transistor and the sixth transistor is 1:1 to 3:1.

It further includes an eighth transistor having a source, a drain and a gate, the drain is connected to the data node, and the gate is connected to the precharge signal.

Wherein the current ratio of the conduction of the seventh transistor and the sixth transistor is 5:1 to 10:1.

The method of the present invention is achieved as follows: a method of increasing the speed and stability of a sense amplifier comprising a pass transistor having an input terminal and an output terminal, the output terminal is coupled to a sensing node, the input terminal The terminal couples a data node to connect a data line, senses the storage state of a memory cell, and sends a data signal from the sensing node through an output stage, and is characterized in that: the method includes the following steps: coupling a compensation current to the data node to maintain the pass transistor is not completely turned off and the data node does not exceed a certain voltage; mirror the compensation current to generate a leakage current coupled to the sensing node; and couple a charging current to the sensing node.

It further includes applying a bias voltage to control the compensation current.

It further includes applying a complementary signal to a precharge signal to control the charging current.

Wherein the ratio of compensation current to leakage current is 1:1 to 3:4.

It further includes coupling a discharge current to the data node.

It further includes applying a pre-charge signal to control the discharge current.

Wherein the charge current to discharge current ratio is 5:1 to 10:1.

It further includes coupling an intermediary transistor with a common gate of the pass transistor to turn on or turn off the path for mirroring the compensation current and the discharge current.

Description of drawings

FIG. 1 is a basic structural diagram of a typical semiconductor memory circuit;

Fig. 2 is a circuit diagram of the sense amplifier in Fig. 1;

Fig. 3 is a timing diagram of the circuit in Fig. 2;

FIG. 4 is an improved circuit of a conventional sense amplifier with improved stability;

Fig. 5 is a timing diagram of the circuit in Fig. 4;

FIG. 6 is an improved circuit of a conventional sense amplifier with increased speed;

Figure 7 is a timing diagram of the circuit in Figure 6;

Fig. 8 is a preferred embodiment circuit diagram of the present invention;

FIG. 9 is a timing diagram of the circuit in FIG. 8 .

Detailed ways

FIG. 8 shows a sense amplifier circuit according to a preferred embodiment of the present invention, and its timing diagram is shown in FIG. 9 . Like conventional sense amplifiers, the sense amplifier 28 shown here includes a pass transistor MN1 having a source as an input connected to a data node VD to connect to the data line DL from the memory cell, a drain As the output terminal, it is connected to a sensing node VZ, and a gate is used as a control terminal, connected to the node VX, and the complementary signal SEB of the sensing enable signal and the signal of the data node VD pass through the NOR gate X1 to generate a control signal to the node VX , to manipulate pass transistor MN1. When the transfer transistor MN1 is turned on, the storage state of the cell is sensed by the cell current Icell flowing on the data line DL, and a corresponding voltage is generated on the sensing node VZ, and a storage signal OUT is sent out through the inverter X2.

As in the conventional art, the sense amplifier 28 also contains a charging current device to improve the speed, as shown in FIG. 8, a transistor MP1 has a source connected to a supply voltage VDD, a drain connected to the sense node VZ, and A gate is connected to an inverting input of a complementary signal PREB of a precharge signal. When the transistor MP1 is turned on by the signal PREB, a charging current Icharge is supplied to the sensing node VZ and the data node VD to complete the preparation for sensing and shorten the sensing time.

In order to further improve the sensing speed, an offset current device is connected to the data node VD, as shown in the figure, a transistor MN4 has a drain connected to the data node VD, and a gate connected to a power supply voltage VDD, thereby generating a compensation current Ioffset , the magnitude of the compensation current Ioffset is about 4 μA to 6 μA to keep the transfer transistor MN1 not completely turned off, and keep the voltage of the data node VD not exceeding a specific voltage, thus increasing the sensing speed. Different from the conventional technology described above, this compensation current Ioffset is independently controlled by the transfer transistor MN1, and has nothing to do with the storage reference unit or the reference current, so it is not affected by other factors, and the compensation current Ioffset is determined by the size of the transistor MN4 And its gate bias decision, for the circuit designer, this characteristic can be selected individually.

A pair of current mirrors is used to reference the compensation current Ioffset to generate leakage current to supply to the sensing node VZ, and the pair of current mirrors includes a master current mirror and a slave current mirror. The main current mirror is composed of transistors MN3 and MN5, the gates of which are connected to each other and the drain of transistor MN3, and the sources of both are grounded. The input terminal of the main current mirror, that is, the drain of the transistor MN3 is connected to the source of the transistor MN4 to receive the compensation current Ioffset. Due to the reflection of the main current mirror, the transistor MN5 conducts a current Iml, and the ratio of the compensation current Ioffset to the mirror current Iml is determined by the size ratio of the transistors MN3 and MN5. In this embodiment, its value is about 1 ratio. 1 to 3 to 4. On the other hand, the slave current mirror is composed of transistors MP3 and MP2, their sources are connected to the power supply voltage VDD, their gates are connected to each other, and connected to the drain of transistor MP3, and the drain of transistor MP2 is connected to the sensing node VZ. A transistor MN6 is inserted between the main current mirror and the slave current mirror, which has a common gate with the transfer transistor MN1, its source is connected to the output terminal of the master current mirror, that is, the drain of the transistor MN5, and its drain is connected to the slave current mirror The input terminal, that is, the drain of transistor MP3. When the transistor MN6 is turned on, since the transistor MN5 conducts a current Iml, the transistor MP3 also conducts a current Iml, and due to the reflection from the current mirror, a leakage current Ileakage is mirrored in the transistor MP2 and supplied to the sensing node VZ , and the ratio of the current Iml to the mirrored leakage current Ileakaget is determined by the size ratio of the transistors MP3 and MP2, and in this embodiment, its value is about 1:1. On the contrary, once the transistor MN6 is turned off, the master current mirror and the slave current mirror will lose the above functions. The continuous charging of the sensing node VZ by the leakage current Ileakage can resist the noise in the circuit, that is, improve the stability of the sense amplifier 28 . The magnitude of the leakage current Ileakage will determine the ability of the sensing node VZ to resist noise. Since the main current mirror and the slave current mirror have a corresponding relationship through the current Iml, there is a proportional relationship between the leakage current Ileakage and the compensation current Ioffset, and the ratio is determined by the size ratio of the transistors MN3 and MN5 and the transistors MP3 and MP2 In this embodiment, the ratio of the compensation current Ioffset to the leakage current Ileakage is about 1:1 to 3:4. Different from the conventional technology described above, the sense amplifier 28 utilizes the leakage current Ileakage to increase the stability, and the leakage current Ileakage is mirrored from the compensation current Ioffset, so the magnitude of the leakage current Ileakage is related to the magnitude of the compensation current Ioffset It has a certain proportional relationship, which can provide the most suitable conditions for the actual circuit, and is not affected by other factors, such as the manufacturing process.

The data node VD is additionally connected to a discharge current device, that is, the transistor MN2, whose source is connected to the input terminal of the main current mirror, that is, the drain of the transistor MN3, and whose gate is connected to the precharge signal PRE. When the transistor MN2 is turned on by the signal PRE, it conducts a discharge current Idischarge whose magnitude is equivalent to the leakage current Ileakage to cancel each other.

When sensing a low state, that is, a turned-on memory cell, a cell current Icell flows from the data node VD toward the selected memory cell on the data line DL. At this time, the data node VD is discharged by the current Icell, so the transfer transistor MN1 A sensing current Isense is induced on the sensing node VZ, and a relatively low voltage is generated on the sensing node VZ. Conversely, when sensing a high state, that is, a non-conductive memory cell, the current Icell flowing from the data node VD to the memory cell is zero, and the sensing node VZ will maintain a relatively high voltage at this time. A small amount of noise current remains in the memory cell or the data line DL, and the transistor MP2 will provide a leakage current Ileakage to offset the influence, which can improve the stability and anti-noise capability of the sense amplifier.

When the data node VD is charged, due to the existence of the compensation current Ioffset, the data node VD will not be overcharged, so the voltage on the data node VD will be maintained below a certain voltage, that is, the drain-source of the transistor MN4 The sum of the voltage difference VDS and the gate-source voltage difference VGS of the transistor MN3 is about 1.0 volts, so that the sensing speed in the next read cycle will not be slowed down. Even if there is no current flowing on the data line DL, the offset current Ioffset still keeps the transfer transistor MN1 from being completely turned off, and in the next read cycle, the sensing speed will be improved due to the faster turn-on speed of the transfer transistor MN1 .

In a sensing period, as shown in FIG. 9, during its pre-charging period, the transistor MP1 of the charging current device is turned on by the signal PREB, conducts a charging current Icharge, charges the sensing node VZ and the data node VD, and discharges The transistor MN2 of the current device is turned on by the signal PRE, conducts a discharge current Idischarge, and discharges the data node VD, so as to prevent the charging current Icharge from overcharging the data node VD instantaneously. After the pre-charging period, the data node VD, that is, the voltage on the data line DL gradually drops. When it drops to a certain voltage, the control signal VX generated by the NOR gate X1 will rise, causing the voltage of the sensing node VZ to drop rapidly. , thus generating the data signal OUT.

Claims (23)

1. A circuit for improving the speed and stability of a sense amplifier comprising a pass transistor having an input and an output, the output coupled to a sense node, the input coupled to a data node to connect A data line, which senses the storage state of a memory cell, and sends a data signal from the sensing node through an output stage, and is characterized in that the circuit includes: a first current mirror, including first and second branches, and Mirror an intermediate current from the first branch to the second branch, insert a compensation current device between the first branch and the data node, and conduct a compensation current under the control of the first control signal; the second current mirror , comprising third and fourth branches, the fourth branch coupled to the sensing node, the third branch adapting the intermediate current to mirror a leakage current at the fourth branch; and a charging current device coupled to the sensing node, And controlled by the inverting input of the second control signal to conduct a charging current. 2. The circuit for improving the speed and stability of the sense amplifier as claimed in claim 1, wherein the first control signal is a power supply voltage. 3. The circuit for improving the speed and stability of the sense amplifier as claimed in claim 1, wherein the first current mirror has a mirror ratio of 1:1 to 3:4. 4. The circuit for improving the speed and stability of the sense amplifier as claimed in claim 1, wherein the second current mirror has a mirror ratio of 1:1. 5. The circuit for improving the speed and stability of a sense amplifier as claimed in claim 1, wherein the ratio of the compensation current to the leakage current is 1:1 to 3:4. 6. The circuit for improving the speed and stability of the sense amplifier according to claim 1, further comprising a discharge current device inserted between the data node and the first branch of the first current mirror, and controlled Conducting a discharge current according to the third control signal. 7. The circuit for improving the speed and stability of a sense amplifier as claimed in claim 6, wherein the third control signal is the complement of the second control signal. 8. The circuit for improving the speed and stability of a sense amplifier as claimed in claim 6, wherein the ratio of the charging current to the discharging current is 5:1 to 10:1. 9. The circuit for improving the speed and stability of the sense amplifier according to claim 1, further comprising an intermediate transistor having a common gate with the transfer transistor, and its source and drain are respectively connected to the first current The second branch of the mirror is connected to the third branch of the second current mirror. 10. A circuit for improving the speed and stability of a sense amplifier comprising a pass transistor having a source and a drain, the drain serving as a sense node and the source serving as a data node connected to A data line, which senses the storage state of a storage unit, and sends a storage signal from the sensing node through an output stage, and is characterized in that the circuit includes: a first transistor with a source, a drain and a gate, the drain is connected to the data node, and the gate is connected to a bias signal; the first current mirror composed of the second and third transistors, the second and third transistors each have a source, a drain and A gate, the two sources are grounded, the two gates are connected to each other, the drain of the second transistor is connected to the gate and the source of the first transistor; the fourth transistor has a source, a drain pole and a gate, the source is connected to the drain of the third transistor, and the gate is connected to the gate of the transfer transistor; the second current mirror composed of the fifth and sixth transistors, the fifth and sixth transistors are respectively It has a source, a drain and a gate, the two sources are connected to a power supply voltage, the two gates are connected to each other, the drain of the fifth transistor is connected to its gate and the drain of the fourth transistor , the drain of the sixth transistor is connected to the sensing node; and the seventh transistor has a source, a drain and a gate, the source is connected to the power supply voltage, the drain is connected to the sensing node, and the gate The pole is connected to the inverting input of the complementary signal of a precharge signal. 11. The circuit for improving the speed and stability of a sense amplifier as claimed in claim 10, wherein the size ratio of the second and third transistors is 1:1 to 3:1. 12. The circuit for improving the speed and stability of the sense amplifier as claimed in claim 10, wherein the size ratio of the fifth and sixth transistors is 1:1. 13. The circuit for improving the speed and stability of the sense amplifier as claimed in claim 10, wherein the current ratio of the second and sixth transistors being turned on is 1:1 to 3:1. 14. The circuit for improving the speed and stability of a sense amplifier according to claim 10, further comprising an eighth transistor having a source, a drain and a gate, the drain being connected to the data node , the gate is connected to the precharge signal. 15. The circuit for improving the speed and stability of the sense amplifier as claimed in claim 14, wherein the current ratio of the seventh and sixth transistors being turned on is 5:1 to 10:1. 16. A method of increasing the speed and stability of a sense amplifier comprising a pass transistor having an input and an output, the output coupled to a sense node, the input coupled to a data node to connect A data line for sensing the storage state of a memory cell, and sending a data signal from the sensing node through an output stage, characterized in that: the method includes the following steps: coupling a compensation current to the data node to maintain the The pass transistor is not fully turned off and the data node does not exceed a certain voltage; mirroring the compensation current to generate a leakage current coupled to the sensing node; and coupling a charging current to the sensing node. 17. The method for improving the speed and stability of a sense amplifier as claimed in claim 16, further comprising applying a bias voltage to control the compensation current. 18. The method of improving the speed and stability of a sense amplifier as claimed in claim 16, further comprising applying a complementary signal to a precharge signal to control the charging current. 19. The method for improving the speed and stability of a sense amplifier as claimed in claim 16, wherein the compensation current-to-leakage current ratio is 1:1 to 3:4. 20. The method for improving the speed and stability of a sense amplifier as claimed in claim 16, further comprising coupling a discharge current to the data node. 21. The method for improving the speed and stability of a sense amplifier as claimed in claim 20, further comprising applying a precharge signal to control the discharge current. 22. The method for improving the speed and stability of a sense amplifier as claimed in claim 20, wherein the charge current to discharge current ratio is 5:1 to 10:1. 23. The method for improving the speed and stability of a sense amplifier according to claim 16, further comprising: coupling an intermediate transistor with a common gate of the pass transistor to enable or disable mirroring of the compensation current and the discharge current path of.

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