CN1385710A - Event tester structure for mixed signal test - Google Patents
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Abstract
There is a kind of semiconductor testing system used to test the semiconductor devices, and it is specially a kind of semiconductor testing system having multiple type-different testing modules and uses to high-speedily and high-effectively test the signal-mixed integrated circuit. The semiconductor testing system of the invention includes two or more capability-different testing modules, a testing head which can hold two or more capability-different testing modules, the equipment placed on the testing head and used to connect the tester module and the measured device, a selectable circuit corresponding to the measured device when the measured device is a signal-mixed integrated circuit having the analog and digital function, and a host computer which is linked with the tester module by the tester bus to control the whole running of the testing system.
Description
The present invention relates to a kind of semiconductor test system, be used for the measuring semiconductor integrated circuit, as large scale integrated circuit (LSI), more particularly, relate to a kind of semiconductor test system, can at full speed reach high-level efficiency test mixing signal integrated circuit with event tester structure.Therefore in semiconductor test system of the present invention, test macro is made of the identical or different tester module independent assortment of a plurality of performances, and the separate work of each tester module can be tested the simulating signal piece and the digital signal piece of measured device simultaneously.
The schematic block diagram of Fig. 1 represents to be used in the routine techniques semiconductor test system example of measuring semiconductor integrated circuit (below be referred to as " IC device ", " tested LSI " or " measured device " etc.).
In the example of Fig. 1, test processor 11 is application specific processors that are arranged in this semiconductor test system, and it is by the operation of a tester bus TB control test macro.According to the mode data of test processor 11, a mode generator 12 is respectively timing sequencer 13 and waveform format device 14 provides time series data and Wave data.Waveform format device 14 adopts the Wave data of mode generator 12 and the time series data of timing sequencer to produce a test pattern, and this test pattern is provided for measured device (DUT) 19 by driver 15.
According to a predetermined threshold value voltage level, analog comparator 16 converts DUT 19 response signals that provide, that caused by this test pattern to logical signal.Logic comparator 17 compares the expectation value data of this logical signal and mode generator 12.This logic comparative result is stored in the fault memorizer 18 corresponding to the address of this DUT 19.The switch (not shown) that driver 15, analog comparator 16 and being used to changes the measured device pin all is arranged on pin electronic circuit 20.
In this semiconductor test system, each test pin has all disposed the foregoing circuit structure.Therefore, because the large-scale semiconductive test macro has a large amount of test pin, do not wait as from 256 to 1048 test pin, circuit structure equal number, as shown in Figure 1 is combined, and actual semiconductor test system has become a very big system.Shown in Figure 2 is the outward appearance example of this semiconductor test system.This semiconductor test system mainly is made up of main frame 22, measuring head 24 and workstation 26.
For example, workstation 26 is computing machines, disposes graphical user interface (GUT), and its function is as the interface between this test macro and the user.The execution of the operation of this test macro, the generation of test procedure and test procedure all is to be implemented by workstation 26.Main frame 22 comprises a large amount of test channel (pin), is provided with as shown in Figure 1 test processor 11, mode generator 12, timing sequencer 13, waveform format device 14 and comparer 17 in each passage.
Measuring head 24 comprises a large amount of printed circuit board (PCB)s, and each circuit board is provided with pin electronic circuit 20, sees Fig. 1.For example, measuring head 24 is cylindrical, and the printed circuit board (PCB) that wherein constitutes the pin electronic circuit is arranged radially.On measuring head 24, measured device 19 is inserted near the test trough in operation panel 28 centers.
Between this pin electronic circuit and operation panel 28, be provided with a pin (test) stationary installation 27, it is one and is used for the contact structure that electric signal transmits.Pin stationary installation 27 comprises a large amount of connectors, for example is used to be electrically connected the pogo pin (pogo-pin) of pin electronic circuit and operation panel.Measured device 19 is from pin electronic circuit acceptance test mode signal and produce a response output signal.
In conventional semiconductor test system,, adopt to be referred to as based on the described test data of the form in cycle for generation puts on the test pattern of measured device.In the form based on the cycle, the qualification of each variable is relevant with each test period (tester frequency) of this semiconductor test system in the test pattern.More particularly, in a certain fc-specific test FC cycle, test period (tester frequency) describes, waveform (waveform catalog, edge sequential) is described and the vector description has been done to elaborate to this test pattern.
In the design phase of measured device, in computer-aided design (CAD) (CAD) environment, by a test board, the designed result data that goes out is handled by logical simulation and is identified.Yet the design appraising datum that obtains by test board adopts the format description based on incident.In the form based on incident, each change point (incident) reference time section in the certain test modes is described, for example from " 0 " to " 1 " or from " 1 " to " 0 ".For example, the definition of time period is the absolute time length that adopts since a predetermined reference point, or the relative time length between two proximal events.
At U.S. Patent application the 09/340th, in No. 371 files, the present inventor discloses the comparison between two kinds of test patterns, and a kind of is to adopt the test pattern based on the test data of cycle form to constitute, and another kind is to adopt the test pattern based on the test data of event format to constitute.The present invention's inventor has also proposed a kind of test macro based on incident, as a kind of new ideas system in the semiconductor test system.In No. 09/406300 file of U.S. Patent application of the common assignee that belongs to this invention, provided detailed description for the structure and the operation of this test macro based on incident.
As mentioned above, semiconductor test system is provided with a large amount of printed circuit board (PCB)s and similar device, and its quantity is equal to or greater than the quantity of test pin, and its result forms a system that integral body is huge.In conventional semiconductor test system, printed circuit board (PCB) and similar device all are mutually the same.
For example, be that 500MHz, time sequence precision are in the high speed and high resolving power test macro of 80 psecs at test frequency, printed circuit board (PCB) all has same strong performance for all test pin, and each pin can both satisfy this test frequency and timing resolution.Therefore, Chang Gui semiconductor test system becomes the very expensive system of a cost inevitably.And owing to adopt identical circuit structure in each test pin, the test-types that this test macro can be implemented is limited.
For example, tested device comprises a kind of semiconductor devices with analog functuion and digital function.A typical example is exactly audio frequency IC or communication device IC, comprises modulus (AD) converter, digital-to-analogue (DA) converter and digital signal processing circuit etc.In the semiconductor test system of routine, once can only carry out a kind of functional test.So, in order to test above-mentioned composite signal integrated circuits, must test each functional block respectively in a sequential manner, for example, the test AD converter is then tested the DA converter, then the test of digital signal treatment circuit earlier.
Even almost regular such situation arranged, when test only is provided with the device of logical circuit, be not the peak performance that all test pin of this measured device do not need semiconductor test system.For example, to be tested is a typical logic LSI device, this device has a hundreds of test pin, in the actual test, have only several test pin to be in high speed operation state and need high speed test signal, other hundreds ofs test pin then is operated in quite low speed, and needs is low-speed test signal.Recently Kai Fa system-on-a-chip (system-on-chip) also is that so it is a kind of semiconductor devices that receives much concern.Therefore, system-on-a-chip (SOC) has only the minority pin need use the high speed test signal, and just enough with low-speed test signal for other pin.
Because conventional semiconductor test system can not walk abreast simultaneously and carry out dissimilar tests, its defective is that in order to finish the test of mixed signal devices, it needs the long test duration.And just the required high-performance of minority pin of measured device but disposes to all test pin, and the result causes the cost of this test macro very high.
Why conventional semiconductor test system is provided with identical circuit structure in aforesaid all test pin, the result makes it can not be by being provided with different circuit structures carrying out two or more dissimilar tests simultaneously, and one of its reason is that the configuration of this system is to adopt the test data based on the cycle to produce test pattern.Employing produces test pattern based on the principle in cycle, and it is complicated that its software and hardware all is tending towards, and therefore, comprise different circuit structures and relevant software in this test macro, is practically impossible, and can make test macro complicated more like this.
For more clearly explaining above-mentioned reason, according to waveform shown in Figure 3, two kinds of test patterns formations are done simple comparison, and promptly a kind of is the test pattern formation that adopts based on the test data of cycle form, and another kind is the test pattern formation that adopts based on the test data of event format.Relatively be disclosed in more detail in the above-mentioned U.S. Patent application, this application belongs to the assignee identical with the present invention.
Shown in the example of Fig. 3, wherein, the generation of test pattern is according to the resulting data of implementing in the design phase of this integrated circuit of logical simulation.This result data is stored in the dump file (dump file) 37, this dump file 37 is output as the data based on the form of incident, represent the variation in the input and output of designed LSI (large scale integrated circuit) device, and has an explanation 38 shown in Fig. 3 lower right, for example, be used to represent waveform 31.
In this example, suppose that this waveform 31 has illustrated the test pattern that results from pin (tester pin or test channel) Sa and Sb respectively by adopting the test pattern of this explanation formation shown in waveform 31.The event data of describing this waveform is made up of set edge San, Sbn and sequential thereof the time period of a reference point (for example, since), reset edge Ran, Rbn and sequential thereof.
In the conventional semiconductor test system of basis based on the cycle principle, for producing used test pattern, test data must be divided into test period (tester frequency), waveform (type of waveform and edge sequential thereof) and vector.The example of this description is as among Fig. 3 and shown in the left part.In the test pattern based on the cycle, shown in the waveform 33 of the left part of Fig. 3, test pattern is divided into waveform and the sequential (time-delay) of each test period (TS1, TS2 and TS3) to describe each test period in detail.
For the example of the data declaration of this waveform, sequential and test period referring to shown in the time series data (test plan) 36.The example of the logical one of waveform, " 0 " or " Z " is shown in vector data (mode data) 35.For example, in time series data 36, test period is described by " frequency ", to define the time interval between test period; Waveform is described by RZ (making zero), NRZ (not making zero) and XOR (XOR).In addition, the sequential of each waveform is by the time-delay along beginning limits from one of corresponding test period predetermined sides.
As indicated above, because conventional semiconductor test system produces test pattern in the process based on the cycle, it is complicated that hardware configuration in mode generator, timing sequencer and the waveform format device is tending towards, and correspondingly, used software also becomes complicated in such hardware.In addition, owing to all test pin (for example Sa in above example and Sb) were limited by common test period, thereby the impossible test pattern that in each test pin, produces different cycles simultaneously.
Therefore, in the semiconductor test system of routine, same circuit structure is used to all test pin, can not make up the printed circuit board (PCB) of different circuit structures therein, as a result, can not carry out different tests with parallel mode simultaneously, for example simulated block test and digital block test; And for example, the high-speed type test macro also needs to comprise low speed hardware configuration (for example high voltage and large amplitude generation circuit and driver cut-off circuit, or the like), and therefore, in such test macro, high speed performance can not get sufficient improvement.
On the contrary, for by adopting the method based on incident to produce test pattern, only need read the set/reset data and relevant time series data that are stored in the event memory, required hardware and software structure is very simple.And whether each test pin can have any incident and work independently according to it, rather than according to test period; Therefore, can produce the test pattern of difference in functionality and frequency range simultaneously.
As mentioned above, the inventor of this invention has proposed the semiconductor test system based on incident.In this test macro,, a kind of total test macro that wherein has the different soft and hard part might be proposed because the hardware and software that is comprised is all very simple on structure and content based on incident.And, because each test pin can separate work, also just can be simultaneously carry out two or more function differences, test that frequency range is different in the mode that walks abreast.
Therefore, the purpose of this invention is to provide a kind of semiconductor test system, this system has the different tester module of performance and corresponding with test pin, therefore, it can the test mixing signal device by simultaneously analog functuion and digital function being carried out concurrent testing.
Another object of the present invention provides a kind of semiconductor test system, the tester module of different pin numbers, different performance wherein can freely be installed in tester main frame (or measuring head), and these tester modules are standardized with the specification that is connected between this tester main frame.
Another purpose of the present invention provides a kind of semiconductor test system, and it can freely hold the tester module of a plurality of different performances, and therefore, it is a plurality of different types of measured devices of concurrent testing or functional block simultaneously.
Another purpose of the present invention provides a kind of semiconductor test system, and it can freely hold the different tester module of a plurality of performances, thereby can set up a test macro with enough test performances with low cost, and then can improve its performance in the future.
Semiconductor test system of the present invention comprises the tester module that two or more performances are different; A measuring head that holds the different tester module of two or more performances; Be arranged on the device that is used to be electrically connected tester module and measured device on this measuring head; When measured device is one when having the mixed-signal IC of analog functuion and digital function, one with the corresponding optional circuit of measured device; And a principal computer, link to control the overall operation of this test macro by a tester bus and tester module.One type of the performance of tester module is high speed and high timing resolution, and another kind of type is low speed and low timing resolution.
In semiconductor test system of the present invention, each tester module all comprises a plurality of event tester plates.Under the control of this principal computer, each board testei provides the corresponding pin of a test pattern to measured device, and the output signal as a result that this measured device produced is identified.
Because semiconductor test system of the present invention has modular structure, therefore can freely constitute a needed test macro according to the kind of measured device and test purpose.Therefore, when measured device is a composite signal integrated circuits (wherein existing mimic channel has digital circuit again), can test mimic channel and digital circuit with parallel mode simultaneously.When measured device is high speed logic IC, a fraction of logical circuit real work is wherein also only arranged at fast state.Therefore, when testing this high speed logic IC, minority tester pin must have high speed performance.In semiconductor test system of the present invention, the specification that is connected between this measuring head and the tester module (interface) is standardized.Therefore, any tester module with standard interface can be installed in any position of this measuring head.
As mentioned above, in semiconductor test system of the present invention, the structure based on incident is adopted in the configuration of tester module (board testei), wherein, carries out all required information of test and all prepares with the form based on incident.Therefore, the frequency signal of the expression of in routine techniques, being adopted initial sequential of each test period or with the mode generator of this frequency signal synchronised work be necessary no longer just.Owing to needn't comprise this frequency signal or mode generator, can both be independent of other test pin based on each test pin in the test macro of incident and carry out work.Thereby, can carry out dissimilar tests simultaneously, such as analog circuit test and digital circuit test.
In addition,, should just can greatly reduce, and the software that is used to control the tester module also can greatly be simplified based on test system hardware of incident owing to adopted structure based on incident.Correspondingly, this total physical size based on the test macro of incident just can reduce, thereby further reduces cost, reduces shared space and save relevant cost.
In addition, in semiconductor test system of the present invention, in electric design automation (EDA) environment, the logic simulation data in design phase of this device can be directly used in the generation test pattern, to test this device at validation phase.Therefore, can shorten the work period between from the designs to the device, identifying greatly, thereby further reduce testing cost, improve testing efficiency simultaneously.
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Fig. 1 is the basic structure block scheme of a kind of semiconductor test system (LSI tester) in the routine techniques;
Fig. 2 is the synoptic diagram of the outward appearance example of a kind of semiconductor test system in the routine techniques;
Fig. 3 is the chart that is used for two examples of comparison, and one of them example is the explanation that produces in the conventional semiconductor test system based on the test pattern in cycle, and another example is the explanation that produces in semiconductor test system of the present invention based on the test pattern of incident;
Block scheme shown in Figure 4 represents to adopt the test system structure example of semiconductor test system test mixing signal IC of the present invention (composite signal integrated circuits);
Fig. 5 is the block scheme of a circuit structure example in the event tester, and this event tester is arranged in the event tester plate, and this event tester plate is combined in according in the tester module of the present invention;
Fig. 6 sets up the synoptic diagram of a semiconductor test system by making up a plurality of tester module of the present invention, and this test macro has the test pin that is divided into different performance;
Fig. 7 is the block scheme of a tester module example, and this tester module comprises a plurality of event tester plates that are used for semiconductor test system of the present invention;
Synoptic diagram shown in Figure 8 is represented the inner structure of a mixed-signal IC, and this mixed-signal IC has analog functuion and digital function, and represents employing semiconductor test system of the present invention is tested the difference in functionality in this mixed signal devices with parallel mode principle;
Fig. 9 A is the test process synoptic diagram that adopts conventional semiconductor test system test mixing signal device, and Fig. 9 B is the test process synoptic diagram that adopts semiconductor test system test mixing signal device of the present invention;
Figure 10 is the outward appearance example schematic diagram of a semiconductor test system of the present invention.
With reference to Fig. 4 to Figure 10 embodiments of the invention are described.Fig. 4 is the basic structure block scheme of semiconductor test system of the present invention, and this test macro is used for test simulation/digital mixing signal integrated circuit (mixed-signal IC).In semiconductor test system of the present invention, a set measuring head (tester main frame) is used for selectively installing therein one or more modular testers (hereinafter claiming " tester module ").The tester module of being installed can be a plurality of and the corresponding same test device of tester pin number module, or the combination of different tester modules, such as high-speed module HSM and low-speed module LSM.
As after a while will be the same with the explanation that Fig. 7 is done to Fig. 6, each tester block configuration has a plurality of event tester plates 43, such as eight board testeis are arranged.In addition, each event tester plate comprises that a plurality of event testers 66 are corresponding with a plurality of tester pins, such as corresponding 32 the tester pins of 32 event testers.Thereby, in the example of Fig. 4, the simulation part of event tester plate 431 processing apparatus test, and the numerical portion of other event tester plate 43 processing apparatus test.
In the test macro of Fig. 4, a plurality of board testeis 43 are all controlled by system bus 54 by a tester controller 41, and this tester controller is a principal computer of this test macro.As mentioned above, for example, eight blocks of event tester plates 43 can be installed in the tester module.Though not shown among Fig. 4, the Typical Disposition of test macro of the present invention is that two or more such tester modules are arranged, as shown in Figure 6.
In the test macro of Fig. 4, event tester plate 43 provides a test pattern (test signal) to give measured device 19, checks the response signal of measured device under this test pattern then.In order to test the analog functuion of measured device, can an optional circuit 48 be set at this test macro.This optional circuit 48 comprises, for example, and a DA converter, an AD converter and a wave filter.
For example, each event tester plate 43 comprises the interface of event tester 661-6632 53 as 32 passages, a processor 67 and a storer 68.Each event tester 66 is corresponding with a test pin, and all has identical inner structure in same board testei.In this example, event tester 66 comprises an event memory 60, event execution unit 47, a driver/comparer 61 and a test result storer 57.
The block scheme of Fig. 5 shows the topology example of the event tester 66 in the event tester plate 43 in greater detail.In the file of above-mentioned Application No. 09/406,300 and Application No. 09/259,401, done more detailed description for test macro based on incident, these two patented claims belong to the common assignee of this invention.In Fig. 5, the square frame identical with square frame among Fig. 4 represented with identical reference number.
For example, processor 67 is set in each event tester plate, and the operation in the control event board testei, comprises the generation of incident (test pattern), to the evaluation of measured device output signal and the collection of fault data.This processor 67 can be set on each board testei or whenever on several board testeis.In addition, processor 67 always is not necessary to be arranged in this event tester plate, but can be directly to the firm and hard existing identical control function of this event tester by tester controller 41.
For example, under the simplest situation, address control unit 58 is programmable counters, and these address control unit 58 controls are transferred into the address of fault data storer 57 and event memory 60.These event-order serie data are as a test procedure, are transferred into event memory 60 and are stored in wherein from principal computer.
The aforesaid event-order serie data of this event memory 60 storages, this data definition each sequential in this incident (from " 1 " to " 0 " and the point of the change from " 0 " to " 1 ").For example, the event-order serie data are stored as two kinds of data, a kind of integral multiple of representing the reference clock cycle, and the part in another kind of expression reference clock cycle.Preferably, these event-order serie data were compressed earlier before being stored in event memory 60.
In the example of Fig. 5, the event execution unit 47 among Fig. 4 is provided with a decompress(ion) unit 62, a sequential counting/ratio logic (timing count/scaling logic) 63 and event generator 64.The compression time series data of these 62 pairs of event memories 60 in decompress(ion) unit decompress (reproduction).This sequential counting/ratio logic 63 produces the time span data of each incident by amounting to or revising the event-order serie data.These time span data are represented the sequential of each incident by the time span of lighting from a predetermined reference (time-delay).
In the above event tester of summarizing, put on the input signal of measured device, the wanted signal of comparing with the output signal of measured device is to be produced by the data based on event format.In this form based on incident, the information of the change point on input signal and wanted signal is made up of action message (set and/or reset) and temporal information (from the time span of a specified point).
As mentioned above, in the semiconductor test system of routine, the method in the cycle that is based on of employing, the required memory capacity of this method is less than the structure desired volume based on incident.In the test macro based on the cycle, the temporal information of input signal and wanted signal is to be made of cycle information (frequency signal) and delayed data.The action message of input signal and wanted signal is to be made of Wave data and mode data.In this case, delayed data can only be limited by the data of limited quantity.And, in order to produce mode data neatly, its test procedure must comprise therein many circulations, redirect and (or) subroutine.Therefore, conventional test macro needs the complicated structure and the course of work.
In test macro based on incident, there is no need to adopt based on structure and operating process so complicated in the conventionally test system in cycle, therefore increase easily test pin quantity and (or) in identical test macro, make up the test pin of different performance.Although the test macro based on incident needs jumbo storer, the increase of sort memory capacity is not a subject matter, because now, the increase of memory density and the reduction of memory cost have all obtained promptly, constantly made progress.
As mentioned above, in this test macro based on incident, each test pin or each group test pin can be carried out separate test job.Therefore, in the time will carrying out a plurality of different types of test, when comprising the mixed signal devices of simulating signal and digital signal in test, these different types of tests can walk abreast simultaneously and carry out.In addition, the initial and end sequential of these variety classes tests can be set up independently.
Fig. 6 is by making up the synoptic diagram of the semiconductor test macro that a plurality of tester module of the present invention makes up, and this test macro has the test pin that is divided into different performance.
For example, according to the number of pins of test fixing device 127, the type of measured device and the number of pins of measured device, measuring head 124 is provided with a plurality of tester modules.To illustrate that later on the interface between this test fixing device and the test module (connection) specification is standardized, so that make any tester module can be installed in any position in this measuring head (system host).
Test fixing device 127 comprises a large amount of elastic connectors, such as pogo pin, to realize and being electrically connected and mechanical connection of tester module and operation panel 128.Measured device 19 is inserted in the test trough on the operation panel 128, is electrically connected thereby set up with this semiconductor test system.According to the specification of measured device, the optional circuit 48 that is used for simulation test among Fig. 4 can be arranged on operation panel 128.
Each tester module is provided with the pin set of predetermined quantity.For example, high-speed module HSM installs the printed circuit board (PCB) corresponding to 128 test pin (test channel), and low-speed module LSM is equipped with the printed circuit board (PCB) corresponding to 256 test pin.List these numerals just in order to demonstrate, the test pin of other varying number also is possible.In the example of Fig. 7, the tester module is configured 256 passages as an elementary cell, and 8 blocks of event tester plates wherein have been installed.For example, every block of event tester plate comprises 32 event testers (test channel).
As mentioned above, every block of plate in the tester module is provided with event tester, and each event tester produces test pattern and is added in the respective pins of measured device by operation panel 128.The output signal of 19 pairs of these test patterns of measured device response is sent on the event tester plate in the tester module by operation panel 128, and compares with wanted signal, to determine that this measured device is qualified or fault is arranged.
Each board testei is provided with an interface (connector) 126.The setting of this connector 126 meets the standard specification of test fixing device 127.
For example, in the standard specification of test fixing device 127, the distance (pin-pitch) between the structure of connector pinout, the impedance of pin, pin and the relative position of pin all are prescribed and the measuring head that is used to expect.By on all tester modules, adopting the interface (connector) 126 that meets this standard specification, just can freely set up the test macro of the various combination of tester module.
Because structure of the present invention can be set up the test macro that has optimum performance price ratio and adapt with measured device.And, by substituting one or more test modules, the performance of test macro is improved.Therefore, can prolong this test macro total serviceable life.And, test macro of the present invention can hold a plurality of performances different test module mutually, therefore, adopts corresponding test module can directly realize the performance that this test macro is required, thereby the performance of this test macro can be easily, directly be improved.
Fig. 8 utilizes the parallel ultimate principle schematic block diagram that carries out dissimilar tests of semiconductor test system of the present invention, and measured device is the mixed signal devices 19 with analog functuion and digital function.In this example, mixed signal devices 19 comprises an AD converter circuit, logical circuit, and DA converter circuit.As mentioned above, semiconductor test system of the present invention can be independent of the test of other group to each tester pin of organizing specific quantity.Therefore, by giving each circuit of mixed signal devices each group tester pin assignment, just can test these circuit concurrently simultaneously.
Fig. 9 A is the test process synoptic diagram with conventional semiconductor test system test mixing signal device, and Fig. 9 B is the test process synoptic diagram with semiconductor test system test mixing signal device of the present invention.When with the test of conventional semiconductor test system as shown in Figure 8 have the mixed-signal IC of mimic channel and digital circuit the time, this test is carried out in a continuous manner, such as, carry out next step test again after having finished a test.Therefore, finishing required T.T. of test is the summation of all test durations shown in Fig. 9 A.
On the contrary, when adopting semiconductor test system test of the present invention mixed-signal IC shown in Figure 8, AD converter circuit, logical circuit, and the DA converter circuit can walk abreast simultaneously and test, shown in Fig. 9 B.Therefore, the present invention can greatly shorten total test duration.Because the common practice is to adopt predetermined formula to identify the test result of AD converter circuit and DA converter circuit, be defined among Fig. 9 A and the 9B computing time behind each AD and the DA circuit test.
The outward appearance example of semiconductor test system of the present invention is shown in the synoptic diagram of Figure 10.In Figure 10, for example, a principal computer (main system computing machine) 41 is the workstations with graphical user interface (GUI).The function of this principal computer is as a user interface and a controller, to control the total operation of this test macro.Principal computer 41 links to each other with the internal hardware of this test macro by system bus 54 (Fig. 4 and Fig. 5).
Conventional semiconductor test system disposes according to the principle based on the cycle, use mode generator and timing sequencer, and the present invention's the test macro based on incident does not need.Therefore, by all modular event testers are installed, might reduce the physical size of whole test system significantly in measuring head (or tester main frame) 124.
As previously mentioned, in the semiconductor test system based on incident of the present invention, each test pin can both be carried out work independently of each other.Therefore, by each group test pin being distributed to different measured devices or different tested, just can test two or more different devices or pieces simultaneously.Therefore, according to semiconductor test system of the present invention, just can the while mimic channel and the digital circuit in the test mixing signal device concurrently.
As mentioned above, in semiconductor test system of the present invention, the structure based on incident is adopted in the configuration of tester module (board testei), and wherein, all are carried out the required information of test and all prepare with the form based on incident.The frequency signal of the expression of therefore, adopting in routine techniques initial sequential of each test period or the mode generator of synchronousing working with this frequency signal are essential no longer just.Owing to needn't comprise frequency signal or mode generator, can be independent of other test pin based on each test pin in the test macro of incident and work.Therefore, can carry out dissimilar tests, for example analog circuit test and digital circuit test simultaneously.
Because semiconductor test system of the present invention has modular structure, therefore can constitute required test macro neatly according to the kind and the test purpose of measured device.In addition, should can greatly be reduced based on the test system hardware of incident, the software of test macro also can greatly be simplified simultaneously.Therefore, the tester module of different performance and function can be installed in the same test macro.And as shown in Figure 6, this total physical size based on the test macro of incident also can obviously reduce, and causes further reducing cost, reducing equipment occupation space and saves relevant cost.
In addition, in semiconductor test system of the present invention, in electric design automation (EDA) environment, the logic simulation data in design phase of this device can be directly used in the generation test pattern, to test this device at validation phase.Therefore, can shorten the work period between from the designs to the device, identifying greatly, thereby further reduce testing cost, improve testing efficiency simultaneously.
Though a preferred embodiment has been described specially at this, be understandable that, do not deviating from aim of the present invention and desired extent, within the scope of the appended claims,, may make many modifications and variations to the present invention according to above-mentioned guidance.
Claims (11)
1, a kind of semiconductor test system that is used for the test mixing signal integrated circuit comprises:
Two or more performances are different tester modules mutually;
A measuring head is used to hold the different tester module of two or more performances;
Be used to be electrically connected the device of tester module and measured device, this device is arranged on this measuring head;
When measured device is when having the composite signal integrated circuits of analog functuion piece and digital function block, with the corresponding optional circuit of measured device, and
A principal computer links by tester bus and tester module, controls the overall operation of this test macro;
Simultaneously the analog functuion piece and the digital function block of this composite signal integrated circuits of concurrent testing therefrom.
2, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 1, wherein, one type of the performance of tester module is high speed and high timing resolution, another kind of type of performance is low speed and low timing resolution.
3, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 1, the specification that is connected that wherein, be used to connect the tester module, is electrically connected tester module and the coupling arrangement of measured device is standardized.
4, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 1, wherein, the coupling arrangement that is electrically connected tester module and measured device comprises an operation panel and a test fixing device, operation panel is provided with the physical construction that measured device is installed, and test fixing device is provided with a bindiny mechanism that is electrically connected this operation panel and tester module.
5, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 1, wherein, some test pin are distributed to the tester module changeably.
6, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 1, wherein, some test pin are distributed to the tester module changeably, and the distribution of this test pin and modification thereof are adjusted by the address date from this principal computer.
7, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 1, wherein, each tester module comprises a plurality of event tester plates, wherein each event tester plate is assigned to the test pin of predetermined quantity.
8, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 7, wherein, the corresponding event tester plate of each tester module.
9, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 1, wherein, each tester module comprises an internal controller, this internal controller is according to the instruction of principal computer, control produces a test pattern by this tester module, and identifies the output signal of measured device.
10, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 7, wherein, each tester module comprises a plurality of event tester plates, wherein each event tester plate comprises an internal controller, this internal controller is according to the instruction of principal computer, control produces a test pattern by this tester module, and identifies the output signal of measured device.
11, the semiconductor test system that is used for the test mixing signal integrated circuit according to claim 1, wherein, each tester module comprises a plurality of event tester plates, and each event tester plate is assigned to a test pin, and wherein each event tester plate comprises:
One controller, according to the instruction of principal computer, control produces test pattern by this tester module, and identifies the output signal of measured device;
One event memory is used to store the time series data of each incident;
One address sequence generator under the control of this controller, is used to provide address date to this event memory;
Be used for producing the device of test pattern according to the time series data of this event memory; And
One driver/comparer is used for test pattern is sent to the corresponding pin of measured device, and receives the response output signal of measured device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01117615 CN1385710A (en) | 2001-05-11 | 2001-05-11 | Event tester structure for mixed signal test |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01117615 CN1385710A (en) | 2001-05-11 | 2001-05-11 | Event tester structure for mixed signal test |
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|---|---|
| CN1385710A true CN1385710A (en) | 2002-12-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 01117615 Pending CN1385710A (en) | 2001-05-11 | 2001-05-11 | Event tester structure for mixed signal test |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339225B (en) * | 2007-07-06 | 2010-09-29 | 京元电子股份有限公司 | Test interface with mixed signal processing device |
| TWI426367B (en) * | 2010-12-22 | 2014-02-11 | Inventec Corp | A testing device of the array pins of the gpio |
| CN103809112A (en) * | 2012-11-01 | 2014-05-21 | 辉达公司 | System, method, and computer program product for testing an integrated circuit from a command line |
| CN105242159A (en) * | 2014-07-09 | 2016-01-13 | 英飞凌科技股份有限公司 | Testing device and a circuit arrangement |
| CN106802388A (en) * | 2016-12-23 | 2017-06-06 | 北京时代民芯科技有限公司 | A kind of test module of hybrid digital-analog integrated circuit |
| CN108362994A (en) * | 2013-10-12 | 2018-08-03 | 深圳市爱德特科技有限公司 | A kind of test device based on the test separation of high low speed |
| CN113238145A (en) * | 2021-06-16 | 2021-08-10 | 无锡中微腾芯电子有限公司 | Digital-analog hybrid integrated circuit testing device and testing method |
-
2001
- 2001-05-11 CN CN 01117615 patent/CN1385710A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339225B (en) * | 2007-07-06 | 2010-09-29 | 京元电子股份有限公司 | Test interface with mixed signal processing device |
| TWI426367B (en) * | 2010-12-22 | 2014-02-11 | Inventec Corp | A testing device of the array pins of the gpio |
| CN103809112A (en) * | 2012-11-01 | 2014-05-21 | 辉达公司 | System, method, and computer program product for testing an integrated circuit from a command line |
| CN108362994A (en) * | 2013-10-12 | 2018-08-03 | 深圳市爱德特科技有限公司 | A kind of test device based on the test separation of high low speed |
| CN105242159A (en) * | 2014-07-09 | 2016-01-13 | 英飞凌科技股份有限公司 | Testing device and a circuit arrangement |
| CN106802388A (en) * | 2016-12-23 | 2017-06-06 | 北京时代民芯科技有限公司 | A kind of test module of hybrid digital-analog integrated circuit |
| CN113238145A (en) * | 2021-06-16 | 2021-08-10 | 无锡中微腾芯电子有限公司 | Digital-analog hybrid integrated circuit testing device and testing method |
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