CN1374698A - Semi-conductor apparatus and its pattern wiring method - Google Patents
Semi-conductor apparatus and its pattern wiring method Download PDFInfo
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- CN1374698A CN1374698A CN02106955A CN02106955A CN1374698A CN 1374698 A CN1374698 A CN 1374698A CN 02106955 A CN02106955 A CN 02106955A CN 02106955 A CN02106955 A CN 02106955A CN 1374698 A CN1374698 A CN 1374698A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims description 39
- 230000002093 peripheral effect Effects 0.000 claims abstract description 27
- 230000015654 memory Effects 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 description 75
- 238000009826 distribution Methods 0.000 description 23
- -1 boron ion Chemical class 0.000 description 19
- 238000002347 injection Methods 0.000 description 19
- 239000007924 injection Substances 0.000 description 19
- 239000000758 substrate Substances 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
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- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
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Abstract
The invention allows a semiconductor device for turning a driver into a single chip. The semiconductor device is applied to a drive for driving a screen display in which an anode driver, cathode driver, memory part, etc., are formed into a single chip. For example, with the anode drivers being sorted into desired output bit groups (anode drivers 10, 12, 13, and 16), the output bit groups are arranged at a peripheral part in the chip and a wiring 19, connected to the output bits in the output bit groups arranged at the peripheral part, is circulated in matching with a chip shape.
Description
Technical field
The present invention relates to semiconductor device and pattern wiring method thereof, specifically, relate to constituting and have such as anode driver and cathode drive etc. and with the display driver of their singualtion semiconductor device and pattern wiring method thereof with driver etc.
Background technology
Below, constitute the semiconductor device of above-mentioned display driver with reference to description of drawings with driver etc.
Aforementioned display device comprises LCD display, light-emitting diode display, organic EL (electroluminescence) display, inorganic EL display, PDP (plasma display), FED various flat-panel monitors such as (electroluminescent displays).
Below, illustrate and have such as anode driver and cathode drive, supply with constant current to organic EL and make the luminous organic EL display driver driver of organic EL.In addition, because EL element is a self-emission device, having in liquid crystal indicator does not need many advantages such as backlight, that field-of-view angle is unrestricted, thereby expectation can be applied to follow-on liquid crystal indicator.Particularly, compare with inorganic EL element, organic EL has the advantage of high brightness, high efficiency, high response characteristic and multicolor.
Above-mentioned organic EL display driver driver is by constituting with N-channel MOS transistor etc. such as the N-channel MOS transistor and the P channel MOS transistor of the N-channel MOS transistor of logical circuit series and P channel MOS transistor, high withstand voltage series, the N-channel MOS transistor of high withstand voltage series of realizing low on-resistanceization and P channel MOS transistor and switching levels.
Here, the MOS transistor as the high withstand voltage series that realizes low on-resistanceization for example can adopt D (dual diffusion) MOS transistor etc.In addition, the transistorized structure of above-mentioned DMOS is, relatively the diffusion layer that forms of surface of semiconductor chip one side, make the different diffusion of impurities of conductivity type and form new diffusion layer, the horizontal proliferation difference of utilizing these diffusion layers is as the long structure of effective raceway groove, by forming short channel, form the element that is suitable for low on-resistanceization.
In addition, when constituting above-mentioned organic EL display driver with various drivers such as drivers, the pattern wiring of semiconductor device is disposed repeatedly with the output number of necessity by the wiring of output 1 bit size and constitutes.
Here, when above-mentioned organic EL display driver constitutes with driver, constitute parts such as anode driver, cathode drive, memory respectively.Thereby, these parts are configured on the printed substrate, the requirement of cost and size all can't be satisfied.
Thereby, wish to realize the downsizing and the cost degradation of chip size by with part singualtion such as anode driver, cathode drive, memories.
In addition, simply various drivers are disposed repeatedly with the output number of necessity and in the structure that forms, the space of guiding distribution becomes necessary, causes chip size to increase.
That is, Figure 14 (a) is that expression constitutes the plane graph of display driver with the pattern wiring of the semiconductor device of driver, as mentioned above, is disposed repeatedly with the output number of necessity and is constituted by the wiring of output 1 bit size.
Here, among Figure 14 (a), 1 is the output area of suitable 1 bit size, and by disposing the output area of a plurality of these 1 bit sizes, formation has the driver portion of desired output number.In addition, 2 is the grid distribution that forms in the above-mentioned output area 1, abuts to form source region (S) and drain region (D) (with reference to the expanded view in the circle among the figure) with this grid with distribution 2.
In addition, be not limited to the shape of the grid shown in Figure 14 (a), for example, can also constitute grid distribution 2B, 2C, the 2D of the different shape shown in Figure 14 (b), (c), (d) with distribution 2.Like this, disposed repeatedly with the output number of necessity and in the said structure that forms by the wiring of output 1 bit size, when singualtion, corresponding further many requirements than specialization can't solve the inconvenience of distribution configuration and guarantee the problem of its configuration space.
Summary of the invention
Here, semiconductor device of the present invention and pattern wiring method thereof, it is characterized in that, by disposing in the semiconductor device that the driver drives of singualtion that a plurality of output areas that are equivalent to 1 bit constitute the output bit group of expectation uses, the peripheral part in chip disposes a plurality of output bit groups.
In addition, it is characterized in that, cooperate chip form to center on distribution with each distribution of exporting the bit line of above-mentioned peripheral part configuration.
And, semiconductor device of the present invention and pattern wiring method thereof, it is characterized in that, it is applicable to and makes the grade display driver driver of singualtion of driver and memory section, the output bit group of above-mentioned driver according to each issue prestige is being divided under the state of each group, with the peripheral part of output bit configuration set in chip, cooperate chip form to center on distribution with the distribution of respectively exporting in the bit group of respectively exporting the bit line of this peripheral part configuration.
In addition, above-mentioned driver is anode driver and cathode drive, this anode driver or the cathode drive output bit group according to each issue prestige is being divided under the state of each group, with the peripheral part of output bit configuration set in chip, cooperate chip form to center on distribution with the distribution of respectively exporting the bit line of this peripheral part configuration.
And, it is characterized in that above-mentioned distribution is power line and holding wire.And, it is characterized in that the above-mentioned bit group of respectively exporting is configured in this peripheral part round above-mentioned memory portion.
Description of drawings
Fig. 1 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Fig. 2 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Fig. 3 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Fig. 4 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Fig. 5 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Fig. 6 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Fig. 7 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Fig. 8 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Fig. 9 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Figure 10 is the sectional view of manufacture method of the semiconductor device of expression one embodiment of the present of invention.
Figure 11 is the plane graph of pattern wiring of the semiconductor device of expression one embodiment of the present of invention.
Figure 12 is the plane graph of pattern wiring of the semiconductor device of expression one embodiment of the present of invention.
Figure 13 is the plane graph of pattern wiring of the semiconductor device of expression other embodiment of the present invention.
Figure 14 is the plane graph of the pattern wiring of the traditional semiconductor device of expression.
Embodiment
Below, with reference to the embodiment of description of drawings semiconductor device of the present invention and pattern wiring method.In addition, in the present embodiment, be example with the OLED display, illustrate that constituting this organic EL display driver mixes the semiconductor device that forms with the various MOS transistor of driver.
Above-mentioned organic EL display driver driver, begin (for example 3V) N-channel MOS transistor and P channel MOS transistor by logical circuit series from the left side of Figure 10 (a), switching levels (for example 30V) N-channel MOS transistor, (for example 30V) N-channel MOS transistor of high withstand voltage series constitutes, and begins (for example 30V) the N-channel MOS transistor by the high withstand voltage series that realizes low on-resistanceization from the left side of Figure 10 (b), (for example 30V) P channel MOS transistor of high withstand voltage series, and (for example 30V) P channel MOS transistor of realizing the high withstand voltage series of low on-resistanceization constitutes.
In addition, so that distinguish the MOS transistor of the withstand voltage series of above-mentioned height and realize the MOS transistor of the high withstand voltage series of low on-resistanceization, will realize in the following description that the MOS transistor of the high withstand voltage series of low on-resistanceization is called SLED (Slitchannel by counter doping with extended shallow drain) MOS transistor for convenience of explanation.
Organic EL display driver like this mixes in the semiconductor device that forms with the various MOS transistor of driver, as shown in figure 10, the N type trap 23 that the P raceway groove SLEDMOS transistor of the P channel MOS transistor of the withstand voltage series of above-mentioned height and the high withstand voltage series of above-mentioned realization low on-resistanceization constitutes forms the high portion of section difference, the poor lower curtate of P type trap 22 transistors that other various MOS transistor constitute and the P channel MOS transistor section of being configured in and forming.
The manufacture method of above-mentioned semiconductor device below is described.
At first, among Fig. 1,, adopt the LOCOS method for example forming P type trap (PW) 22 and N type trap (NW) 23 in the P type semiconductor substrate (P-sub) 21 in order to divide the zone that constitutes various MOS transistor.That is, omit illustrated explanation, form on the zone at the N of above-mentioned substrate 21 type trap and form buffering (パ Star De) oxide-film and silicon nitride film, with this buffer oxide film and silicon nitride film as mask, with the accelerating voltage, 8 * 10 of boron ion about 80KeV
12/ cm
2Injection condition inject down, form ion implanted layer.Then, as mask, form the LOCOS film with above-mentioned silicon nitride film by LOCOS execution ground oxidation substrate surface.At this moment, the LOCOS film forms the boron ion that injects down in the zone and forms P type layer to the substrate diffusion inside.
Then, after removing above-mentioned buffer oxide film and silicon nitride film, with the LOCOS film as mask, the accelerating voltage about 80KeV, 9 * 10
12/ cm
2Injection condition under inject phosphonium ion to substrate surface, form ion implanted layer.Then, after removing above-mentioned LOCOS film, form P type trap and N type trap by making each foreign ion thermal diffusion of injecting above-mentioned substrate, as shown in Figure 1, P type trap 22 sections of the being configured in difference lower curtate that forms in the above-mentioned substrate 21, the high portion of N type trap 23 sections of being configured in difference.
Among Fig. 2,,, form the thick grid oxic horizon 25 of the high withstand voltage usefulness about 80nm on the active region beyond this element separating layer 24 by thermal oxidation by the element separating layer 24 about LOCOS method formation 500nm in order to separate each MOS transistor element.
Then, as mask, form the N type of first low concentration and P type source drain layer (below, be called LN layer 26, LP layer 27) with diaphragm.That is, at first, unshowned in the drawings diaphragm covering LN layer forms under the state in the zone beyond the zone, for example, and the accelerating voltage about 120KeV, 8 * 10
12/ cm
2Injection condition under inject phosphonium ion to the substrate top layer, form LN layer 26.Then, under the state in the zone beyond diaphragm (PR) covering LP layer forms the zone, the accelerating voltage about 120KeV, 8.5 * 10
12/ cm
2Injection condition under inject the boron ion to the substrate top layer, form LP layer 27.In addition, in fact, through the annealing operation of subsequent handling (1100 ℃ N for example
2Atmosphere, 2 hours) after, make the various ion thermal diffusions that above-mentioned ion implantation injects and form LN layer 26 and LP layer 27.
Then, among Fig. 3, between the above-mentioned LN layer 26 and LP layer 27 that forms in P raceway groove and N raceway groove SLEDMOS transistor formation region territory, as mask, form the N type of second low concentration and P type source drain layer (below, be called SLN layer 28 and SLP layer 29) with diaphragm.That is, at first, forming under the state in zone in addition, zone with not shown diaphragm covering SLN layer, for example, the accelerating voltage about 120KeV, 1.5 * 10
12/ cm
2Injection condition under inject phosphonium ion to the substrate top layer with ion implantation, form the SLN layer 28 be connected with above-mentioned LN layer 26.Then, forming under the state in zone in addition, zone with diaphragm (PR) covering SLP layer, for example, the accelerating voltage about 140KeV, 2.5 * 10
12/ cm
2Injection condition under to the substrate top layer with ion implantation inject the boron difluoride ion (
49BF
2 +), form the SLP layer 29 that is connected with above-mentioned LP layer 27.In addition, the impurity concentration of above-mentioned LN layer 26, above-mentioned LP layer 27 and above-mentioned SLN layer 28, above-mentioned SLP layer 29 is set for roughly the same or either party is higher.
And, among Fig. 4, as mask, form the N type of high concentration and P type source drain layer (below, be called N+ layer 30, P+ layer 31) with diaphragm.That is, at first, forming under the state in zone in addition, zone with not shown diaphragm covering N+ layer, for example, the accelerating voltage about 80KeV, 2 * 10
15/ cm
2Injection condition under inject phosphonium ion with ion implantation to the substrate top layer, form N+ layer 30.Then, under the state in the zone beyond diaphragm (PR) covering P+ layer forms the zone, the accelerating voltage about 140KeV, 2 * 10
15/ cm
2Injection condition under inject the boron difluoride ion with ion implantation to the substrate top layer, form P+ layer 31.
Then; among Fig. 5; form the mask open opening diaphragm directly that directly (with reference to Fig. 3) is narrower of usefulness as mask to have than above-mentioned SLN layer 28 and SLP layer 29; the middle body that reaches the SLP layer 29 that is connected with above-mentioned LP layer 27 by the middle body to the SLN layer 28 that is connected with above-mentioned LN layer 26 carries out the impurity that ion injects contrary conductivity type respectively, forms the P type body layer 32 and the N type body layer 33 of this SLN layer 28 of disjunction and SLP layer 29.That is, at first, forming under the state in zone in addition, zone with not shown diaphragm covering P type layer, for example, the accelerating voltage about 120KeV, 5 * 10
12/ cm
2Injection condition under inject boron difluoride ion ion with ion implantation to the substrate top layer, form P type body layer 32.Then, cover N type layer at diaphragm (PR) and form under the state in zone in addition, zone the accelerating voltage about 190KeV, 5 * 10
12/ cm
2Injection condition under inject phosphonium ion with ion implantation to the substrate top layer, form N type body layer 33.In addition, the process sequence of the ion injecting process of above-mentioned Fig. 3～shown in Figure 5 can appropriate change, at the fractal one-tenth raceway groove of skin section of above-mentioned P type body layer 32 and N type body layer 33.
And, among Fig. 6, formation 2P type trap (SPW) 34 and 2N type trap (SNW) 35 in the substrate (P type trap 22) that the N channel-type and the P channel type MOS transistor of the granular of above-mentioned common withstand voltage usefulness forms the zone.
That is, to form not shown diaphragm that the zone has opening in the N of above-mentioned common withstand voltage usefulness channel type MOS transistor as mask, the accelerating voltage about 190KeV, 1.5 * 10
13/ cm
2The 1st injection condition under in above-mentioned P type trap 22, inject the boron ion with ion implantation after, similarly, the accelerating voltage about 50KeV, 2.6 * 10
12/ cm
2The 2nd injection condition inject down the boron ion, form 2P type trap 34.In addition, to form diaphragm (PR) that the zone has opening in the P of above-mentioned common withstand voltage usefulness channel type MOS transistor as mask, the accelerating voltage about 380KeV, 1.5 * 10
13/ cm
2Injection condition under in above-mentioned P type trap 22, inject phosphonium ion with ion implantation, form 2N type trap 35.In addition, if there is not high accelerating voltage generating means about 380KeV, also can adopt accelerating voltage, 1.5 * 10 at 190KeV
13/ cm
2Injection condition under inject the double-charge mode of divalent phosphonium ion with ion implantation.Then, at the accelerating voltage, 4.0 * 10 of 140KeV
12/ cm
2Injection condition inject down phosphonium ion.
Then, after the N channel-type of removing common withstand voltage usefulness and P channel type MOS transistor form zone and level conversion and form above-mentioned grid oxidation film 25 on the zone with the N channel type MOS transistor, as shown in Figure 7, form the grid oxidation film of the thickness of new expectation in this zone.
That is, at first, by thermal oxidation, at whole grid oxidation film 36 that forms the 14nm that level conversion uses with the N channel type MOS transistor (is about 7nm in this stage, but in withstand voltage usually thickness increase when forming described later) with grid oxidation film.Then, remove after the N channel-type of common withstand voltage usefulness and P channel type MOS transistor form the zone and go up the grid oxidation film 36 of above-mentioned level conversion with the N channel type MOS transistor that forms, form the thin grid oxidation film 37 (about 7nm) of common withstand voltage usefulness by thermal oxidation in this zone.
Then, among Fig. 8, at whole polysilicon film that forms about 100nm, at this polysilicon film with POCl
3After carrying out thermal diffusion and conductionization as the thermal diffusion source, at the tungsten silicide film about stacked 100nm on this polysilicon film, the SiO about stacked again 150nm
2Film utilizes not shown diaphragm to form pattern, forms grid 38A, 38B, 38C, 38D, 38E, 38F, 38G that each MOS transistor is used.In addition, above-mentioned SiO
2Film plays hard mask when forming pattern.
Then, among Fig. 9, form the N channel-type of above-mentioned common withstand voltage usefulness and the low concentration source drain layer that the P channel type MOS transistor is used.
That is, at first, the low concentration source drain layer of using with the N channel type MOS transistor that covers common withstand voltage usefulness forms the not shown diaphragm in the zone beyond the zone as mask, for example, and the accelerating voltage about 20KeV, 6.2 * 10
13/ cm
2Injection condition under inject phosphonium ion with ion implantation, form the N type source drain layer 39 of low concentration.Then, the low concentration source drain layer of using with the P channel type MOS transistor that covers common withstand voltage usefulness forms the diaphragm (PR) in the zone beyond the zone as mask, for example, and the accelerating voltage about 20KeV, 2 * 10
13/ cm
2Injection condition under inject the boron difluoride ion with ion implantation, form the P type source drain layer 40 of low concentration.
And; among Figure 10; by the TEOS film 41 about LPCVD method formation 250nm; make it cover whole above-mentioned grid 38A, 38B, 38C, 38D, 38E, 38F, 38G; with form in the N of above-mentioned common withstand voltage usefulness channel-type and P channel type MOS transistor have opening on the zone diaphragm (PR) as mask, above-mentioned TEOS film is carried out anisotropic etching.Thereby as shown in figure 10, the two side portion of above-mentioned grid 38A, 38B forms sidewall separation membrane 41A, and in the zone that said protection film (PR) covers, TEOS film 41 is kept intact.
As mask, form the N channel-type of above-mentioned common withstand voltage usefulness and the high concentration source drain layer that the P channel type MOS transistor is used with above-mentioned grid 38A and sidewall separation membrane 41A and above-mentioned grid 38B and sidewall separation membrane 41A.
That is, the high concentration source drain layer of using with the N channel type MOS transistor that covers common withstand voltage usefulness forms the not shown diaphragm in the zone beyond the zone as mask, for example, and the accelerating voltage about 100KeV, 5 * 10
15/ cm
2Injection condition under inject arsenic ion with ion implantation, form the N+ type source drain layer 42 of high concentration.Then, the high concentration source drain layer of using with the P channel type MOS transistor that covers common withstand voltage usefulness forms the not shown diaphragm in the zone beyond the zone as mask, for example, and the accelerating voltage about 40KeV, 2 * 10
15/ cm
2Injection condition inject down the boron difluoride ion, form the P+ type source drain layer 43 of high concentration.
Below, omit illustrated explanation, by TEOS film and BPSG etc. behind whole interlayer dielectric that forms about 600nm, by the source drain layer 30 of formation with above-mentioned each high concentration, 31,42,43 connect the metallic wiring layer of contact, finish in order to constitute N-channel MOS transistor and the P channel MOS transistor of above-mentioned organic EL display driver with the common withstand voltage usefulness of driver, switching levels N-channel MOS transistor, the N-channel MOS transistor and the P channel MOS transistor of high withstand voltage usefulness, realize the N channel-type SLEDMOS transistor and the P channel-type SLEDMOS transistor (with reference to Figure 10) of the high withstand voltage usefulness of low on-resistanceization.
Here, the invention is characterized in, it be at display driver with driver, for example supply with constant current, make the luminous organic EL display driver of organic EL with in the driver etc. to organic EL (electroluminescent cell), the effective pattern wiring method during with singualtion such as the memory portion of anode driver, cathode drive, storage video data and controllers.
Below, with reference to description of drawings pattern wiring structure of the present invention.In addition, for fear of repeat specification and tradition (Figure 14) identical structure, use prosign and omit its explanation.
Among Figure 11,1 is the output area of suitable 1 bit size, constitute organic EL display driver with pattern wiring such as the various drivings of driver etc., dispose the output area of this 1 bit size repeatedly, constitute the output bit group of expectation by output variable with necessity with the semiconductor device of drivers.
In addition, form the grid distribution identical in the output area of above-mentioned 1 bit size with Figure 14.
Here, the invention is characterized in, with anode driver, cathode drive, memory portion and controller singualtion such as (omitting among the figure), upper left from the paper of Figure 11, dispose the anode driver zone 10 (section: SEG) of 32 bits, the cathode drive zone 11 (COM) of 128 bits, the anode driver zone 12 (SEG) of 32 bits, from the paper lower-left, dispose the anode driver zone 13 (SEG) of 32 bits, the icon of 10 bits anode driver zone 14 (icon SEG), the icon of 10 bits anode driver zone 15 (icon SEG), the anode driver zone 16 (SEG) of 32 bits.In addition, each driver region disposes the output area 1 that is equivalent to 1 bit size repeatedly by the output variable with necessity, constitutes the output bit group of expectation.
Like this, among the present invention, each driver region (anode driver zone 10, cathode drive zone 11, anode driver zone 12, anode driver zone 13, icon with anode driver zone 14, icon with anode driver zone 15 and anode driver zone 16) evenly is configured in the peripheral part in the chip, the memory portion 17,18 of the substantial middle part configuration store video data of this chip etc. and controller etc.In addition, along distributions 19 such as each driver region configuration power line, holding wires, this distribution 19 is connected with the output area of each 1 bit size.
As mentioned above, among the present invention, during with singualtion such as anode driver, cathode drive, memory portion and controllers, by cooperating chip form to center on configuration distributions such as power line, holding wire 19, can be on whole 4 directions the output of configuration driven device.
In addition, by memory portion and controller etc. being configured in the middle body of chip, can realizing good wiring efficiency and make the chip size downsizing.Promptly, as shown in figure 12, (present embodiment is a left-right symmetric to the symmetric position of chip middle body, configuration in the chip also can be a symmetry up and down) go up the memory portion 17,18 that configuration is formed by SRAM (static RAM (SRAM)), be connected with above-mentioned anode driver zone 10,12,13,16 respectively from the output distribution 20 of this memory portion 17,18.
Like this, among the present invention, memory portion 17,18 is configured on 4 interior directions of chip with the driver that is connected (present embodiment is an anode driver), memory portion is divided into two parts with each anode driver zone 10,12,13,16, the group in the anode driver zone 12,16 of the group in the anode driver zone 10,13 of the left end portion configuration of the corresponding chip of difference and the right end portion configuration of chip, it is easy that thereby the distribution that makes distribution 20 becomes, dwindle the distribution space, realize the downsizing of chip size.
Below, other wiring methods of each driver region that disposes in the chip are described with reference to Figure 13.In addition, Figure 13 (a) is the ideograph of the above-mentioned pattern wiring shown in Figure 12 of expression, the various variation of the configuration example of this Figure 13 (a) such as Figure 13 (b), (c), (d).In addition, for convenience, omitted memory portion.
At first, configuration example shown in Figure 13 (b), among Figure 13 (a), will be with respect to paper, become the anode driver zone 13 and 16 of upper-lower position to be configured to become 90 ℃ of adjacent angles respectively respectively with anode driver zone 10 and 12 with above-mentioned anode driver zone 10 and 12, and icon anode driver zone 14,15 is configured to adjacent respectively with anode driver zone 13 and 16.Thereby relatively the paper downside of chip forms the clear area of broad, degree of freedom increase when making other logical circuits parts of configuration and controller etc.
In addition, configuration example shown in Figure 13 (c), among Figure 13 (a), with icon with anode driver zone 14,15 and anode driver zone 13 and 16 respectively near configuration, and anode driver zone 10 and 12 is configured to become adjacent an angle of 90 degrees with anode driver zone 10 respectively with 12.Thereby, compare with Figure 13 (a), 13 (b), can realize the downsizing of chip size.
In addition, the configuration example shown in Figure 13 (d) be it seems not as the configuration example shown in Figure 13 (c) from the minification this point, but has identical size with the example of configuration shown in Figure 13 (a), 13 (b), can further realize comparing specialization more.In addition, 8,9,11A compares with anode driver zone and cathode drive zone among above-mentioned Figure 13 (a), 13 (b), 13 (c), how than the anode driver zone and the cathode drive zones of specialization.
In addition, display in the present embodiment is that example illustrates its driving driver with the OLED display, but the present invention is not limited to this, for example, also be applicable to the driving driver of LCD display, light-emitting diode display, inorganic EL display, PDP (plasma display), FED various flat-panel monitors such as (electroluminescent displays), also be applicable to and insert circuit repeatedly, determine in the purposes of bit number as required.
(effect of invention)
According to the present invention, driver region evenly is configured in the peripheral part in the chip, by Along distributions such as each driver region configuration power line, holding wires, make the configuration sky of distribution Between downsizing. By memory portion etc. being configured in the middle body of chip, can realize Good wiring efficiency also makes the chip size downsizing.
And, drive by the demonstration that is applied to have anode driver and cathode drive etc. Employ driver etc., can make their singualtion, realize downsizing and cost degradation.
Claims (12)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001061828A JP2002270693A (en) | 2001-03-06 | 2001-03-06 | Semiconductor device and pattern layout method thereof |
| JP61828/01 | 2001-03-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1374698A true CN1374698A (en) | 2002-10-16 |
| CN100517683C CN100517683C (en) | 2009-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021069557A Expired - Fee Related CN100517683C (en) | 2001-03-06 | 2002-03-06 | Semiconductor device and pattern wiring method thereof |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2002270693A (en) |
| KR (1) | KR20020071725A (en) |
| CN (1) | CN100517683C (en) |
| TW (1) | TW536826B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4683833B2 (en) | 2003-10-31 | 2011-05-18 | 株式会社半導体エネルギー研究所 | Functional circuit and design method thereof |
| JP4561247B2 (en) * | 2004-08-31 | 2010-10-13 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0265157A (en) * | 1988-08-30 | 1990-03-05 | Fujitsu Ltd | Master slice type semiconductor integrated circuit device |
| JP3235615B2 (en) * | 1990-04-24 | 2001-12-04 | セイコーエプソン株式会社 | Semiconductor chip package and display device using the same |
| KR950005462B1 (en) * | 1991-12-19 | 1995-05-24 | 삼성전자주식회사 | 4-terminal hybrid device composed of single chip and manufacturing method thereof |
| JPH05267626A (en) * | 1992-01-24 | 1993-10-15 | Toshiba Corp | Gate array circuit |
| JPH0689962A (en) * | 1992-02-28 | 1994-03-29 | Mega Chips:Kk | Semiconductor device |
| JP2616721B2 (en) * | 1994-11-22 | 1997-06-04 | 日本電気株式会社 | Semiconductor integrated circuit device |
| JP2000332201A (en) * | 1999-05-17 | 2000-11-30 | Mitsubishi Electric Corp | Semiconductor integrated circuit and manufacture thereof |
| JP4146613B2 (en) * | 2000-12-11 | 2008-09-10 | セイコーエプソン株式会社 | Semiconductor device |
-
2001
- 2001-03-06 JP JP2001061828A patent/JP2002270693A/en active Pending
-
2002
- 2002-01-31 TW TW091101620A patent/TW536826B/en not_active IP Right Cessation
- 2002-02-20 KR KR1020020008975A patent/KR20020071725A/en not_active Application Discontinuation
- 2002-03-06 CN CNB021069557A patent/CN100517683C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| TW536826B (en) | 2003-06-11 |
| KR20020071725A (en) | 2002-09-13 |
| CN100517683C (en) | 2009-07-22 |
| JP2002270693A (en) | 2002-09-20 |
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