CN1357920A - Flip Chip Conductive Bump and Redistribution Wire Layer Configuration - Google Patents

Abstract

A flip chip conductive bump and redistribution layer configuration at least comprises a plurality of power connection conductive bumps and grounding conductive bumps arranged in a honeycomb manner on the core of the flip chip, a plurality of power wires with 60-degree trend for connecting the power connection conductive bumps, and a plurality of grounding wires with 60-degree trend for connecting the grounding conductive bumps. Because the power wire and the grounding wire are respectively obliquely crossed with the power bus and the grounding bus of the metal inner connecting wire, the probability of crossing can be increased. Or the conductive bumps are arranged in an array, wherein the ground and power connection conductive bumps are arranged in a checkerboard-like staggered manner, or the conductive bumps are arranged in a staggered manner, and the ground and power connection conductive bumps can be connected with a ground wire and a power connection wire of 45 degrees, respectively. The grounding and power supply wires are located on the redistribution layer.

Description

Flip Chip Conductive Bump and Redistribution Wire Layer Configuration

technical field

The invention relates to an integrated circuit packaging technology, in particular to the configuration of the redistribution wire layer designed in response to the core voltage source bump and the ground bump of the flip-chip chip.

Background technique

With the generational replacement of very large integrated circuit process technology, a single chip, the function is enhanced, and the level of packaging technology has to be greatly improved accordingly. Traditional large-scale integrated circuits or medium-sized integrated circuits use a lead frame to connect the input and output ends of the chip or contact pads, or wire contact pads, and then use ceramic or resin molding packaging methods, which are not enough for ultra-large integrated circuits. , not to mention VLSI.

In the packaging method of connecting the contact pads with lead frames, in order to prevent the gold wires from being too long or the gold wires being shifted due to the injection of the packaging gel material, the contact pads can only be designed on the periphery of the device area of the chip. The components therefore require longer electrical leads to connect between the contact pads and the components. In addition, with the trend of single-chip function enhancement and high-speed performance requirements, the number of 1/0 pins is also increasing. The traditional method of connecting contact pads with bonding wires is accompanied by high inductance, which is not conducive to the high-speed operation of the chip, and can no longer meet the needs of future high-performance integrated circuits.

Therefore, an integrated circuit packaging technology called flip chip was born in response to the above-mentioned needs. This technology, as shown in FIG. 1, is to design a plurality of conductive bumps 24 on the uppermost layer of the wafer 20. Each conductive bump 24 is not limited to be formed around the wafer element area, but is formed in an array. are almost evenly distributed throughout the wafer 20 . Finally, the wafer 20 is turned over again, so that the conductive bumps 24 distributed in an array on the upper layer of the wafer face down and connect to the corresponding substrate 26 . The package substrate 26 has corresponding conductive bump pads (or flip-chip bump pads) 28 corresponding thereto in an array to receive the conductive bumps 24 .

There is not much variation within the die core due to the flip chip versus the wire contact pad die. When the chip system is designed as a wire contact pad chip, the contact pads are arranged around the chip (generally no components are allowed to exist below the contact pads), and the rest of the chip is covered with a protective layer. When the chip is designed as a flip-chip chip, a metal layer is formed on the protective layer of the original wire contact pad type chip, and a redistribution wire layer is formed through lithography and etching steps. The conductive bumps on the core of the chip can be connected to the conductive bumps at the surrounding wire contact pads in the chip. Therefore, as far as integrated circuit design companies are concerned, most of them still use the existing design tools for designing flip-chip chips corresponding to wire contact pads.

Traditionally, all conductive bumps are distributed in an array. In addition, regardless of whether the conductive bumps are signal or grounded or connected to the power supply voltage, multiple systems are mixed between the conductive bumps in each row and column. In this way, the signal wire bumps require a long connection wire, which is not conducive to speed performance. Therefore, US Patent No. 5,952,726 proposes to form the signal conductive bumps on the outer ring, and the core of the chip is set as the voltage source conductive bump VDD and the ground conductive bump VSS to make the conductive bumps VDD and VSS evenly distributed as much as possible. See the schematic diagram shown in Figure 2. The voltage bus bar 60 and the ground bus bar 70 of the redistribution wire layer are arranged in the upper and lower rows of the conductive bumps. Then, the conductive bump VDD is connected to the voltage source bus bar 60 and the conductive bump VSS is connected to the ground bus bar 70 by using the electric wires 65 and 75 respectively.

The above-mentioned U.S. patent also needs to reserve the connection position of the lead wire, and because it is still parallel to the power bus bar and the ground bus bar in the interconnection line, so the chance of intersection is reduced, and additional connection lines are required in addition to the interposer. , the redistribution layer also requires additional connection lines to connect the power lines to the power connection conductive bumps, and therefore, the density of the conductive bumps will be difficult to increase. The present invention proposes a method by which electrical leads can be lowered to reduce impedance.

In view of the fact that the signal conductive bumps, ground conductive bumps, and power conductive bumps in the traditional flip chip design are mixed among the array conductive bumps, or the power conductive bumps and ground conductive bumps are interlaced, and reused Distributed wire layer layout A plurality of wire layers distributed longitudinally or laterally along the array are connected to the conductive bumps. The above layout method has obvious disadvantages. For example, if the sum of the wire lengths of the redistribution wire layer layout is to be reduced, the grounding or power position of the wire layer below the redistribution wire layer must be restricted first, otherwise such horizontal or vertical wires in the redistribution wire layer will be Additional leads are required to connect to the signal bus, ground bus or power bus of the lower layers of wires. Therefore, not only the grounding or power supply conductive bumps require a long length of electric wire, but the impedance will be large. And also due to uneven distribution, the speed performance is further deteriorated. In addition, the conductive bumps in the prior art described in the Background of the Invention also need to reserve positions for connecting wires, so it is difficult to increase the density of the conductive bumps. The present invention will provide a solution to the above-mentioned problems.

Contents of the invention

The object of the present invention is to provide a conductive bump arrangement to reduce the total length of the wires in the redistribution wire layer, thereby lowering the resistance value.

Another object of the present invention is to provide the wires of the redistribution wire layer at an oblique angle to increase the chance of intersecting with the power bus bar and the ground bus bar in the interconnection line so as to reduce extra lead wires (or connection wires).

The purpose of the present invention is achieved like this:

A flip chip conductive bump and redistribution wire layer configuration, characterized in that it at least includes:

A plurality of power supply connection conductive bumps are arranged in a plurality of first longitudinal rows in an oblique direction;

A plurality of ground connection conductive bumps are arranged in a plurality of second longitudinal rows, and are obliquely parallel to the first longitudinal row, the most adjacent longitudinal row of the first longitudinal row is the second longitudinal row, and each power supply connection The conductive bump can form an equilateral triangle with the two most adjacent conductive bumps connected to the ground, and each conductive bump connected to the ground can also form an equilateral triangle with the two most adjacent conductive bumps connected to the power supply;

a plurality of power connection wires for connecting the power connection conductive bumps of the first column; and

A plurality of ground connection wires are used for connecting the power connection conductive bumps of the second column. as well as

The above-mentioned power connection wires and ground connection wires are the same layer of metal wires.

The metal wire layer of the above-mentioned power connection wire and the ground connection wire is a redistribution wire layer located under the conductive bump layer and is connected to the above-mentioned conductive bump through an interlayer.

The periphery of the above-mentioned first longitudinal row and second-level row further includes a plurality of conductive bumps arranged vertically alternately. or

A flip chip conductive bump and redistribution wire layer configuration, characterized in that it at least includes:

The ground connection conductive bumps and the power connection conductive bumps arranged in an array are formed on the core of the flip chip, and the array arrangement of the ground connection conductive bumps and the power connection conductive bumps is staggered in each horizontal row or vertical row Arranged and alternated with each other;

A plurality of power wires with a direction of approximately 45 degrees are used to connect the power connection conductive bumps. as well as

The above-mentioned power wires and ground wires are metal wires of the same layer.

The above-mentioned power wires and ground wires are redistribution wire layers located under the conductive bump layer, and are connected to the above-mentioned conductive bumps through interlayers. or

A flip chip conductive bump and redistribution wire layer configuration, characterized in that it at least includes:

A plurality of rows with grounding and power connection conductive bumps are arranged in a staggered manner on the core of the flip chip, and two adjacent rows are misaligned by half a unit distance from each other. The above-mentioned one unit distance refers to two adjacent grounding and power supply terminals Connect the spacing between the conductive bumps, so the straight line formed by the ground conductive bumps of adjacent rows intersects with the row at an angle of 45 degrees, and the straight line formed by the power connection conductive bumps of adjacent rows intersects the row with an angle of 45 degrees. degree angle;

a plurality of power conductors oriented at approximately 45 degrees for connecting to the power connection conductive bump; and

A plurality of grounding wires oriented at approximately 45 degrees are used to connect the grounding conductive bumps, so that the grounding wires and the power wires are interlaced with each other. as well as

The above-mentioned power wires and ground wires are metal wires of the same layer.

The metal wire layers of the above-mentioned power wires and ground wires are redistribution wire layers located under the conductive bump layer and are connected to the above-mentioned conductive bumps through interlayers.

Because the arrangement of conductive bumps and redistribution wiring layers of a flip chip disclosed by the present invention at least includes: a plurality of conductive bumps including power connection conductive bumps and ground conductive bumps are formed on the core of the flip chip in a honeycomb arrangement, and the plurality of A power wire with a direction of about 60° is used to connect the power connection conductive bump; and a plurality of ground wires with a direction of about 60° is used for connecting the ground conductive bump. Therefore, since the power wire and the ground wire are obliquely intersected with the power bus bar and the ground bus bar of the metal interconnection line respectively, the probability of intersection can be increased. Or the conductive bumps are arranged in an array, wherein the grounding and power supply are connected to the conductive bumps and arranged in a checkerboard pattern, or the conductive bumps are arranged in a staggered manner, and the grounding and power supply connecting conductive bumps can be connected to the ground wire at 45° and power connection. The above ground and power connections are located on the redistribution wire layer. Comparing the arrangement of the present invention with the arrangement of conventional conductive bumps, under the same pitch, the size or density of each conductive bump can be the largest or the highest density, without causing short circuit problems. Since the conductive bumps of the present invention are distributed in a staggered manner and the power lines or ground lines are oblique, the chance of intersecting with the voltage source bus bar or ground bus bar of the three-layer metal interconnection is increased, thereby reducing excess current. wire, the effect is equivalent to reducing the resistance value.

Description of drawings

FIG. 1 shows a flip-chip integrated circuit packaging technology, a schematic diagram of flip-chip bump pads corresponding to flip-chip bump pads on a substrate;

FIG. 2 is a schematic diagram showing the relationship between the conventional flip-chip conductive bump and the redistribution wiring layer;

FIG. 3 is a configuration diagram of the conductive bumps according to the first embodiment of the present invention, a schematic diagram of the same type of conductive bumps (P or G) slanted at 60°. The upper P line and the G line are used to connect the P conductive bump and the G conductive bump respectively;

Fig. 4 shows the relative relationship diagram between the electrical wires of the redistribution wire layer RDL layer and the metal interconnection wires MI, M2, M3 thereunder;

Fig. 5 shows the configuration diagram of the conductive bumps arranged in an array according to the second embodiment of the present invention, the conductive bumps (P or G) of the same type can be connected by the P line or the G line on the redistribution wiring layer RDL, and the 45 ° oblique;

Fig. 6 shows the configuration diagram of the conductive bumps of the third embodiment of the present invention, two adjacent rows are displaced by half the pitch of the conductive bumps, therefore, the redistribution wire layer RDL is used to connect the P conductive bumps and the G conductive bumps respectively The P line and the G line of the block are oblique at 45°. Part number description

20 Wafer 24 Conductive Bumps

26 Substrate 28 Conductive bump pad

60 Voltage bus bar 70 Ground bus bar

65, 75 Electric wires 100 Chip cores

110, 120, 130 conductive bump rows RDL redistribution wire layer

140a, 140b, 140c conductive bump pitch

P Voltage source conductive bump G Ground conductive bump

Detailed ways

The preferred embodiment of the present invention will be described in more detail with the help of the following figures in the following explanatory text:

The method provided by the present invention is a schematic diagram of the first embodiment shown in FIG. 3 . The common arrangement of conductive bumps arranged in an array at the core position of the flip-chip chip in the traditional method is changed to a row-to-row staggered arrangement. In addition, all signal conductive bumps have been moved to the periphery of the chip (not shown). The chip core 100 only has the voltage source conductive bump P and the ground conductive bump G.

Still as shown in FIG. 3 , the conductive bumps listed in the marked row 120 and the conductive bumps listed in the left adjacent vertical row 110 and the right adjacent vertical row 130 are alternately arranged. Moreover, the voltage source conductive bumps P and the ground conductive bumps G in each vertical row are also presented alternately. Moreover, the conductive bumps in each longitudinal row are arranged in a staggered manner, so that the distribution of P and G is more uniform. And if you look at the conductive bumps shown in FIG. 3 from an oblique angle, you can find that the conductive bumps P in adjacent columns can be connected to form a plurality of oblique straight lines (referred to as P lines), and the grounded conductive bump G can also be connected. Connect to form a plurality of oblique straight lines (referred to as G lines), and the G lines and P lines appear alternately, and they are arranged at an angle of 60° with the rows.

Taking the three-layer M3, M2 and M1 metal interconnection lines as an example, as shown in Figure 4, since the metal interconnection layers are generally distributed in horizontal or vertical rows, the oblique P line and G line and the above-mentioned M3, M2 and the voltage source bus or ground bus in the M1 metal interconnection will have more chances to intersect than the electrical conductors 60 and 70 connected by the conductive bumps of the crossbar array (as described in the background of the invention) Rendezvous. Because if the electric wire 60 or the electric wire 70 does not happen to intersect with the same horizontal or vertical metal interconnection (the voltage source bus bar or the ground bus bar, then they will not intersect except perpendicular to each other. And the conductive bumps of the present invention are staggered distribution and the power P line or ground G line is oblique. Therefore, it increases the chance of intersecting with the voltage source bus bar or ground bus bar of M3, M2 and M1 metal interconnection. When the conductive bump P or G respectively When it must be connected to the ground or power bus on one of the layers of M3, M2, and M1, it can be connected as long as a via hole is formed at the intersection point. Therefore, the excess electrical wires will be reduced, and the effect is equivalent to reducing the resistance value.

In particular, the honeycomb arrangement of the conductive bumps shown in FIG. 3 can make the pitches 140 a , 140 b , 140 c of the conductive bumps not only in the same direction, but also the smallest pitch. In other words, the highest number of conducting and distributing bumps can be laid out under the same chip core area. From another point of view, comparing the arrangement of the present invention with the arrangement of conventional conductive bumps, under the same pitch, each conductive bump can have the largest size or the highest density without causing short circuit problems.

Therefore, in response to the above-mentioned conductive bumps arranged at 60°, the voltage supply wires in the redistribution wire layer must also be wires inclined at about 60°, such as P wires and G wires.

Of course, in the present invention, some conductive bumps can also be arranged on the periphery of the above-mentioned 60° column conductive bumps in a traditional row and column, as indicated by the index 145 .

The second embodiment of the present invention is shown in FIG. 5 . Flip chip conductive bumps are arranged in a longitudinal direction (Y vertical axis) or a lateral direction (X axis). And the P or G of each horizontal row or vertical row are presented alternately. In this case, corresponding to the staggered (checkerboard) arrangement of the conductive bumps, no matter the P line or the G line, there are more meeting points than those parallel or perpendicular to the interconnection lines. Therefore, the purpose of reducing the total wire length of the redistribution wire layer can be achieved.

The third embodiment of the present invention is shown in FIG. 6 . The arrangement of conductive bumps in each longitudinal row of the flip chip is alternately distributed with adjacent rows. And the P or G of each longitudinal row is presented alternately. At this time, the part different from the first embodiment is a unit in which the conductive bumps in two adjacent columns are displaced by half in the longitudinal direction. The unit referred to here is the distance between two conductive bumps in the same row. Therefore, the connection between a certain conductive bump P in row B and the conductive bump P in row A and the conductive bump P in row C is 45°. ° inclined to the wale. Therefore, the corresponding P-line and G-line of the redistribution wire layer also have an oblique direction of 45°. Therefore, please note that when the two 45° inclinations are shown in Figure 5 and Figure 6, three adjacent conductive bumps (two conductive bumps P and one conductive bump P) can also be described by a vertical isosceles triangle. Bump G, or two conductive bumps G and one conductive bump P.

Claims (10)

1, a kind of overlay crystal chip conductive projection and redistribution lead wire layer configuration is characterized in that, comprises at least:

A plurality of power supplys connect conductive projection and are arranged as a plurality of first stringers with incline direction;

A plurality of ground connection connect conductive projection and are arranged as a plurality of second stringers, and oblique parallel is in this first stringer, the most adjoining stringer of this first stringer is this second stringer, and each power supply connection conductive projection can be connected conductive projection with two the most adjoining ground connection and form an equilateral triangle, and each ground connection connection conductive projection can be connected conductive projection with two power supplys the most adjoining equally and form an equilateral triangle;

A plurality of power supplys connect lead, connect conductive projection in order to the power supply that connects this first stringer; And

A plurality of ground connection connect lead, connect conductive projection in order to the power supply that connects this second stringer.

2, configuration as claimed in claim 1 is characterized in that, above-mentioned power supply connects lead and ground connection connects lead system with one deck plain conductor.

3, configuration as claimed in claim 2 is characterized in that, above-mentioned power supply connects plain conductor series of strata that lead and ground connection connects lead and is positioned at the redistribution lead wire layer under the conductive bump layer and connects the conductive projection of stating via interlayer.

4, configuration as claimed in claim 1 is characterized in that, the first above-mentioned stringer and the periphery of second level row more comprise the plural conductive projection that is mutual vertical arrangement.

5, a kind of overlay crystal chip conductive projection and redistribution lead wire layer configuration is characterized in that, comprises at least:

The ground connection of arrayed connects conductive projection and power supply connects the core that conductive projection is formed at this overlay crystal chip, and this ground connection connection conductive projection is connected conductive projection with power supply arrayed is all to be interlaced arrangements, alternately to present mutually in each line or stringer;

A plurality of power leads that are 45 degree trends connect conductive projection in order to connect this power supply.

6, configuration as claimed in claim 5 is characterized in that, above-mentioned power lead and earth lead are with one deck plain conductor.

7, configuration as claimed in claim 6 is characterized in that, above-mentioned power lead and earth lead are the redistribution lead wire layers that is positioned under the conductive bump layer, and connects the conductive projection of stating via interlayer.

8, a kind of overlay crystal chip conductive projection and redistribution lead wire layer configuration is characterized in that, comprises at least:

Plural number row has ground connection and power supply and connects conductive projection and be staggered and be formed at the core of this overlay crystal chip, and adjacent two rows are dislocation 1/2nd unit distances mutually, an above-mentioned unit distance is meant that ground connection that same row two is adjacent and power supply connect the spacing between conductive projection, so straight line and line that adjacent row's ground connection conductive projection is linked to be are intersected miter angle, straight line that the conductive projection of adjacent row's power supply connection simultaneously is linked to be and the crossing miter angle of line;

A plurality of power leads that are 45 degree trends connect conductive projection in order to connect this power supply; And

A plurality of earth leads that are 45 degree trends are in order to connect this ground connection conductive projection, and this earth lead and this power lead are therefore staggered each other to be presented.

9, configuration as claimed in claim 8 is characterized in that, above-mentioned power lead and earth lead are with one deck plain conductor.

10, configuration as claimed in claim 9 is characterized in that, the above-mentioned power lead and the metal carbonyl conducting layer of earth lead are to be positioned at the redistribution lead wire layer under the conductive bump layer and to connect the conductive projection of stating via interlayer.

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